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GET /api/patches/93286/?format=api
{ "id": 93286, "url": "https://patches.dpdk.org/api/patches/93286/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210517100002.19905-2-feifei.wang2@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210517100002.19905-2-feifei.wang2@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210517100002.19905-2-feifei.wang2@arm.com", "date": "2021-05-17T10:00:01", "name": "[v2,1/2] net/mlx4: remove unnecessary wmb for Memory Region cache", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "537322e1c0def79023c4e48b3084e8d1a124304e", "submitter": { "id": 1771, "url": "https://patches.dpdk.org/api/people/1771/?format=api", "name": "Feifei Wang", "email": "feifei.wang2@arm.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210517100002.19905-2-feifei.wang2@arm.com/mbox/", "series": [ { "id": 17004, "url": "https://patches.dpdk.org/api/series/17004/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17004", "date": "2021-05-17T10:00:00", "name": "remove wmb for net/mlx", "version": 2, "mbox": "https://patches.dpdk.org/series/17004/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/93286/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/93286/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E60D8A0A02;\n\tMon, 17 May 2021 12:00:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7581E41107;\n\tMon, 17 May 2021 12:00:16 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id B835941103\n for <dev@dpdk.org>; Mon, 17 May 2021 12:00:14 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3800A106F;\n Mon, 17 May 2021 03:00:14 -0700 (PDT)", "from net-x86-dell-8268.shanghai.arm.com\n (net-x86-dell-8268.shanghai.arm.com [10.169.210.111])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 256AC3F719;\n Mon, 17 May 2021 03:00:11 -0700 (PDT)" ], "From": "Feifei Wang <feifei.wang2@arm.com>", "To": "Matan Azrad <matan@nvidia.com>,\n\tShahaf Shuler <shahafs@nvidia.com>", "Cc": "dev@dpdk.org, nd@arm.com, Feifei Wang <feifei.wang2@arm.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>", "Date": "Mon, 17 May 2021 18:00:01 +0800", "Message-Id": "<20210517100002.19905-2-feifei.wang2@arm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210517100002.19905-1-feifei.wang2@arm.com>", "References": "<20210318071840.359957-1-feifei.wang2@arm.com>\n <20210517100002.19905-1-feifei.wang2@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 1/2] net/mlx4: remove unnecessary wmb for\n Memory Region cache", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "'dev_gen' is a variable to inform other cores to flush their local cache\nwhen global cache is rebuilt. It is unnecessary to add write memory\nbarrier (wmb) before or after its updating for synchronization.\n\nThis is due to MR cache's R/W lock can maintain synchronization between\nthreads:\n1. dev_gen and global cache update ordering inside the lock protected\nsection does not matter. Because other threads cannot take the lock\nuntil global cache has been updated. Thus, in out of order platform,\neven if other agents firstly observed updated dev_gen but global does\nnot update, they also needs to wait the lock. As a result, it is\nunnecessary to add a wmb between rebuiling global cache and updating\ndev_gen to keep the order of rebuilding global cache and updating\ndev_gen.\n\n2. Store-Release of unlock can provide the implicit wmb at the level\nvisible by software. This makes 'rebuiling global cache' and 'updating\ndev_gen' be observed before local_cache starts to be updated by other\nagents. Thus, wmb after 'updating dev_gen' can be removed.\n\nSuggested-by: Ruifeng Wang <ruifeng.wang@arm.com>\nSigned-off-by: Feifei Wang <feifei.wang2@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n drivers/net/mlx4/mlx4_mr.c | 13 +++++--------\n 1 file changed, 5 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4_mr.c b/drivers/net/mlx4/mlx4_mr.c\nindex 6b2f0cf187..9a396f5729 100644\n--- a/drivers/net/mlx4/mlx4_mr.c\n+++ b/drivers/net/mlx4/mlx4_mr.c\n@@ -948,18 +948,15 @@ mlx4_mr_mem_event_free_cb(struct rte_eth_dev *dev, const void *addr, size_t len)\n \tif (rebuild) {\n \t\tmr_rebuild_dev_cache(dev);\n \t\t/*\n-\t\t * Flush local caches by propagating invalidation across cores.\n-\t\t * rte_smp_wmb() is enough to synchronize this event. If one of\n-\t\t * freed memsegs is seen by other core, that means the memseg\n-\t\t * has been allocated by allocator, which will come after this\n-\t\t * free call. Therefore, this store instruction (incrementing\n-\t\t * generation below) will be guaranteed to be seen by other core\n-\t\t * before the core sees the newly allocated memory.\n+\t\t * No wmb is needed after updating dev_gen due to store-release of\n+\t\t * unlock can provide the implicit wmb at the level visible by\n+\t\t * software. This makes rebuilt global cache and updated dev_gen\n+\t\t * be observed when local_cache starts to be updating by other\n+\t\t * agents.\n \t\t */\n \t\t++priv->mr.dev_gen;\n \t\tDEBUG(\"broadcasting local cache flush, gen=%d\",\n \t\t priv->mr.dev_gen);\n-\t\trte_smp_wmb();\n \t}\n \trte_rwlock_write_unlock(&priv->mr.rwlock);\n #ifdef RTE_LIBRTE_MLX4_DEBUG\n", "prefixes": [ "v2", "1/2" ] }