Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92765/?format=api
{ "id": 92765, "url": "https://patches.dpdk.org/api/patches/92765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-6-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504210857.3398397-6-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504210857.3398397-6-matan@nvidia.com", "date": "2021-05-04T21:08:47", "name": "[v3,05/15] crypto/mlx5: support queue pairs operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "05b87c36999af2c31cadf9dcb6cff164b46d00c9", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210504210857.3398397-6-matan@nvidia.com/mbox/", "series": [ { "id": 16812, "url": "https://patches.dpdk.org/api/series/16812/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16812", "date": "2021-05-04T21:08:42", "name": "drivers: introduce mlx5 crypto PMD", "version": 3, "mbox": "https://patches.dpdk.org/series/16812/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92765/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92765/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 292A0A0A02;\n\tTue, 4 May 2021 23:10:06 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 43C094110A;\n\tTue, 4 May 2021 23:09:37 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n (mail-eopbgr760078.outbound.protection.outlook.com [40.107.76.78])\n by mails.dpdk.org (Postfix) with ESMTP id E771940697\n for <dev@dpdk.org>; Tue, 4 May 2021 23:09:35 +0200 (CEST)", "from CO1PR15CA0079.namprd15.prod.outlook.com (2603:10b6:101:20::23)\n by BN7PR12MB2723.namprd12.prod.outlook.com (2603:10b6:408:2d::30)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.38; Tue, 4 May\n 2021 21:09:33 +0000", "from CO1NAM11FT053.eop-nam11.prod.protection.outlook.com\n (2603:10b6:101:20:cafe::8d) by CO1PR15CA0079.outlook.office365.com\n (2603:10b6:101:20::23) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.25 via Frontend\n Transport; Tue, 4 May 2021 21:09:33 +0000", "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT053.mail.protection.outlook.com (10.13.175.63) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4087.27 via Frontend Transport; Tue, 4 May 2021 21:09:31 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 May\n 2021 21:09:29 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=UZoqw9syhB+Ti4i4LnzbKIpTwECMXRZnQENaLqLkYMyxkJ+VP3d1VCpbwlVIWTWSZ1h18keb4cQDeC6K4lwhk6lThfPKKKbQbnE0PQGdhdQQfeZRqDvT+9n5Gzi48FVQDN+1xC7S1xWoEi4h/HBdSEe7jwsS+5g6z1lvZgy6MnrS1fuu0cna9wzEoVvrOqThjXdcc7/Pm92SpQBRj1WiqR0+qw+kY/ThmDF1xRklMlucHIGdlWdpvhwvkAIZLEkGzs8lHkaw2CzC3xOKXiRN62+IS2Q4NIWbMAN3umjFGVr2FQm73kyEhzXtYr4dV76xXObEny6AY0s3RMfYjRFA1Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=9UUhfwDMdVyBLhH+xbwq1/hj/7gTljXP6St2/gfyEjM=;\n b=gLpNfU+cZYAkJ4uRsOl9OicwDSKYUrt6QG17wqdfO2pG1fbEk+Of69Ccw0TJdnoc+TCZENuf+009sw0IoYHGjMB4qkVx4+0K1tGwmMrP26jUm+HszdPpEFVmfAxba0DyM72v/9nBE+wNFuwrN5pvcxp1oTLC9jUd5khT4VPlo7Rrla0HZv0WSKV+xV7y/QYSmF5y+h0D3ECjMqYxV9typ/j6aDn2wTs/L7byzuLNN62VrtyjDoaDFz0dnhBdpaXDftGU/q27V53Fev1XglTJ49+2Wuw1uQ24e8LxCgNgo8mDyKAzJAFZL0Yry/r5mNCr7b2jAwEE64qS8XjnHciRDg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=9UUhfwDMdVyBLhH+xbwq1/hj/7gTljXP6St2/gfyEjM=;\n b=bcFmL98A0M0Y4BKY6Q+93++ePsQlinoMu6FCpkOQS0XbO/t32zRgJmAT2wFWvdLmzMd/74/4E+zXdEagLlKmURIYxiSIDJIXEYt9kMruv3E5tFqY81SlB+LoZsZNx6exr8L0Bp1sNvcmNXdObazOWv679fcdQqqSuKL9yZpe1u7j6L46DOi8kRFbIPmfesKWQO/t/R7cpMgcIdpRFneVLBA6FxXHOXxYJnTzY3YBoFWH/OCuO4FgUXkm0BHyPSNUorQrBcTTkvxDrMDHo2r+NkmQq5juSyA7PpMheD/7+uxN0++NXY5i08qrOWNnuBqGT5curRZO6B2UxzIOAw1Tyw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Thomas\n Monjalon\" <thomas@monjalon.net>, Shiri Kuzin <shirik@nvidia.com>", "Date": "Wed, 5 May 2021 00:08:47 +0300", "Message-ID": "<20210504210857.3398397-6-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210504210857.3398397-1-matan@nvidia.com>", "References": "<20210429154712.2820159-1-matan@nvidia.com>\n <20210504210857.3398397-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "aefe41b5-2e00-4dbd-83ef-08d90f40e93d", "X-MS-TrafficTypeDiagnostic": "BN7PR12MB2723:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN7PR12MB272331918449A129C4A9CB42DF5A9@BN7PR12MB2723.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2512;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n codMW0imTQibY+ojxCfo67504B6qgnQ9Cqxm6j67mGr0PZzc1W1qDDqLY6FluJqDLRyMkqkssGwN7QdqL44Q20HAPiiuOJGiPtGDs8iCzMgVCLkrrAhNQV+ux+0mUwLGoV68mBSE1tOzUiSi8CVRc9UXtCB6/z0OmtNT6XNrjaXzrNVHJEtUPJG5v/aJLKM1Ii+T7yJXvHMMq2JYTmRY22vpy6+j8M++rk6WTotAefyg8fGFTVkvdR8UDp7zuhYm6eIN1YdHKwZdlep9HqIx+HJTsC0h8QWSqLCqT+042DfK5/do00kO0bf9VxOAJjKWlUk94G6HExncSGGi6Fc5VMwS9UOBixPLi6DbtrBpFNd8LOUz+HGETcb+sWdhZtL1+hL7SU6GRY0HhTNdGm3/cExWsYYFU0QlO6CxFSqx/Hsr9+SPv7df8Yz7WpY5gKSOXgAn6GvbBkYfHoUaah4pR66ABV2yb+GVGbJV6sbPJ+9/gwPdwjUoXS49PjvGiizcvjhHmsBYQbnHsUEv0J0eD097sEz6gj10lx5nJ+aQoUDY0jnTC7jVzHxxSIENqCYfPS+M/7BFQVO52TwhyuWl5jrSvMJLzUY29LcFJDNNwJFNqwiPAnraguGH/zZ3qZRhVdVg3/hnJGYJ1g4XepJyzf+8Sq9kX47CviMblkDewFo=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(396003)(346002)(39860400002)(376002)(46966006)(36840700001)(107886003)(336012)(86362001)(2616005)(1076003)(478600001)(8676002)(36756003)(2906002)(82310400003)(36860700001)(6666004)(6916009)(70206006)(4326008)(26005)(70586007)(316002)(356005)(8936002)(7636003)(83380400001)(36906005)(7696005)(16526019)(47076005)(55016002)(82740400003)(186003)(5660300002)(54906003)(426003)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 21:09:31.3982 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aefe41b5-2e00-4dbd-83ef-08d90f40e93d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT053.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR12MB2723", "Subject": "[dpdk-dev] [PATCH v3 05/15] crypto/mlx5: support queue pairs\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nThe HW queue pairs are a pair of send queue and receive queue of\nindependent work queues packed together in one object for the purpose\nof transferring data between nodes of a network.\n\nCompletion Queue is a FIFO queue of completed work requests.\n\nIn crypto driver we use one QP in loopback in order to encrypt and\ndecrypt data locally without sending it to the wire.\nIn the configured QP we only use the SQ to perform the encryption and\ndecryption operations.\n\nAdded implementation for the QP setup function which creates the CQ,\ncreates the QP and changes its state to RTS (ready to send).\n\nAdded implementation for the release QP function to release all the QP\nresources.\n\nAdded the ops structure that contains any operation which is supported\nby the cryptodev.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 124 +++++++++++++++++++++++++++++-\n drivers/crypto/mlx5/mlx5_crypto.h | 11 +++\n 2 files changed, 133 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex cec21dbea7..8c3417ee96 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -7,6 +7,7 @@\n #include <rte_errno.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n+#include <rte_memory.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_common.h>\n@@ -184,6 +185,125 @@ mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,\n \tDRV_LOG(DEBUG, \"Session %p was cleared.\", sess_private_data);\n }\n \n+static int\n+mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\tif (qp->qp_obj != NULL)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp_obj));\n+\tif (qp->umem_obj != NULL)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n+\tif (qp->umem_buf != NULL)\n+\t\trte_free(qp->umem_buf);\n+\tmlx5_devx_cq_destroy(&qp->cq_obj);\n+\trte_free(qp);\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)\n+{\n+\t/*\n+\t * In Order to configure self loopback, when calling these functions the\n+\t * remote QP id that is used is the id of the same QP.\n+\t */\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to INIT state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTR state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t qp->qp_obj->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTS state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\t int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_devx_qp_attr attr = {0};\n+\tstruct mlx5_crypto_qp *qp;\n+\tuint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);\n+\tuint32_t umem_size = RTE_BIT32(log_nb_desc) *\n+\t\t\t MLX5_CRYPTO_WQE_SET_SIZE +\n+\t\t\t sizeof(*qp->db_rec) * 2;\n+\tuint32_t alloc_size = sizeof(*qp);\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n+\t};\n+\n+\talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n+\talloc_size += sizeof(struct rte_crypto_op *) * RTE_BIT32(log_nb_desc);\n+\tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (qp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate QP memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc,\n+\t\t\t\t&cq_attr, socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n+\t\tgoto error;\n+\t}\n+\tqp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id);\n+\tif (qp->umem_buf == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate QP umem.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (qp->umem_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n+\t\tgoto error;\n+\t}\n+\tattr.pd = priv->pdn;\n+\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n+\tattr.cqn = qp->cq_obj.cq->id;\n+\tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n+\tattr.rq_size = 0;\n+\tattr.sq_size = RTE_BIT32(log_nb_desc);\n+\tattr.dbr_umem_valid = 1;\n+\tattr.wq_umem_id = qp->umem_obj->umem_id;\n+\tattr.wq_umem_offset = 0;\n+\tattr.dbr_umem_id = qp->umem_obj->umem_id;\n+\tattr.dbr_address = RTE_BIT64(log_nb_desc) *\n+\t\t\t MLX5_CRYPTO_WQE_SET_SIZE;\n+\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tif (qp->qp_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n+\t\tgoto error;\n+\t}\n+\tqp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address);\n+\tif (mlx5_crypto_qp2rts(qp))\n+\t\tgoto error;\n+\tqp->ops = (struct rte_crypto_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n+\t\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\treturn 0;\n+error:\n+\tmlx5_crypto_queue_pair_release(dev, qp_id);\n+\treturn -1;\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= NULL,\n@@ -192,8 +312,8 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\n-\t.queue_pair_setup\t\t= NULL,\n-\t.queue_pair_release\t\t= NULL,\n+\t.queue_pair_setup\t\t= mlx5_crypto_queue_pair_setup,\n+\t.queue_pair_release\t\t= mlx5_crypto_queue_pair_release,\n \t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n \t.sym_session_configure\t\t= mlx5_crypto_sym_session_configure,\n \t.sym_session_clear\t\t= mlx5_crypto_sym_session_clear,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 5e270d3d5a..f5313b89f2 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -11,9 +11,11 @@\n #include <rte_cryptodev_pmd.h>\n \n #include <mlx5_common_utils.h>\n+#include <mlx5_common_devx.h>\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n+#define MLX5_CRYPTO_WQE_SET_SIZE 1024\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n@@ -27,6 +29,15 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev_config dev_config;\n };\n \n+struct mlx5_crypto_qp {\n+\tstruct mlx5_devx_cq cq_obj;\n+\tstruct mlx5_devx_obj *qp_obj;\n+\tstruct mlx5dv_devx_umem *umem_obj;\n+\tvoid *umem_buf;\n+\tvolatile uint32_t *db_rec;\n+\tstruct rte_crypto_op **ops;\n+};\n+\n struct mlx5_crypto_dek {\n \tstruct mlx5_hlist_entry entry; /* Pointer to DEK hash list entry. */\n \tstruct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */\n", "prefixes": [ "v3", "05/15" ] }