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GET /api/patches/92653/?format=api
{ "id": 92653, "url": "https://patches.dpdk.org/api/patches/92653/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-16-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-16-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-16-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:18", "name": "[v4,15/34] event/cnxk: add SSO GWS fastpath enqueue functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "96dce46d89068e4c6656a2f395dfd52b20969f01", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-16-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "https://patches.dpdk.org/api/series/16799/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/16799/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92653/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 534BAA0562;\n\tMon, 3 May 2021 17:24:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EE79041137;\n\tMon, 3 May 2021 17:23:41 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0C2B64117A\n for <dev@dpdk.org>; Mon, 3 May 2021 17:23:39 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FArtf032473; Mon, 3 May 2021 08:23:39 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv2e-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 03 May 2021 08:23:39 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:23:37 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:23:37 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 76DFC3F703F;\n Mon, 3 May 2021 08:23:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=PXPg161LfuF16O6MjhImUdHZ0DCiKB4Pvi4fVexjLkE=;\n b=WhbiYrauCvl6MI4Y9v1obqUnXStbVaXiwocOHC22X+0a1n1elAQ1N/ayMqTTBtZLKbqi\n WBojPdWtnGHdXivZskfhXwwXKuYQTVIeF4YQKHJggiDjseLG5FeQOblRp6BnseumYOq3\n s9uIlWR3us/qPuSCwyGOtMnaFTup99HKvBIY/5xswMbYmhAkCsE6zruEXQGUhnAzbKG0\n xPbSyG5UW29vTcq3vRM6c4cXGDFXd7icqGI+Dp56JNpYOihavyisAFQPWVxEN/lQxoCJ\n 6uhFgzU8PfNk1skxID11roaOCDKYrk8BmbWhEBl7bnsRVdJitLwihjHXaJzHKRBS6oeZ CQ==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:18 +0530", "Message-ID": "<20210503152238.2437-16-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "66pb4qr103cHra1GOmjAfu60d8HKt7ze", "X-Proofpoint-ORIG-GUID": "66pb4qr103cHra1GOmjAfu60d8HKt7ze", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 15/34] event/cnxk: add SSO GWS fastpath\n enqueue functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO GWS fastpath event device enqueue functions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 16 +++-\n drivers/event/cnxk/cn10k_worker.c | 54 ++++++++++++++\n drivers/event/cnxk/cn10k_worker.h | 12 +++\n drivers/event/cnxk/cn9k_eventdev.c | 25 ++++++-\n drivers/event/cnxk/cn9k_worker.c | 112 ++++++++++++++++++++++++++++\n drivers/event/cnxk/cn9k_worker.h | 24 ++++++\n 6 files changed, 241 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 6522351ca..a1b44744b 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -2,7 +2,9 @@\n * Copyright(C) 2021 Marvell.\n */\n \n+#include \"cn10k_worker.h\"\n #include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n \n static void\n cn10k_init_hws_ops(struct cn10k_sso_hws *ws, uintptr_t base)\n@@ -130,6 +132,16 @@ cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)\n \treturn roc_sso_rsrc_init(&dev->sso, hws, hwgrp);\n }\n \n+static void\n+cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n+{\n+\tPLT_SET_USED(event_dev);\n+\tevent_dev->enqueue = cn10k_sso_hws_enq;\n+\tevent_dev->enqueue_burst = cn10k_sso_hws_enq_burst;\n+\tevent_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;\n+\tevent_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;\n+}\n+\n static void\n cn10k_sso_info_get(struct rte_eventdev *event_dev,\n \t\t struct rte_event_dev_info *dev_info)\n@@ -276,8 +288,10 @@ cn10k_sso_init(struct rte_eventdev *event_dev)\n \n \tevent_dev->dev_ops = &cn10k_sso_dev_ops;\n \t/* For secondary processes, the primary has done all the work */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\tcn10k_sso_fp_fns_set(event_dev);\n \t\treturn 0;\n+\t}\n \n \trc = cnxk_sso_init(event_dev);\n \tif (rc < 0)\ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex 63b587301..9b5cb7be6 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -5,3 +5,57 @@\n #include \"cn10k_worker.h\"\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n+\n+uint16_t __rte_hot\n+cn10k_sso_hws_enq(void *port, const struct rte_event *ev)\n+{\n+\tstruct cn10k_sso_hws *ws = port;\n+\n+\tswitch (ev->op) {\n+\tcase RTE_EVENT_OP_NEW:\n+\t\treturn cn10k_sso_hws_new_event(ws, ev);\n+\tcase RTE_EVENT_OP_FORWARD:\n+\t\tcn10k_sso_hws_forward_event(ws, ev);\n+\t\tbreak;\n+\tcase RTE_EVENT_OP_RELEASE:\n+\t\tcnxk_sso_hws_swtag_flush(ws->tag_wqe_op, ws->swtag_flush_op);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+uint16_t __rte_hot\n+cn10k_sso_hws_enq_burst(void *port, const struct rte_event ev[],\n+\t\t\tuint16_t nb_events)\n+{\n+\tRTE_SET_USED(nb_events);\n+\treturn cn10k_sso_hws_enq(port, ev);\n+}\n+\n+uint16_t __rte_hot\n+cn10k_sso_hws_enq_new_burst(void *port, const struct rte_event ev[],\n+\t\t\t uint16_t nb_events)\n+{\n+\tstruct cn10k_sso_hws *ws = port;\n+\tuint16_t i, rc = 1;\n+\n+\tfor (i = 0; i < nb_events && rc; i++)\n+\t\trc = cn10k_sso_hws_new_event(ws, &ev[i]);\n+\n+\treturn nb_events;\n+}\n+\n+uint16_t __rte_hot\n+cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n+\t\t\t uint16_t nb_events)\n+{\n+\tstruct cn10k_sso_hws *ws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\tcn10k_sso_hws_forward_event(ws, ev);\n+\n+\treturn 1;\n+}\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 04517055d..48158b320 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -148,4 +148,16 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \treturn !!gw.u64[1];\n }\n \n+/* CN10K Fastpath functions. */\n+uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev);\n+uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+\n #endif\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 00c5565e7..61a4d0823 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -2,7 +2,9 @@\n * Copyright(C) 2021 Marvell.\n */\n \n+#include \"cn9k_worker.h\"\n #include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n \n #define CN9K_DUAL_WS_NB_WS\t 2\n #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)\n@@ -150,6 +152,25 @@ cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)\n \treturn roc_sso_rsrc_init(&dev->sso, hws, hwgrp);\n }\n \n+static void\n+cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\n+\tevent_dev->enqueue = cn9k_sso_hws_enq;\n+\tevent_dev->enqueue_burst = cn9k_sso_hws_enq_burst;\n+\tevent_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;\n+\tevent_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;\n+\n+\tif (dev->dual_ws) {\n+\t\tevent_dev->enqueue = cn9k_sso_hws_dual_enq;\n+\t\tevent_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst;\n+\t\tevent_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;\n+\t\tevent_dev->enqueue_forward_burst =\n+\t\t\tcn9k_sso_hws_dual_enq_fwd_burst;\n+\t}\n+}\n+\n static void *\n cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)\n {\n@@ -349,8 +370,10 @@ cn9k_sso_init(struct rte_eventdev *event_dev)\n \n \tevent_dev->dev_ops = &cn9k_sso_dev_ops;\n \t/* For secondary processes, the primary has done all the work */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\tcn9k_sso_fp_fns_set(event_dev);\n \t\treturn 0;\n+\t}\n \n \trc = cnxk_sso_init(event_dev);\n \tif (rc < 0)\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex 836914163..538bc4b0b 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -5,3 +5,115 @@\n #include \"roc_api.h\"\n \n #include \"cn9k_worker.h\"\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_enq(void *port, const struct rte_event *ev)\n+{\n+\tstruct cn9k_sso_hws *ws = port;\n+\n+\tswitch (ev->op) {\n+\tcase RTE_EVENT_OP_NEW:\n+\t\treturn cn9k_sso_hws_new_event(ws, ev);\n+\tcase RTE_EVENT_OP_FORWARD:\n+\t\tcn9k_sso_hws_forward_event(ws, ev);\n+\t\tbreak;\n+\tcase RTE_EVENT_OP_RELEASE:\n+\t\tcnxk_sso_hws_swtag_flush(ws->tag_op, ws->swtag_flush_op);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_enq_burst(void *port, const struct rte_event ev[],\n+\t\t uint16_t nb_events)\n+{\n+\tRTE_SET_USED(nb_events);\n+\treturn cn9k_sso_hws_enq(port, ev);\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_enq_new_burst(void *port, const struct rte_event ev[],\n+\t\t\t uint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws *ws = port;\n+\tuint16_t i, rc = 1;\n+\n+\tfor (i = 0; i < nb_events && rc; i++)\n+\t\trc = cn9k_sso_hws_new_event(ws, &ev[i]);\n+\n+\treturn nb_events;\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n+\t\t\t uint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws *ws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\tcn9k_sso_hws_forward_event(ws, ev);\n+\n+\treturn 1;\n+}\n+\n+/* Dual ws ops. */\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_dual_enq(void *port, const struct rte_event *ev)\n+{\n+\tstruct cn9k_sso_hws_dual *dws = port;\n+\tstruct cn9k_sso_hws_state *vws;\n+\n+\tvws = &dws->ws_state[!dws->vws];\n+\tswitch (ev->op) {\n+\tcase RTE_EVENT_OP_NEW:\n+\t\treturn cn9k_sso_hws_dual_new_event(dws, ev);\n+\tcase RTE_EVENT_OP_FORWARD:\n+\t\tcn9k_sso_hws_dual_forward_event(dws, vws, ev);\n+\t\tbreak;\n+\tcase RTE_EVENT_OP_RELEASE:\n+\t\tcnxk_sso_hws_swtag_flush(vws->tag_op, vws->swtag_flush_op);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_dual_enq_burst(void *port, const struct rte_event ev[],\n+\t\t\t uint16_t nb_events)\n+{\n+\tRTE_SET_USED(nb_events);\n+\treturn cn9k_sso_hws_dual_enq(port, ev);\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_dual_enq_new_burst(void *port, const struct rte_event ev[],\n+\t\t\t\tuint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws_dual *dws = port;\n+\tuint16_t i, rc = 1;\n+\n+\tfor (i = 0; i < nb_events && rc; i++)\n+\t\trc = cn9k_sso_hws_dual_new_event(dws, &ev[i]);\n+\n+\treturn nb_events;\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n+\t\t\t\tuint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws_dual *dws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\tcn9k_sso_hws_dual_forward_event(dws, &dws->ws_state[!dws->vws], ev);\n+\n+\treturn 1;\n+}\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex 85be742c1..aa321d0e4 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -246,4 +246,28 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \treturn !!gw.u64[1];\n }\n \n+/* CN9K Fastpath functions. */\n+uint16_t __rte_hot cn9k_sso_hws_enq(void *port, const struct rte_event *ev);\n+uint16_t __rte_hot cn9k_sso_hws_enq_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+\n+uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port,\n+\t\t\t\t\t const struct rte_event *ev);\n+uint16_t __rte_hot cn9k_sso_hws_dual_enq_burst(void *port,\n+\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port,\n+\t\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n+\t\t\t\t\t\t const struct rte_event ev[],\n+\t\t\t\t\t\t uint16_t nb_events);\n+\n #endif\n", "prefixes": [ "v4", "15/34" ] }