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GET /api/patches/92614/?format=api
{ "id": 92614, "url": "https://patches.dpdk.org/api/patches/92614/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1619895841-7467-26-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1619895841-7467-26-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1619895841-7467-26-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-05-01T19:04:00", "name": "[v5,25/26] event/dlb2: move rte config defines to runtime devargs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b18cc01b5d339e8b94c7d1bc801f407bbd4eacd9", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1619895841-7467-26-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16784, "url": "https://patches.dpdk.org/api/series/16784/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16784", "date": "2021-05-01T19:03:37", "name": "Add DLB v2.5", "version": 5, "mbox": "https://patches.dpdk.org/series/16784/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92614/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92614/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1E260A0546;\n\tSat, 1 May 2021 21:08:39 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1AED841296;\n\tSat, 1 May 2021 21:06:11 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 6F20241183\n for <dev@dpdk.org>; Sat, 1 May 2021 21:05:44 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2021 12:05:43 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga002.fm.intel.com with ESMTP; 01 May 2021 12:05:43 -0700" ], "IronPort-SDR": [ "\n VqDgLh0j2iTHovzOS8qg/NQsWqbamiqXmM96jHiPAd1l2VyrentIvAOB4VTJ7lUtFIoX5SfiPO\n HvbWv4bR/72w==", "\n dJAAf2Hll4Pn0cB/gI/Rh49FgGIbbtEsrwe36V+99VfqXCBoNeLVyRWGY/g7gInAQHD2Ns0lUm\n f2K/SchJp5Tg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9971\"; a=\"282865206\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"282865206\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"460767102\"" ], "X-ExtLoop1": "1", "From": "\"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net,\n Timothy McDaniel <timothy.mcdaniel@intel.com>", "Date": "Sat, 1 May 2021 14:04:00 -0500", "Message-Id": "<1619895841-7467-26-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 25/26] event/dlb2: move rte config defines to\n runtime devargs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Timothy McDaniel <timothy.mcdaniel@intel.com>\n\nThe new devarg names and their default values\nare listed below. The defaults have not changed, and\nnone of these parameters are accessed in the fast path.\n\npoll_interval=1000\nsw_credit_quantai=32\ndefault_depth_thresh=256\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n config/rte_config.h | 4 --\n drivers/event/dlb2/dlb2.c | 122 ++++++++++++++++++++++++++++----\n drivers/event/dlb2/dlb2_priv.h | 14 ++++\n drivers/event/dlb2/pf/dlb2_pf.c | 5 +-\n 4 files changed, 125 insertions(+), 20 deletions(-)", "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex b13c0884b..590903c07 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -140,10 +140,6 @@\n #define RTE_LIBRTE_QEDE_FW \"\"\n \n /* DLB2 defines */\n-#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000\n-#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE 0\n #undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS\n-#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32\n-#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256\n \n #endif /* _RTE_CONFIG_H_ */\ndiff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex cc6495b76..818b1c367 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -315,6 +315,66 @@ set_cos(const char *key __rte_unused,\n \treturn 0;\n }\n \n+static int\n+set_poll_interval(const char *key __rte_unused,\n+\tconst char *value,\n+\tvoid *opaque)\n+{\n+\tint *poll_interval = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(poll_interval, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_sw_credit_quanta(const char *key __rte_unused,\n+\tconst char *value,\n+\tvoid *opaque)\n+{\n+\tint *sw_credit_quanta = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(sw_credit_quanta, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_default_depth_thresh(const char *key __rte_unused,\n+\tconst char *value,\n+\tvoid *opaque)\n+{\n+\tint *default_depth_thresh = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(default_depth_thresh, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n static int\n set_qid_depth_thresh(const char *key __rte_unused,\n \t\t const char *value,\n@@ -667,15 +727,8 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)\n \t}\n \n \t/* Does this platform support umonitor/umwait? */\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {\n-\t\tif (RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 0 &&\n-\t\t RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 1) {\n-\t\t\tDLB2_LOG_ERR(\"invalid value (%d) for RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE, must be 0 or 1.\\n\",\n-\t\t\t\t RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE);\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG))\n \t\tdlb2->umwait_allowed = true;\n-\t}\n \n \trsrcs->num_dir_ports = config->nb_single_link_event_port_queues;\n \trsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;\n@@ -930,8 +983,9 @@ dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2,\n \t}\n \n \tif (ev_queue->depth_threshold == 0) {\n-\t\tcfg.depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;\n-\t\tev_queue->depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;\n+\t\tcfg.depth_threshold = dlb2->default_depth_thresh;\n+\t\tev_queue->depth_threshold =\n+\t\t\tdlb2->default_depth_thresh;\n \t} else\n \t\tcfg.depth_threshold = ev_queue->depth_threshold;\n \n@@ -1623,7 +1677,7 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev,\n \t\t RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);\n \tev_port->outstanding_releases = 0;\n \tev_port->inflight_credits = 0;\n-\tev_port->credit_update_quanta = RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA;\n+\tev_port->credit_update_quanta = dlb2->sw_credit_quanta;\n \tev_port->dlb2 = dlb2; /* reverse link */\n \n \t/* Tear down pre-existing port->queue links */\n@@ -1718,8 +1772,9 @@ dlb2_hw_create_dir_queue(struct dlb2_eventdev *dlb2,\n \tcfg.port_id = qm_port_id;\n \n \tif (ev_queue->depth_threshold == 0) {\n-\t\tcfg.depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;\n-\t\tev_queue->depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;\n+\t\tcfg.depth_threshold = dlb2->default_depth_thresh;\n+\t\tev_queue->depth_threshold =\n+\t\t\tdlb2->default_depth_thresh;\n \t} else\n \t\tcfg.depth_threshold = ev_queue->depth_threshold;\n \n@@ -2747,7 +2802,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \tDLB2_INC_STAT(ev_port->stats.tx_op_cnt[ev->op], 1);\n \tDLB2_INC_STAT(ev_port->stats.traffic.tx_ok, 1);\n \n-#ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS\n+#ifndef RTE_LIBRTE_PMD_DLB_QUELL_STATS\n \tif (ev->op != RTE_EVENT_OP_RELEASE) {\n \t\tDLB2_INC_STAT(ev_port->stats.queue[ev->queue_id].enq_ok, 1);\n \t\tDLB2_INC_STAT(ev_port->stats.tx_sched_cnt[*sched_type], 1);\n@@ -3070,7 +3125,7 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,\n \n \t\tDLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);\n \t} else {\n-\t\tuint64_t poll_interval = RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL;\n+\t\tuint64_t poll_interval = dlb2->poll_interval;\n \t\tuint64_t curr_ticks = rte_get_timer_cycles();\n \t\tuint64_t init_ticks = curr_ticks;\n \n@@ -4025,6 +4080,9 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \tdlb2->max_num_events_override = dlb2_args->max_num_events;\n \tdlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;\n \tdlb2->qm_instance.cos_id = dlb2_args->cos_id;\n+\tdlb2->poll_interval = dlb2_args->poll_interval;\n+\tdlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta;\n+\tdlb2->default_depth_thresh = dlb2_args->default_depth_thresh;\n \n \terr = dlb2_iface_open(&dlb2->qm_instance, name);\n \tif (err < 0) {\n@@ -4125,6 +4183,9 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DEV_ID_ARG,\n \t\t\t\t\t DLB2_QID_DEPTH_THRESH_ARG,\n \t\t\t\t\t DLB2_COS_ARG,\n+\t\t\t\t\t DLB2_POLL_INTERVAL_ARG,\n+\t\t\t\t\t DLB2_SW_CREDIT_QUANTA_ARG,\n+\t\t\t\t\t DLB2_DEPTH_THRESH_ARG,\n \t\t\t\t\t NULL };\n \n \tif (params != NULL && params[0] != '\\0') {\n@@ -4207,6 +4268,37 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_POLL_INTERVAL_ARG,\n+\t\t\t\t\t\t set_poll_interval,\n+\t\t\t\t\t\t &dlb2_args->poll_interval);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing poll interval parameter\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\t\t DLB2_SW_CREDIT_QUANTA_ARG,\n+\t\t\t\t\t\t set_sw_credit_quanta,\n+\t\t\t\t\t\t &dlb2_args->sw_credit_quanta);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing sw xredit quanta parameter\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist, DLB2_DEPTH_THRESH_ARG,\n+\t\t\t\t\tset_default_depth_thresh,\n+\t\t\t\t\t&dlb2_args->default_depth_thresh);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing set depth thresh parameter\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n \t\t\trte_kvargs_free(kvlist);\n \t\t}\n \t}\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex f3a9fe0aa..cf120c92d 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -22,6 +22,11 @@\n \n #define EVDEV_DLB2_NAME_PMD dlb2_event\n \n+/* Default values for command line devargs */\n+#define DLB2_POLL_INTERVAL_DEFAULT 1000\n+#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32\n+#define DLB2_DEPTH_THRESH_DEFAULT 256\n+\n /* command line arg strings */\n #define NUMA_NODE_ARG \"numa_node\"\n #define DLB2_MAX_NUM_EVENTS \"max_num_events\"\n@@ -30,6 +35,9 @@\n #define DLB2_DEFER_SCHED_ARG \"defer_sched\"\n #define DLB2_QID_DEPTH_THRESH_ARG \"qid_depth_thresh\"\n #define DLB2_COS_ARG \"cos\"\n+#define DLB2_POLL_INTERVAL_ARG \"poll_interval\"\n+#define DLB2_SW_CREDIT_QUANTA_ARG \"sw_credit_quanta\"\n+#define DLB2_DEPTH_THRESH_ARG \"default_depth_thresh\"\n \n /* Begin HW related defines and structs */\n \n@@ -570,6 +578,9 @@ struct dlb2_eventdev {\n \tbool global_dequeue_wait; /* Not using per dequeue wait if true */\n \tbool defer_sched;\n \tenum dlb2_cq_poll_modes poll_mode;\n+\tint poll_interval;\n+\tint sw_credit_quanta;\n+\tint default_depth_thresh;\n \tuint8_t revision;\n \tuint8_t version;\n \tbool configured;\n@@ -603,6 +614,9 @@ struct dlb2_devargs {\n \tint defer_sched;\n \tstruct dlb2_qid_depth_thresholds qid_depth_thresholds;\n \tenum dlb2_cos cos_id;\n+\tint poll_interval;\n+\tint sw_credit_quanta;\n+\tint default_depth_thresh;\n };\n \n /* End Eventdev related defines and structs */\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex f57dc1584..e9da89d65 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -615,7 +615,10 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n \t\t.num_dir_credits_override = -1,\n \t\t.qid_depth_thresholds = { {0} },\n-\t\t.cos_id = DLB2_COS_DEFAULT\n+\t\t.cos_id = DLB2_COS_DEFAULT,\n+\t\t.poll_interval = DLB2_POLL_INTERVAL_DEFAULT,\n+\t\t.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,\n+\t\t.default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT\n \t};\n \tstruct dlb2_eventdev *dlb2;\n \n", "prefixes": [ "v5", "25/26" ] }