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GET /api/patches/92591/?format=api
{ "id": 92591, "url": "https://patches.dpdk.org/api/patches/92591/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1619895841-7467-2-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1619895841-7467-2-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1619895841-7467-2-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-05-01T19:03:36", "name": "[v5,01/26] event/dlb2: minor code cleanup", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0cf27b5afc640dc7979c6802347a3b505b9f9583", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1619895841-7467-2-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16784, "url": "https://patches.dpdk.org/api/series/16784/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16784", "date": "2021-05-01T19:03:37", "name": "Add DLB v2.5", "version": 5, "mbox": "https://patches.dpdk.org/series/16784/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92591/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92591/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 69560A0546;\n\tSat, 1 May 2021 21:05:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7C132410DA;\n\tSat, 1 May 2021 21:05:36 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id EB13A40140\n for <dev@dpdk.org>; Sat, 1 May 2021 21:05:32 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2021 12:05:29 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga002.fm.intel.com with ESMTP; 01 May 2021 12:05:29 -0700" ], "IronPort-SDR": [ "\n 0CwVUx5fAsIYUuOz3Wuudet4rQ8oKdJwEqNh3xEZF6qIDG4WXz0PBIvWEXMeuAZ7po/D9Wgnfk\n JLAf8kt97o8w==", "\n ZgCjFusC2sSYSD2i2yktkK6PzE7/OhcF4Dybmu4FigxcejGsZ80xVh1O+AtkxllygQW9CMVL67\n VjeG7/76yScg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9971\"; a=\"282865175\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"282865175\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"460766990\"" ], "X-ExtLoop1": "1", "From": "\"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net,\n Timothy McDaniel <timothy.mcdaniel@intel.com>", "Date": "Sat, 1 May 2021 14:03:36 -0500", "Message-Id": "<1619895841-7467-2-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 01/26] event/dlb2: minor code cleanup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Timothy McDaniel <timothy.mcdaniel@intel.com>\n\n1) Remove references to FPGA.\n2) Do not include dlb2_mbox.h, it is not needed.\n3) Remove duplicate macros/defines that were\n present in both dlb2_priv.h and dlb2_hw_types.h.\n Update dlb2_resource.c to include dlb2_priv.h\n so that it picks up the macros/defines that\n have now been consolidated.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_hw_types.h | 46 +-\n drivers/event/dlb2/pf/base/dlb2_mbox.h | 596 ---------------------\n drivers/event/dlb2/pf/base/dlb2_resource.c | 1 -\n 3 files changed, 2 insertions(+), 641 deletions(-)\n delete mode 100644 drivers/event/dlb2/pf/base/dlb2_mbox.h", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nindex 1d99f1e01..c7cd41f8b 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -5,55 +5,25 @@\n #ifndef __DLB2_HW_TYPES_H\n #define __DLB2_HW_TYPES_H\n \n+#include \"../../dlb2_priv.h\"\n #include \"dlb2_user.h\"\n \n #include \"dlb2_osdep_list.h\"\n #include \"dlb2_osdep_types.h\"\n \n #define DLB2_MAX_NUM_VDEVS\t\t\t16\n-#define DLB2_MAX_NUM_DOMAINS\t\t\t32\n-#define DLB2_MAX_NUM_LDB_QUEUES\t\t\t32 /* LDB == load-balanced */\n-#define DLB2_MAX_NUM_DIR_QUEUES\t\t\t64 /* DIR == directed */\n-#define DLB2_MAX_NUM_LDB_PORTS\t\t\t64\n-#define DLB2_MAX_NUM_DIR_PORTS\t\t\t64\n-#define DLB2_MAX_NUM_LDB_CREDITS\t\t(8 * 1024)\n-#define DLB2_MAX_NUM_DIR_CREDITS\t\t(2 * 1024)\n-#define DLB2_MAX_NUM_HIST_LIST_ENTRIES\t\t2048\n #define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n-#define DLB2_MAX_NUM_QIDS_PER_LDB_CQ\t\t8\n #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n #define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n-#define DLB2_QID_PRIORITIES\t\t\t8\n+\n #define DLB2_NUM_ARB_WEIGHTS\t\t\t8\n #define DLB2_MAX_WEIGHT\t\t\t\t255\n #define DLB2_NUM_COS_DOMAINS\t\t\t4\n #define DLB2_MAX_CQ_COMP_CHECK_LOOPS\t\t409600\n #define DLB2_MAX_QID_EMPTY_CHECK_LOOPS\t\t(32 * 64 * 1024 * (800 / 30))\n-#ifdef FPGA\n-#define DLB2_HZ\t\t\t\t\t2000000\n-#else\n-#define DLB2_HZ\t\t\t\t\t800000000\n-#endif\n-\n #define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710\n #define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711\n \n-/* Interrupt related macros */\n-#define DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n-#define DLB2_PF_NUM_CQ_INTERRUPT_VECTORS 64\n-#define DLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS \\\n-\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n-\t DLB2_PF_NUM_CQ_INTERRUPT_VECTORS)\n-#define DLB2_PF_NUM_COMPRESSED_MODE_VECTORS \\\n-\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + 1)\n-#define DLB2_PF_NUM_PACKED_MODE_VECTORS \\\n-\tDLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS\n-#define DLB2_PF_COMPRESSED_MODE_CQ_VECTOR_ID \\\n-\tDLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS\n-\n-/* DLB non-CQ interrupts (alarm, mailbox, WDT) */\n-#define DLB2_INT_NON_CQ 0\n-\n #define DLB2_ALARM_HW_SOURCE_SYS 0\n #define DLB2_ALARM_HW_SOURCE_DLB 1\n \n@@ -65,18 +35,6 @@\n #define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ\t1\n #define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2\n \n-#define DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n-#define DLB2_VF_NUM_CQ_INTERRUPT_VECTORS 31\n-#define DLB2_VF_BASE_CQ_VECTOR_ID\t 0\n-#define DLB2_VF_LAST_CQ_VECTOR_ID\t 30\n-#define DLB2_VF_MBOX_VECTOR_ID\t\t 31\n-#define DLB2_VF_TOTAL_NUM_INTERRUPT_VECTORS \\\n-\t(DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n-\t DLB2_VF_NUM_CQ_INTERRUPT_VECTORS)\n-\n-#define DLB2_VDEV_MAX_NUM_INTERRUPT_VECTORS (DLB2_MAX_NUM_LDB_PORTS + \\\n-\t\t\t\t\t DLB2_MAX_NUM_DIR_PORTS + 1)\n-\n /*\n * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by\n * the PF driver.\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_mbox.h b/drivers/event/dlb2/pf/base/dlb2_mbox.h\ndeleted file mode 100644\nindex ce462c089..000000000\n--- a/drivers/event/dlb2/pf/base/dlb2_mbox.h\n+++ /dev/null\n@@ -1,596 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2020 Intel Corporation\n- */\n-\n-#ifndef __DLB2_BASE_DLB2_MBOX_H\n-#define __DLB2_BASE_DLB2_MBOX_H\n-\n-#include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs.h\"\n-\n-#define DLB2_MBOX_INTERFACE_VERSION 1\n-\n-/*\n- * The PF uses its PF->VF mailbox to send responses to VF requests, as well as\n- * to send requests of its own (e.g. notifying a VF of an impending FLR).\n- * To avoid communication race conditions, e.g. the PF sends a response and then\n- * sends a request before the VF reads the response, the PF->VF mailbox is\n- * divided into two sections:\n- * - Bytes 0-47: PF responses\n- * - Bytes 48-63: PF requests\n- *\n- * Partitioning the PF->VF mailbox allows responses and requests to occupy the\n- * mailbox simultaneously.\n- */\n-#define DLB2_PF2VF_RESP_BYTES\t 48\n-#define DLB2_PF2VF_RESP_BASE\t 0\n-#define DLB2_PF2VF_RESP_BASE_WORD (DLB2_PF2VF_RESP_BASE / 4)\n-\n-#define DLB2_PF2VF_REQ_BYTES\t 16\n-#define DLB2_PF2VF_REQ_BASE\t (DLB2_PF2VF_RESP_BASE + DLB2_PF2VF_RESP_BYTES)\n-#define DLB2_PF2VF_REQ_BASE_WORD (DLB2_PF2VF_REQ_BASE / 4)\n-\n-/*\n- * Similarly, the VF->PF mailbox is divided into two sections:\n- * - Bytes 0-239: VF requests\n- * -- (Bytes 0-3 are unused due to a hardware errata)\n- * - Bytes 240-255: VF responses\n- */\n-#define DLB2_VF2PF_REQ_BYTES\t 236\n-#define DLB2_VF2PF_REQ_BASE\t 4\n-#define DLB2_VF2PF_REQ_BASE_WORD (DLB2_VF2PF_REQ_BASE / 4)\n-\n-#define DLB2_VF2PF_RESP_BYTES\t 16\n-#define DLB2_VF2PF_RESP_BASE\t (DLB2_VF2PF_REQ_BASE + DLB2_VF2PF_REQ_BYTES)\n-#define DLB2_VF2PF_RESP_BASE_WORD (DLB2_VF2PF_RESP_BASE / 4)\n-\n-/* VF-initiated commands */\n-enum dlb2_mbox_cmd_type {\n-\tDLB2_MBOX_CMD_REGISTER,\n-\tDLB2_MBOX_CMD_UNREGISTER,\n-\tDLB2_MBOX_CMD_GET_NUM_RESOURCES,\n-\tDLB2_MBOX_CMD_CREATE_SCHED_DOMAIN,\n-\tDLB2_MBOX_CMD_RESET_SCHED_DOMAIN,\n-\tDLB2_MBOX_CMD_CREATE_LDB_QUEUE,\n-\tDLB2_MBOX_CMD_CREATE_DIR_QUEUE,\n-\tDLB2_MBOX_CMD_CREATE_LDB_PORT,\n-\tDLB2_MBOX_CMD_CREATE_DIR_PORT,\n-\tDLB2_MBOX_CMD_ENABLE_LDB_PORT,\n-\tDLB2_MBOX_CMD_DISABLE_LDB_PORT,\n-\tDLB2_MBOX_CMD_ENABLE_DIR_PORT,\n-\tDLB2_MBOX_CMD_DISABLE_DIR_PORT,\n-\tDLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN,\n-\tDLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN,\n-\tDLB2_MBOX_CMD_MAP_QID,\n-\tDLB2_MBOX_CMD_UNMAP_QID,\n-\tDLB2_MBOX_CMD_START_DOMAIN,\n-\tDLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR,\n-\tDLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR,\n-\tDLB2_MBOX_CMD_ARM_CQ_INTR,\n-\tDLB2_MBOX_CMD_GET_NUM_USED_RESOURCES,\n-\tDLB2_MBOX_CMD_GET_SN_ALLOCATION,\n-\tDLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH,\n-\tDLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH,\n-\tDLB2_MBOX_CMD_PENDING_PORT_UNMAPS,\n-\tDLB2_MBOX_CMD_GET_COS_BW,\n-\tDLB2_MBOX_CMD_GET_SN_OCCUPANCY,\n-\tDLB2_MBOX_CMD_QUERY_CQ_POLL_MODE,\n-\n-\t/* NUM_QE_CMD_TYPES must be last */\n-\tNUM_DLB2_MBOX_CMD_TYPES,\n-};\n-\n-static const char dlb2_mbox_cmd_type_strings[][128] = {\n-\t\"DLB2_MBOX_CMD_REGISTER\",\n-\t\"DLB2_MBOX_CMD_UNREGISTER\",\n-\t\"DLB2_MBOX_CMD_GET_NUM_RESOURCES\",\n-\t\"DLB2_MBOX_CMD_CREATE_SCHED_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_RESET_SCHED_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_CREATE_LDB_QUEUE\",\n-\t\"DLB2_MBOX_CMD_CREATE_DIR_QUEUE\",\n-\t\"DLB2_MBOX_CMD_CREATE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_CREATE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_DISABLE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_DISABLE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_MAP_QID\",\n-\t\"DLB2_MBOX_CMD_UNMAP_QID\",\n-\t\"DLB2_MBOX_CMD_START_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR\",\n-\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR\",\n-\t\"DLB2_MBOX_CMD_ARM_CQ_INTR\",\n-\t\"DLB2_MBOX_CMD_GET_NUM_USED_RESOURCES\",\n-\t\"DLB2_MBOX_CMD_GET_SN_ALLOCATION\",\n-\t\"DLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH\",\n-\t\"DLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH\",\n-\t\"DLB2_MBOX_CMD_PENDING_PORT_UNMAPS\",\n-\t\"DLB2_MBOX_CMD_GET_COS_BW\",\n-\t\"DLB2_MBOX_CMD_GET_SN_OCCUPANCY\",\n-\t\"DLB2_MBOX_CMD_QUERY_CQ_POLL_MODE\",\n-};\n-\n-/* PF-initiated commands */\n-enum dlb2_mbox_vf_cmd_type {\n-\tDLB2_MBOX_VF_CMD_DOMAIN_ALERT,\n-\tDLB2_MBOX_VF_CMD_NOTIFICATION,\n-\tDLB2_MBOX_VF_CMD_IN_USE,\n-\n-\t/* NUM_DLB2_MBOX_VF_CMD_TYPES must be last */\n-\tNUM_DLB2_MBOX_VF_CMD_TYPES,\n-};\n-\n-static const char dlb2_mbox_vf_cmd_type_strings[][128] = {\n-\t\"DLB2_MBOX_VF_CMD_DOMAIN_ALERT\",\n-\t\"DLB2_MBOX_VF_CMD_NOTIFICATION\",\n-\t\"DLB2_MBOX_VF_CMD_IN_USE\",\n-};\n-\n-#define DLB2_MBOX_CMD_TYPE(hdr) \\\n-\t(((struct dlb2_mbox_req_hdr *)hdr)->type)\n-#define DLB2_MBOX_CMD_STRING(hdr) \\\n-\tdlb2_mbox_cmd_type_strings[DLB2_MBOX_CMD_TYPE(hdr)]\n-\n-enum dlb2_mbox_status_type {\n-\tDLB2_MBOX_ST_SUCCESS,\n-\tDLB2_MBOX_ST_INVALID_CMD_TYPE,\n-\tDLB2_MBOX_ST_VERSION_MISMATCH,\n-\tDLB2_MBOX_ST_INVALID_OWNER_VF,\n-};\n-\n-static const char dlb2_mbox_status_type_strings[][128] = {\n-\t\"DLB2_MBOX_ST_SUCCESS\",\n-\t\"DLB2_MBOX_ST_INVALID_CMD_TYPE\",\n-\t\"DLB2_MBOX_ST_VERSION_MISMATCH\",\n-\t\"DLB2_MBOX_ST_INVALID_OWNER_VF\",\n-};\n-\n-#define DLB2_MBOX_ST_TYPE(hdr) \\\n-\t(((struct dlb2_mbox_resp_hdr *)hdr)->status)\n-#define DLB2_MBOX_ST_STRING(hdr) \\\n-\tdlb2_mbox_status_type_strings[DLB2_MBOX_ST_TYPE(hdr)]\n-\n-/* This structure is always the first field in a request structure */\n-struct dlb2_mbox_req_hdr {\n-\tu32 type;\n-};\n-\n-/* This structure is always the first field in a response structure */\n-struct dlb2_mbox_resp_hdr {\n-\tu32 status;\n-};\n-\n-struct dlb2_mbox_register_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 min_interface_version;\n-\tu16 max_interface_version;\n-};\n-\n-struct dlb2_mbox_register_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 interface_version;\n-\tu8 pf_id;\n-\tu8 vf_id;\n-\tu8 is_auxiliary_vf;\n-\tu8 primary_vf_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_unregister_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_unregister_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_num_resources_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_num_resources_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu16 num_sched_domains;\n-\tu16 num_ldb_queues;\n-\tu16 num_ldb_ports;\n-\tu16 num_cos_ldb_ports[4];\n-\tu16 num_dir_ports;\n-\tu32 num_atomic_inflights;\n-\tu32 num_hist_list_entries;\n-\tu32 max_contiguous_hist_list_entries;\n-\tu16 num_ldb_credits;\n-\tu16 num_dir_credits;\n-};\n-\n-struct dlb2_mbox_create_sched_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 num_ldb_queues;\n-\tu32 num_ldb_ports;\n-\tu32 num_cos_ldb_ports[4];\n-\tu32 num_dir_ports;\n-\tu32 num_atomic_inflights;\n-\tu32 num_hist_list_entries;\n-\tu32 num_ldb_credits;\n-\tu32 num_dir_credits;\n-\tu8 cos_strict;\n-\tu8 padding0[3];\n-\tu32 padding1;\n-};\n-\n-struct dlb2_mbox_create_sched_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_reset_sched_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_reset_sched_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-};\n-\n-struct dlb2_mbox_create_ldb_queue_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 num_sequence_numbers;\n-\tu32 num_qid_inflights;\n-\tu32 num_atomic_inflights;\n-\tu32 lock_id_comp_level;\n-\tu32 depth_threshold;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_create_ldb_queue_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_dir_queue_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 depth_threshold;\n-};\n-\n-struct dlb2_mbox_create_dir_queue_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu16 cq_depth;\n-\tu16 cq_history_list_size;\n-\tu8 cos_id;\n-\tu8 cos_strict;\n-\tu16 padding1;\n-\tu64 cq_base_address;\n-};\n-\n-struct dlb2_mbox_create_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu64 cq_base_address;\n-\tu16 cq_depth;\n-\tu16 padding0;\n-\ts32 queue_id;\n-};\n-\n-struct dlb2_mbox_create_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_ldb_port_owned_by_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_ldb_port_owned_by_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\ts32 owned;\n-};\n-\n-struct dlb2_mbox_dir_port_owned_by_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_dir_port_owned_by_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\ts32 owned;\n-};\n-\n-struct dlb2_mbox_map_qid_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 qid;\n-\tu32 priority;\n-\tu32 padding0;\n-};\n-\n-struct dlb2_mbox_map_qid_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_unmap_qid_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 qid;\n-};\n-\n-struct dlb2_mbox_unmap_qid_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_start_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-};\n-\n-struct dlb2_mbox_start_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 port_id;\n-\tu16 thresh;\n-\tu16 vector;\n-\tu16 owner_vf;\n-\tu16 reserved[2];\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 port_id;\n-\tu16 thresh;\n-\tu16 vector;\n-\tu16 owner_vf;\n-\tu16 reserved[2];\n-};\n-\n-struct dlb2_mbox_enable_dir_port_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_arm_cq_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 is_ldb;\n-};\n-\n-struct dlb2_mbox_arm_cq_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding0;\n-};\n-\n-/*\n- * The alert_id and aux_alert_data follows the format of the alerts defined in\n- * dlb2_types.h. The alert id contains an enum dlb2_domain_alert_id value, and\n- * the aux_alert_data value varies depending on the alert.\n- */\n-struct dlb2_mbox_vf_alert_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 alert_id;\n-\tu32 aux_alert_data;\n-};\n-\n-enum dlb2_mbox_vf_notification_type {\n-\tDLB2_MBOX_VF_NOTIFICATION_PRE_RESET,\n-\tDLB2_MBOX_VF_NOTIFICATION_POST_RESET,\n-\n-\t/* NUM_DLB2_MBOX_VF_NOTIFICATION_TYPES must be last */\n-\tNUM_DLB2_MBOX_VF_NOTIFICATION_TYPES,\n-};\n-\n-struct dlb2_mbox_vf_notification_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 notification;\n-};\n-\n-struct dlb2_mbox_vf_in_use_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_vf_in_use_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 in_use;\n-};\n-\n-struct dlb2_mbox_get_sn_allocation_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 group_id;\n-};\n-\n-struct dlb2_mbox_get_sn_allocation_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_ldb_queue_depth_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 queue_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_ldb_queue_depth_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 depth;\n-};\n-\n-struct dlb2_mbox_get_dir_queue_depth_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 queue_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_dir_queue_depth_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 depth;\n-};\n-\n-struct dlb2_mbox_pending_port_unmaps_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_pending_port_unmaps_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_cos_bw_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 cos_id;\n-};\n-\n-struct dlb2_mbox_get_cos_bw_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_sn_occupancy_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 group_id;\n-};\n-\n-struct dlb2_mbox_get_sn_occupancy_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_query_cq_poll_mode_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_query_cq_poll_mode_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 mode;\n-};\n-\n-#endif /* __DLB2_BASE_DLB2_MBOX_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex ae5ef2fc3..b57157fdc 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -5,7 +5,6 @@\n #include \"dlb2_user.h\"\n \n #include \"dlb2_hw_types.h\"\n-#include \"dlb2_mbox.h\"\n #include \"dlb2_osdep.h\"\n #include \"dlb2_osdep_bitmap.h\"\n #include \"dlb2_osdep_types.h\"\n", "prefixes": [ "v5", "01/26" ] }