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GET /api/patches/92524/?format=api
{ "id": 92524, "url": "https://patches.dpdk.org/api/patches/92524/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-13-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210430135336.2749-13-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210430135336.2749-13-pbhagavatula@marvell.com", "date": "2021-04-30T13:53:15", "name": "[v3,12/33] event/cnxk: add devargs to configure getwork mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2656d894035266acc45075b9fb1b8dffb376b718", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-13-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16775, "url": "https://patches.dpdk.org/api/series/16775/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16775", "date": "2021-04-30T13:53:03", "name": "Marvell CNXK Event device Driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16775/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92524/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92524/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9C9B4A0546;\n\tFri, 30 Apr 2021 15:55:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D74C1412A1;\n\tFri, 30 Apr 2021 15:54:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 49D7D41138\n for <dev@dpdk.org>; Fri, 30 Apr 2021 15:54:17 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13UDoqZD014506 for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:16 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3883jtbfua-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:16 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 30 Apr 2021 06:54:15 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 30 Apr 2021 06:54:14 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 5C22D3F7040;\n Fri, 30 Apr 2021 06:54:13 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=6cga5IB+VGljHnEjQYxqyYhwbE7xxk1FyBOlN21W6aQ=;\n b=X1MbP3uU4tV87ZH0xWHfK0ceLuyzec6lyJZVACqhinMDQmrWAaI7k9sBifB+cYQSpgvr\n fQX0WcyWgCRWk1XsbqlSKz2w4uU+kylM36M4OA82Y5e1SFxnIdhkQ/u2lo7vM7Y563E5\n +VLXklx53o1GHYBGfFNGHasTJIf+86Fx6BhofhXP7kIlRXx49tKvkWY8GqYQQCKxjzLg\n uoV2MF8F4sI6aWlzJx17rrgH11u6sDEcRlHCXrbYKNstfBrh2seotvyuAY7gf1SylArS\n pHK1vyhH+sFVL0lFVa2NWua9XJK+CcDSrGyhI+mhexdWTnQr8fhzAkuj62csqXLDW+U4 tg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 30 Apr 2021 19:23:15 +0530", "Message-ID": "<20210430135336.2749-13-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210430135336.2749-1-pbhagavatula@marvell.com>", "References": "<20210426174441.2302-1-pbhagavatula@marvell.com>\n <20210430135336.2749-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "_GAtdOdmWu-2L9UeGnXaKuvY1gx2l0lO", "X-Proofpoint-ORIG-GUID": "_GAtdOdmWu-2L9UeGnXaKuvY1gx2l0lO", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-30_08:2021-04-30,\n 2021-04-30 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 12/33] event/cnxk: add devargs to configure\n getwork mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs to configure the platform specific getwork mode.\n\nCN9K getwork mode by default is set to use dual workslot mode.\nAdd option to force single workslot mode.\nExample:\n\t--dev \"0002:0e:00.0,single_ws=1\"\n\nCN10K supports multiple getwork prefetch modes, by default the\nprefetch mode is set to none.\nAdd option to select getwork prefetch mode\nExample:\n\t--dev \"0002:1e:00.0,gw_mode=1\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 18 ++++++++++++++++++\n drivers/event/cnxk/cn10k_eventdev.c | 3 ++-\n drivers/event/cnxk/cn9k_eventdev.c | 3 ++-\n drivers/event/cnxk/cnxk_eventdev.c | 6 ++++++\n drivers/event/cnxk/cnxk_eventdev.h | 6 ++++--\n 5 files changed, 32 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 0583e5fdd..f48452982 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -55,6 +55,24 @@ Runtime Config Options\n \n -a 0002:0e:00.0,xae_cnt=16384\n \n+- ``CN9K Getwork mode``\n+\n+ CN9K ``single_ws`` devargs parameter is introduced to select single workslot\n+ mode in SSO and disable the default dual workslot mode.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,single_ws=1\n+\n+- ``CN10K Getwork mode``\n+\n+ CN10K supports multiple getwork prefetch modes, by default the prefetch\n+ mode is set to none.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,gw_mode=1\n+\n - ``Event Group QoS support``\n \n SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex b149b7831..fe1bbd2d4 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -327,4 +327,5 @@ RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n-\t\t\t CNXK_SSO_GGRP_QOS \"=<string>\");\n+\t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n+\t\t\t CN10K_SSO_GW_MODE \"=<int>\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex b26fc0eae..29d1de09e 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -395,4 +395,5 @@ RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\"\n-\t\t\t CNXK_SSO_GGRP_QOS \"=<string>\");\n+\t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n+\t\t\t CN9K_SSO_SINGLE_WS \"=1\");\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex e68079997..2a387ff95 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -406,6 +406,7 @@ static void\n cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)\n {\n \tstruct rte_kvargs *kvlist;\n+\tuint8_t single_ws = 0;\n \n \tif (devargs == NULL)\n \t\treturn;\n@@ -417,6 +418,11 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)\n \t\t\t &dev->xae_cnt);\n \trte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,\n \t\t\t dev);\n+\trte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value,\n+\t\t\t &single_ws);\n+\trte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value,\n+\t\t\t &dev->gw_mode);\n+\tdev->dual_ws = !single_ws;\n \trte_kvargs_free(kvlist);\n }\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 97a944d88..437cdf3db 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -14,8 +14,10 @@\n \n #include \"roc_api.h\"\n \n-#define CNXK_SSO_XAE_CNT \"xae_cnt\"\n-#define CNXK_SSO_GGRP_QOS \"qos\"\n+#define CNXK_SSO_XAE_CNT \"xae_cnt\"\n+#define CNXK_SSO_GGRP_QOS \"qos\"\n+#define CN9K_SSO_SINGLE_WS \"single_ws\"\n+#define CN10K_SSO_GW_MODE \"gw_mode\"\n \n #define NSEC2USEC(__ns)\t\t((__ns) / 1E3)\n #define USEC2NSEC(__us)\t\t((__us)*1E3)\n", "prefixes": [ "v3", "12/33" ] }