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GET /api/patches/92519/?format=api
{ "id": 92519, "url": "https://patches.dpdk.org/api/patches/92519/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-8-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210430135336.2749-8-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210430135336.2749-8-pbhagavatula@marvell.com", "date": "2021-04-30T13:53:10", "name": "[v3,07/33] event/cnxk: allocate event inflight buffers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "80c45483b961577b66bd46c2f29e44caa2e361e2", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210430135336.2749-8-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16775, "url": "https://patches.dpdk.org/api/series/16775/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16775", "date": "2021-04-30T13:53:03", "name": "Marvell CNXK Event device Driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16775/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92519/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92519/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 86251A0546;\n\tFri, 30 Apr 2021 15:54:31 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 355D94116A;\n\tFri, 30 Apr 2021 15:54:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B80C040693\n for <dev@dpdk.org>; Fri, 30 Apr 2021 15:54:03 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13UDoOEb013859 for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:03 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3883jtbftc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 30 Apr 2021 06:54:02 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 30 Apr 2021 06:54:01 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 30 Apr 2021 06:54:01 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id CFD813F703F;\n Fri, 30 Apr 2021 06:53:59 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gFR/OhIf+lq1jsnmWPuHCWP+OWeGXEqTCQv8q2kRU5k=;\n b=k1HyXx6CwSvOyQkRWvfCGKLBWt+iw0m2BTvdyQ8wtn8Gnpr+jfK/XEVTuMhNSF0Drm9+\n lm6be1Vt579ICy9ome1Rfbi0bdKGnzHOPJMg6OkPoYtKNnqytoLh24Chq4fKUsQCnrab\n xPVJZyCRn5YwddaKN0ibMmpDAyaZmpl1N8u9CJgjTWGSC9O0LOg2xkaOoEZlIwu6p6do\n Z8H865rvXegwyTLipWbV3Gt1lQ/eMjqRLbl6YqX1qpyb3aI5Ddgkndev3p7lT+tSOGdm\n gQ2guqp1er71vtIBqgjCTk6w5yZqBfapII4kBqeZn97gu9/3ya949tAZukpIVG6dXEsb tg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 30 Apr 2021 19:23:10 +0530", "Message-ID": "<20210430135336.2749-8-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210430135336.2749-1-pbhagavatula@marvell.com>", "References": "<20210426174441.2302-1-pbhagavatula@marvell.com>\n <20210430135336.2749-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "PFonK8ctQhmsZJ_egxGOU2uEnrXb57sf", "X-Proofpoint-ORIG-GUID": "PFonK8ctQhmsZJ_egxGOU2uEnrXb57sf", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-30_08:2021-04-30,\n 2021-04-30 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 07/33] event/cnxk: allocate event inflight\n buffers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAllocate buffers in DRAM that hold inflight events.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 7 ++\n drivers/event/cnxk/cn9k_eventdev.c | 7 ++\n drivers/event/cnxk/cnxk_eventdev.c | 105 ++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 14 +++-\n 4 files changed, 132 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex fe562d65b..20d141f16 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -55,6 +55,13 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \t\treturn -ENODEV;\n \t}\n \n+\trc = cnxk_sso_xaq_allocate(dev);\n+\tif (rc < 0)\n+\t\tgoto cnxk_rsrc_fini;\n+\n+\treturn 0;\n+cnxk_rsrc_fini:\n+\troc_sso_rsrc_fini(&dev->sso);\n \treturn rc;\n }\n \ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex d49acad83..5f93fc2a7 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -63,6 +63,13 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \t\treturn -ENODEV;\n \t}\n \n+\trc = cnxk_sso_xaq_allocate(dev);\n+\tif (rc < 0)\n+\t\tgoto cnxk_rsrc_fini;\n+\n+\treturn 0;\n+cnxk_rsrc_fini:\n+\troc_sso_rsrc_fini(&dev->sso);\n \treturn rc;\n }\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex e22479a19..34a8bce05 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -28,12 +28,107 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n \t\t\t\t RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;\n }\n \n+int\n+cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n+{\n+\tchar pool_name[RTE_MEMZONE_NAMESIZE];\n+\tuint32_t xaq_cnt, npa_aura_id;\n+\tconst struct rte_memzone *mz;\n+\tstruct npa_aura_s *aura;\n+\tstatic int reconfig_cnt;\n+\tint rc;\n+\n+\tif (dev->xaq_pool) {\n+\t\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n+\t\tif (rc < 0) {\n+\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\trte_mempool_free(dev->xaq_pool);\n+\t\tdev->xaq_pool = NULL;\n+\t}\n+\n+\t/*\n+\t * Allocate memory for Add work backpressure.\n+\t */\n+\tmz = rte_memzone_lookup(CNXK_SSO_FC_NAME);\n+\tif (mz == NULL)\n+\t\tmz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME,\n+\t\t\t\t\t\t sizeof(struct npa_aura_s) +\n+\t\t\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t\t\t 0, 0, RTE_CACHE_LINE_SIZE);\n+\tif (mz == NULL) {\n+\t\tplt_err(\"Failed to allocate mem for fcmem\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tdev->fc_iova = mz->iova;\n+\tdev->fc_mem = mz->addr;\n+\n+\taura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem +\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tmemset(aura, 0, sizeof(struct npa_aura_s));\n+\n+\taura->fc_ena = 1;\n+\taura->fc_addr = dev->fc_iova;\n+\taura->fc_hyst_bits = 0; /* Store count on all updates */\n+\n+\t/* Taken from HRM 14.3.3(4) */\n+\txaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;\n+\txaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +\n+\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n+\n+\tplt_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n+\t/* Setup XAQ based on number of nb queues. */\n+\tsnprintf(pool_name, 30, \"cnxk_xaq_buf_pool_%d\", reconfig_cnt);\n+\tdev->xaq_pool = (void *)rte_mempool_create_empty(\n+\t\tpool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0,\n+\t\trte_socket_id(), 0);\n+\n+\tif (dev->xaq_pool == NULL) {\n+\t\tplt_err(\"Unable to create empty mempool.\");\n+\t\trte_memzone_free(mz);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trc = rte_mempool_set_ops_byname(dev->xaq_pool,\n+\t\t\t\t\trte_mbuf_platform_mempool_ops(), aura);\n+\tif (rc != 0) {\n+\t\tplt_err(\"Unable to set xaqpool ops.\");\n+\t\tgoto alloc_fail;\n+\t}\n+\n+\trc = rte_mempool_populate_default(dev->xaq_pool);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to set populate xaqpool.\");\n+\t\tgoto alloc_fail;\n+\t}\n+\treconfig_cnt++;\n+\t/* When SW does addwork (enqueue) check if there is space in XAQ by\n+\t * comparing fc_addr above against the xaq_lmt calculated below.\n+\t * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO\n+\t * to request XAQ to cache them even before enqueue is called.\n+\t */\n+\tdev->xaq_lmt =\n+\t\txaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues);\n+\tdev->nb_xaq_cfg = xaq_cnt;\n+\n+\tnpa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id);\n+\treturn roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id,\n+\t\t\t\t dev->nb_event_queues);\n+alloc_fail:\n+\trte_mempool_free(dev->xaq_pool);\n+\trte_memzone_free(mz);\n+\treturn rc;\n+}\n+\n int\n cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n {\n \tstruct rte_event_dev_config *conf = &event_dev->data->dev_conf;\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint32_t deq_tmo_ns;\n+\tint rc;\n \n \tdeq_tmo_ns = conf->dequeue_timeout_ns;\n \n@@ -67,6 +162,16 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (dev->xaq_pool) {\n+\t\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n+\t\tif (rc < 0) {\n+\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\trte_mempool_free(dev->xaq_pool);\n+\t\tdev->xaq_pool = NULL;\n+\t}\n+\n \tdev->nb_event_queues = conf->nb_event_queues;\n \tdev->nb_event_ports = conf->nb_event_ports;\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 426219c85..4abe4548d 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -5,6 +5,7 @@\n #ifndef __CNXK_EVENTDEV_H__\n #define __CNXK_EVENTDEV_H__\n \n+#include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n #include <eventdev_pmd_pci.h>\n@@ -13,7 +14,10 @@\n \n #define USEC2NSEC(__us) ((__us)*1E3)\n \n-#define CNXK_SSO_MZ_NAME \"cnxk_evdev_mz\"\n+#define CNXK_SSO_FC_NAME \"cnxk_evdev_xaq_fc\"\n+#define CNXK_SSO_MZ_NAME \"cnxk_evdev_mz\"\n+#define CNXK_SSO_XAQ_CACHE_CNT (0x7)\n+#define CNXK_SSO_XAQ_SLACK (8)\n \n struct cnxk_sso_evdev {\n \tstruct roc_sso sso;\n@@ -26,6 +30,11 @@ struct cnxk_sso_evdev {\n \tuint32_t min_dequeue_timeout_ns;\n \tuint32_t max_dequeue_timeout_ns;\n \tint32_t max_num_events;\n+\tuint64_t *fc_mem;\n+\tuint64_t xaq_lmt;\n+\tuint64_t nb_xaq_cfg;\n+\trte_iova_t fc_iova;\n+\tstruct rte_mempool *xaq_pool;\n \t/* CN9K */\n \tuint8_t dual_ws;\n } __rte_cache_aligned;\n@@ -36,6 +45,9 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)\n \treturn event_dev->data->dev_private;\n }\n \n+/* Configuration functions */\n+int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);\n+\n /* Common ops API. */\n int cnxk_sso_init(struct rte_eventdev *event_dev);\n int cnxk_sso_fini(struct rte_eventdev *event_dev);\n", "prefixes": [ "v3", "07/33" ] }