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GET /api/patches/92500/?format=api
{ "id": 92500, "url": "https://patches.dpdk.org/api/patches/92500/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210430125725.28796-12-mk@semihalf.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210430125725.28796-12-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210430125725.28796-12-mk@semihalf.com", "date": "2021-04-30T12:57:14", "name": "[11/22] net/ena/base: adjust changes to lastest ena-com", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "38caa6d2834214816f7422c1c0f2820bdef3a4a4", "submitter": { "id": 786, "url": "https://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210430125725.28796-12-mk@semihalf.com/mbox/", "series": [ { "id": 16774, "url": "https://patches.dpdk.org/api/series/16774/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16774", "date": "2021-04-30T12:57:03", "name": "net/ena: update ENA PMD to v2.3.0", "version": 1, "mbox": "https://patches.dpdk.org/series/16774/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92500/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/92500/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 924C8A0546;\n\tFri, 30 Apr 2021 14:58:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 996294123D;\n\tFri, 30 Apr 2021 14:57:58 +0200 (CEST)", "from mail-wr1-f47.google.com (mail-wr1-f47.google.com\n [209.85.221.47]) by mails.dpdk.org (Postfix) with ESMTP id 17CEF411F0\n for <dev@dpdk.org>; Fri, 30 Apr 2021 14:57:51 +0200 (CEST)", "by mail-wr1-f47.google.com with SMTP id d11so12633708wrw.8\n for <dev@dpdk.org>; Fri, 30 Apr 2021 05:57:51 -0700 (PDT)", "from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl.\n [89.79.189.199])\n by smtp.gmail.com with ESMTPSA id l13sm13476245wmj.3.2021.04.30.05.57.48\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 30 Apr 2021 05:57:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20150623.gappssmtp.com; s=20150623;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=N1Zhgr2+1C+kbsDg0SeNcocJIXeHybGGWxf8UVMnFic=;\n b=kq+1bVR/9y55aEyDwnbJmfa5cKalTkYeOlI846tNtVUvRnFZcHJKilPypq45JAuYxS\n 90bmzanRjYlpBCaaCqJHTbDHzrEGQwyGXWpdku80/+ZphrexHgNyoI9rzHtub2rD7Pqx\n hI2ROu3Eu9B6pb37+z7ureFRf/ZR4bKAA/p2EZRwEA13rdXM2/1WgltO8N7d3+5/BBjU\n iiLCnvP2o4wYewpI9l0KRMJYODripWVqWcBJGI5CpQGmfL/9L+dLYHAKv92xWs39lOhS\n wP5cnZj6J0XVFQjTDncvzkZ0EfsGe59kaND4QbyfzrnSZAtzx/s5ONVarTU/Z9wcm5Kz\n uw4A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=N1Zhgr2+1C+kbsDg0SeNcocJIXeHybGGWxf8UVMnFic=;\n b=rwob7HkXfqujaZNBkw8z6QYVSB5A92Uc+R9lP0bKbusFslUgoUPdFM7kNEA3r2Lws8\n Cyh6oQ10IeB5yfIjEHL3PNTRMF30o+l//oAImWNoOQXM7qT9ilGuf/JHzUK1abVDb1JG\n Oosd0l0Loh0/B208xLtgukg4IYp+7yG6rizYaMC0qgnV4qKxfoKNoea6sKv6cq2652wg\n 61yxkhypd8UaU5q3hpMe+rGV+2+Q4rLG3x/RF19sCgHawzko83ppWJOutnt6EhGII1zb\n lSkfwS48FdX6FllklUAUHpvI/2heuCss0qmYot1K1/HNn1oJYAM/uysdBV8QRWZ4ORLY\n dhYQ==", "X-Gm-Message-State": "AOAM532j6OwJjrXrzIX20GmKcQCt1+3tpT/qVYSfXyfS40TT9YjL47xW\n oi1F+Ovqplx6DE/Q4VlBOO5FTh9Cjay/zwqE", "X-Google-Smtp-Source": "\n ABdhPJw1deGRPJCkXkjXjGlgXqRURwK8952M6BxaXGFqSamFEdBbCOYUzoPotphRVVrRKS2UrIDpLw==", "X-Received": "by 2002:adf:fc07:: with SMTP id i7mr6513938wrr.43.1619787470432;\n Fri, 30 Apr 2021 05:57:50 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "ndagan@amazom.com, gtzalik@amazon.com, igorch@amazon.com, mw@semihalf.com,\n Amit Bernstein <amitbern@amazon.com>, Shay Agroskin <shayagr@amazon.com>,\n Michal Krawczyk <mk@semihalf.com>", "Date": "Fri, 30 Apr 2021 14:57:14 +0200", "Message-Id": "<20210430125725.28796-12-mk@semihalf.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210430125725.28796-1-mk@semihalf.com>", "References": "<20210430125725.28796-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 11/22] net/ena/base: adjust changes to lastest\n ena-com", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Amit Bernstein <amitbern@amazon.com>\n\n1. As memzone uses unique names, changed alloc coherent macro to use\n 64 bit size atomic variable to increase the memzone name space\n2. \"handle\" param name change to be consistent with other macros\n3. Variable definition displacement\n4. Backslash alignment to column 80\n\nSigned-off-by: Amit Bernstein <amitbern@amazon.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Shay Agroskin <shayagr@amazon.com>\nReviewed-by: Michal Krawczyk <mk@semihalf.com>\n---\n drivers/net/ena/base/ena_plat_dpdk.h | 242 +++++++++++++--------------\n drivers/net/ena/ena_ethdev.c | 2 +-\n 2 files changed, 114 insertions(+), 130 deletions(-)", "diff": "diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h\nindex 1eec4f0c72..2e40ea1bb4 100644\n--- a/drivers/net/ena/base/ena_plat_dpdk.h\n+++ b/drivers/net/ena/base/ena_plat_dpdk.h\n@@ -34,10 +34,12 @@ typedef uint8_t u8;\n \n typedef struct rte_eth_dev ena_netdev;\n typedef uint64_t dma_addr_t;\n+\n #ifndef ETIME\n #define ETIME ETIMEDOUT\n #endif\n \n+#define ENA_PRIu64 PRIu64\n #define ena_atomic32_t rte_atomic32_t\n #define ena_mem_handle_t const struct rte_memzone *\n \n@@ -73,7 +75,7 @@ typedef uint64_t dma_addr_t;\n #define __iomem\n \n #define US_PER_S 1000000\n-#define ENA_GET_SYSTEM_USECS()\t\t\t\t\t\t\\\n+#define ENA_GET_SYSTEM_USECS()\t\t\t\t\t\t \\\n \t(rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())\n \n extern int ena_logtype_com;\n@@ -92,15 +94,15 @@ extern int ena_logtype_com;\n #define BIT(nr) (1UL << (nr))\n #define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n #define GENMASK(h, l)\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n-#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \\\n+#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \t\t \\\n \t\t\t (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n \n #ifdef RTE_LIBRTE_ENA_COM_DEBUG\n-#define ena_trc_log(dev, level, fmt, arg...)\t\t\t\t\\\n+#define ena_trc_log(dev, level, fmt, arg...)\t\t\t\t \\\n \t(\n-\t\tENA_TOUCH(dev),\t\t\t\t\t\t\\\n-\t\trte_log(RTE_LOG_ ## level, ena_logtype_com,\t\t\\\n-\t\t\t\"[ENA_COM: %s]\" fmt, __func__, ##arg))\t\t\\\n+\t\tENA_TOUCH(dev),\t\t\t\t\t\t \\\n+\t\trte_log(RTE_LOG_ ## level, ena_logtype_com,\t\t \\\n+\t\t\t\"[ENA_COM: %s]\" fmt, __func__, ##arg))\t\t \\\n \t)\n \n #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg)\n@@ -114,51 +116,51 @@ extern int ena_logtype_com;\n #define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev)\n #endif /* RTE_LIBRTE_ENA_COM_DEBUG */\n \n-#define ENA_WARN(cond, dev, format, arg...)\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tif (unlikely(cond)) {\t\t\t\t\t\\\n-\t\t\tena_trc_err(dev,\t\t\t\t\\\n-\t\t\t\t\"Warn failed on %s:%s:%d:\" format,\t\\\n-\t\t\t\t__FILE__, __func__, __LINE__, ##arg);\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n+#define ENA_WARN(cond, dev, format, arg...)\t\t\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tif (unlikely(cond)) {\t\t\t\t\t \\\n+\t\t\tena_trc_err(dev,\t\t\t\t \\\n+\t\t\t\t\"Warn failed on %s:%s:%d:\" format,\t \\\n+\t\t\t\t__FILE__, __func__, __LINE__, ##arg);\t \\\n+\t\t}\t\t\t\t\t\t\t \\\n \t} while (0)\n \n /* Spinlock related methods */\n #define ena_spinlock_t rte_spinlock_t\n #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)\n-#define ENA_SPINLOCK_LOCK(spinlock, flags)\t\t\t\t\\\n+#define ENA_SPINLOCK_LOCK(spinlock, flags)\t\t\t\t \\\n \t({(void)flags; rte_spinlock_lock(&spinlock); })\n-#define ENA_SPINLOCK_UNLOCK(spinlock, flags)\t\t\t\t\\\n+#define ENA_SPINLOCK_UNLOCK(spinlock, flags)\t\t\t\t \\\n \t({(void)flags; rte_spinlock_unlock(&(spinlock)); })\n #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock)\n \n-#define q_waitqueue_t\t\t\t\\\n-\tstruct {\t\t\t\\\n-\t\tpthread_cond_t cond;\t\\\n-\t\tpthread_mutex_t mutex;\t\\\n+#define q_waitqueue_t\t\t\t\t\t\t\t \\\n+\tstruct {\t\t\t\t\t\t\t \\\n+\t\tpthread_cond_t cond;\t\t\t\t\t \\\n+\t\tpthread_mutex_t mutex;\t\t\t\t\t \\\n \t}\n \n #define ena_wait_queue_t q_waitqueue_t\n \n-#define ENA_WAIT_EVENT_INIT(waitqueue)\t\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tpthread_mutex_init(&(waitqueue).mutex, NULL);\t\t\\\n-\t\tpthread_cond_init(&(waitqueue).cond, NULL);\t\t\\\n+#define ENA_WAIT_EVENT_INIT(waitqueue)\t\t\t\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tpthread_mutex_init(&(waitqueue).mutex, NULL);\t\t \\\n+\t\tpthread_cond_init(&(waitqueue).cond, NULL);\t\t \\\n \t} while (0)\n \n-#define ENA_WAIT_EVENT_WAIT(waitevent, timeout)\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tstruct timespec wait;\t\t\t\t\t\\\n-\t\tstruct timeval now;\t\t\t\t\t\\\n-\t\tunsigned long timeout_us;\t\t\t\t\\\n-\t\tgettimeofday(&now, NULL);\t\t\t\t\\\n-\t\twait.tv_sec = now.tv_sec + timeout / 1000000UL;\t\t\\\n-\t\ttimeout_us = timeout % 1000000UL;\t\t\t\\\n-\t\twait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;\t\\\n-\t\tpthread_mutex_lock(&waitevent.mutex);\t\t\t\\\n-\t\tpthread_cond_timedwait(&waitevent.cond,\t\t\t\\\n-\t\t\t\t&waitevent.mutex, &wait);\t\t\\\n-\t\tpthread_mutex_unlock(&waitevent.mutex);\t\t\t\\\n+#define ENA_WAIT_EVENT_WAIT(waitevent, timeout)\t\t\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tstruct timespec wait;\t\t\t\t\t \\\n+\t\tstruct timeval now;\t\t\t\t\t \\\n+\t\tunsigned long timeout_us;\t\t\t\t \\\n+\t\tgettimeofday(&now, NULL);\t\t\t\t \\\n+\t\twait.tv_sec = now.tv_sec + timeout / 1000000UL;\t\t \\\n+\t\ttimeout_us = timeout % 1000000UL;\t\t\t \\\n+\t\twait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;\t \\\n+\t\tpthread_mutex_lock(&waitevent.mutex);\t\t\t \\\n+\t\tpthread_cond_timedwait(&waitevent.cond,\t\t\t \\\n+\t\t\t\t&waitevent.mutex, &wait);\t\t \\\n+\t\tpthread_mutex_unlock(&waitevent.mutex);\t\t\t \\\n \t} while (0)\n #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)\n /* pthread condition doesn't need to be rearmed after usage */\n@@ -170,104 +172,88 @@ extern int ena_logtype_com;\n \n #define ena_time_t uint64_t\n #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())\n-#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \\\n- (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n+#define ENA_GET_SYSTEM_TIMEOUT(timeout_us)\t\t\t\t \\\n+\t(timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n \n /*\n * Each rte_memzone should have unique name.\n * To satisfy it, count number of allocations and add it to name.\n */\n-extern rte_atomic32_t ena_alloc_cnt;\n-\n-#define ENA_MEM_ALLOC_COHERENT_ALIGNED(\t\t\t\t\t\\\n-\tdmadev, size, virt, phys, handle, alignment)\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tconst struct rte_memzone *mz = NULL;\t\t\t\\\n-\t\tENA_TOUCH(dmadev); ENA_TOUCH(handle);\t\t\t\\\n-\t\tif (size > 0) {\t\t\t\t\t\t\\\n-\t\t\tchar z_name[RTE_MEMZONE_NAMESIZE];\t\t\\\n-\t\t\tsnprintf(z_name, sizeof(z_name),\t\t\\\n-\t\t\t \"ena_alloc_%d\",\t\t\t\t\\\n-\t\t\t rte_atomic32_add_return(&ena_alloc_cnt, 1));\t\\\n-\t\t\tmz = rte_memzone_reserve_aligned(z_name, size,\t\\\n-\t\t\t\t\tSOCKET_ID_ANY,\t\t\t\\\n-\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\t\\\n-\t\t\t\t\talignment);\t\t\t\\\n-\t\t\thandle = mz;\t\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n-\t\tif (mz == NULL) {\t\t\t\t\t\\\n-\t\t\tvirt = NULL;\t\t\t\t\t\\\n-\t\t\tphys = 0;\t\t\t\t\t\\\n-\t\t} else {\t\t\t\t\t\t\\\n-\t\t\tmemset(mz->addr, 0, size);\t\t\t\\\n-\t\t\tvirt = mz->addr;\t\t\t\t\\\n-\t\t\tphys = mz->iova;\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n+extern rte_atomic64_t ena_alloc_cnt;\n+\n+#define ENA_MEM_ALLOC_COHERENT_ALIGNED(\t\t\t\t\t \\\n+\tdmadev, size, virt, phys, mem_handle, alignment)\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tconst struct rte_memzone *mz = NULL;\t\t\t \\\n+\t\tENA_TOUCH(dmadev);\t\t\t\t\t \\\n+\t\tif (size > 0) {\t\t\t\t\t\t \\\n+\t\t\tchar z_name[RTE_MEMZONE_NAMESIZE];\t\t \\\n+\t\t\tsnprintf(z_name, sizeof(z_name), \"ena_alloc_%\"PRIi64\"\",\\\n+\t\t\t\trte_atomic64_add_return(&ena_alloc_cnt,\t1)); \\\n+\t\t\tmz = rte_memzone_reserve_aligned(z_name, size,\t \\\n+\t\t\t\t\tSOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\\\n+\t\t\t\t\talignment);\t\t\t \\\n+\t\t\tmem_handle = mz;\t\t\t\t \\\n+\t\t}\t\t\t\t\t\t\t \\\n+\t\tif (mz == NULL) {\t\t\t\t\t \\\n+\t\t\tvirt = NULL;\t\t\t\t\t \\\n+\t\t\tphys = 0;\t\t\t\t\t \\\n+\t\t} else {\t\t\t\t\t\t \\\n+\t\t\tmemset(mz->addr, 0, size);\t\t\t \\\n+\t\t\tvirt = mz->addr;\t\t\t\t \\\n+\t\t\tphys = mz->iova;\t\t\t\t \\\n+\t\t}\t\t\t\t\t\t\t \\\n \t} while (0)\n-#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)\t\\\n-\t\tENA_MEM_ALLOC_COHERENT_ALIGNED(\t\t\t\t\\\n-\t\t\tdmadev,\t\t\t\t\t\t\\\n-\t\t\tsize,\t\t\t\t\t\t\\\n-\t\t\tvirt,\t\t\t\t\t\t\\\n-\t\t\tphys,\t\t\t\t\t\t\\\n-\t\t\thandle,\t\t\t\t\t\t\\\n-\t\t\tRTE_CACHE_LINE_SIZE)\n-#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \t\\\n-\t\t({ ENA_TOUCH(size); ENA_TOUCH(phys);\t\t\t\\\n-\t\t ENA_TOUCH(dmadev);\t\t\t\t\t\\\n-\t\t rte_memzone_free(handle); })\n-\n-#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(\t\t\t\t\\\n-\tdmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tconst struct rte_memzone *mz = NULL;\t\t\t\\\n-\t\tENA_TOUCH(dmadev); ENA_TOUCH(dev_node);\t\t\t\\\n-\t\tif (size > 0) {\t\t\t\t\t\t\\\n-\t\t\tchar z_name[RTE_MEMZONE_NAMESIZE];\t\t\\\n-\t\t\tsnprintf(z_name, sizeof(z_name),\t\t\\\n-\t\t\t \"ena_alloc_%d\",\t\t\t\t\\\n-\t\t\t rte_atomic32_add_return(&ena_alloc_cnt, 1)); \\\n-\t\t\tmz = rte_memzone_reserve_aligned(z_name, size, node, \\\n-\t\t\t\tRTE_MEMZONE_IOVA_CONTIG, alignment);\t\\\n-\t\t\tmem_handle = mz;\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n-\t\tif (mz == NULL) {\t\t\t\t\t\\\n-\t\t\tvirt = NULL;\t\t\t\t\t\\\n-\t\t\tphys = 0;\t\t\t\t\t\\\n-\t\t} else {\t\t\t\t\t\t\\\n-\t\t\tmemset(mz->addr, 0, size);\t\t\t\\\n-\t\t\tvirt = mz->addr;\t\t\t\t\\\n-\t\t\tphys = mz->iova;\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n+#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, mem_handle)\t \\\n+\t\tENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, \\\n+\t\t\tmem_handle, RTE_CACHE_LINE_SIZE)\n+#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle) \t \\\n+\t\t({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev);\t \\\n+\t\t rte_memzone_free(mem_handle); })\n+\n+#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(\t\t\t\t \\\n+\tdmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tconst struct rte_memzone *mz = NULL;\t\t\t \\\n+\t\tENA_TOUCH(dmadev); ENA_TOUCH(dev_node);\t\t\t \\\n+\t\tif (size > 0) {\t\t\t\t\t\t \\\n+\t\t\tchar z_name[RTE_MEMZONE_NAMESIZE];\t\t \\\n+\t\t\tsnprintf(z_name, sizeof(z_name), \"ena_alloc_%\"PRIi64\"\",\\\n+\t\t\t\trte_atomic64_add_return(&ena_alloc_cnt, 1)); \\\n+\t\t\tmz = rte_memzone_reserve_aligned(z_name, size,\t \\\n+\t\t\t\tnode, RTE_MEMZONE_IOVA_CONTIG, alignment); \\\n+\t\t\tmem_handle = mz;\t\t\t\t \\\n+\t\t}\t\t\t\t\t\t\t \\\n+\t\tif (mz == NULL) {\t\t\t\t\t \\\n+\t\t\tvirt = NULL;\t\t\t\t\t \\\n+\t\t\tphys = 0;\t\t\t\t\t \\\n+\t\t} else {\t\t\t\t\t\t \\\n+\t\t\tmemset(mz->addr, 0, size);\t\t\t \\\n+\t\t\tvirt = mz->addr;\t\t\t\t \\\n+\t\t\tphys = mz->iova;\t\t\t\t \\\n+\t\t}\t\t\t\t\t\t\t \\\n \t} while (0)\n-#define ENA_MEM_ALLOC_COHERENT_NODE(\t\t\t\t\t\\\n-\tdmadev, size, virt, phys, mem_handle, node, dev_node)\t\t\\\n-\t\tENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(\t\t\t\\\n-\t\t\tdmadev,\t\t\t\t\t\t\\\n-\t\t\tsize,\t\t\t\t\t\t\\\n-\t\t\tvirt,\t\t\t\t\t\t\\\n-\t\t\tphys,\t\t\t\t\t\t\\\n-\t\t\tmem_handle,\t\t\t\t\t\\\n-\t\t\tnode,\t\t\t\t\t\t\\\n-\t\t\tdev_node,\t\t\t\t\t\\\n-\t\t\tRTE_CACHE_LINE_SIZE)\n-#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tENA_TOUCH(dmadev); ENA_TOUCH(dev_node);\t\t\t\\\n-\t\tvirt = rte_zmalloc_socket(NULL, size, 0, node);\t\t\\\n+#define ENA_MEM_ALLOC_COHERENT_NODE(\t\t\t\t\t \\\n+\tdmadev, size, virt, phys, mem_handle, node, dev_node)\t\t \\\n+\t\tENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt,\tphys, \\\n+\t\t\tmem_handle, node, dev_node, RTE_CACHE_LINE_SIZE)\n+#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node)\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tENA_TOUCH(dmadev); ENA_TOUCH(dev_node);\t\t\t \\\n+\t\tvirt = rte_zmalloc_socket(NULL, size, 0, node);\t\t \\\n \t} while (0)\n \n #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)\n-#define ENA_MEM_FREE(dmadev, ptr, size)\t\t\t\t\t\\\n+#define ENA_MEM_FREE(dmadev, ptr, size)\t\t\t\t\t \\\n \t({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })\n \n #define ENA_DB_SYNC(mem_handle) ((void)mem_handle)\n \n-#define ENA_REG_WRITE32(bus, value, reg)\t\t\t\t\\\n+#define ENA_REG_WRITE32(bus, value, reg)\t\t\t\t \\\n \t({ (void)(bus); rte_write32((value), (reg)); })\n-#define ENA_REG_WRITE32_RELAXED(bus, value, reg)\t\t\t\\\n+#define ENA_REG_WRITE32_RELAXED(bus, value, reg)\t\t\t \\\n \t({ (void)(bus); rte_write32_relaxed((value), (reg)); })\n-#define ENA_REG_READ32(bus, reg)\t\t\t\t\t\\\n+#define ENA_REG_READ32(bus, reg)\t\t\t\t\t \\\n \t({ (void)(bus); rte_read32_relaxed((reg)); })\n \n #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)\n@@ -293,7 +279,7 @@ extern rte_atomic32_t ena_alloc_cnt;\n #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))\n \n #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())\n-#define ENA_GET_SYSTEM_TIMEOUT(timeout_us)\t\t\t\t\\\n+#define ENA_GET_SYSTEM_TIMEOUT(timeout_us)\t\t\t\t \\\n (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n #define ENA_WAIT_EVENTS_DESTROY(waitqueue) ((void)(waitqueue))\n \n@@ -306,14 +292,14 @@ extern rte_atomic32_t ena_alloc_cnt;\n #define READ_ONCE32(var) READ_ONCE(var)\n \n /* The size must be 8 byte align */\n-#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tint count, i;\t\t\t\t\t\t\\\n-\t\tuint64_t *to = (uint64_t *)(dst);\t\t\t\\\n-\t\tconst uint64_t *from = (const uint64_t *)(src);\t\t\\\n-\t\tcount = (size) / 8;\t\t\t\t\t\\\n-\t\tfor (i = 0; i < count; i++, from++, to++)\t\t\\\n-\t\t\trte_write64_relaxed(*from, to);\t\t\t\\\n+#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)\t\t\t\t \\\n+\tdo {\t\t\t\t\t\t\t\t \\\n+\t\tint count, i;\t\t\t\t\t\t \\\n+\t\tuint64_t *to = (uint64_t *)(dst);\t\t\t \\\n+\t\tconst uint64_t *from = (const uint64_t *)(src);\t\t \\\n+\t\tcount = (size) / 8;\t\t\t\t\t \\\n+\t\tfor (i = 0; i < count; i++, from++, to++)\t\t \\\n+\t\t\trte_write64_relaxed(*from, to);\t\t\t \\\n \t} while(0)\n \n #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n@@ -326,7 +312,5 @@ void ena_rss_key_fill(void *key, size_t size);\n \n #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0\n \n-#define ENA_PRIu64 PRIu64\n-\n #include \"ena_includes.h\"\n #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */\ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex f1ff4dad36..3c9102cd19 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -85,7 +85,7 @@ struct ena_stats {\n * Each rte_memzone should have unique name.\n * To satisfy it, count number of allocation and add it to name.\n */\n-rte_atomic32_t ena_alloc_cnt;\n+rte_atomic64_t ena_alloc_cnt;\n \n static const struct ena_stats ena_stats_global_strings[] = {\n \tENA_STAT_GLOBAL_ENTRY(wd_expired),\n", "prefixes": [ "11/22" ] }