Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92447/?format=api
{ "id": 92447, "url": "https://patches.dpdk.org/api/patches/92447/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-16-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-16-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-16-matan@nvidia.com", "date": "2021-04-29T15:47:12", "name": "[v2,15/15] crypto/mlx5: set feature flags and capabilities", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1ac5cb495f2b019f47bcc5ad0ae233732303f91d", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-16-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92447/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/92447/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CE51AA0547;\n\tThu, 29 Apr 2021 17:49:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0892041363;\n\tThu, 29 Apr 2021 17:49:08 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2061.outbound.protection.outlook.com [40.107.94.61])\n by mails.dpdk.org (Postfix) with ESMTP id 9154F4135B\n for <dev@dpdk.org>; Thu, 29 Apr 2021 17:49:06 +0200 (CEST)", "from MW4PR03CA0035.namprd03.prod.outlook.com (2603:10b6:303:8e::10)\n by CY4PR12MB1143.namprd12.prod.outlook.com (2603:10b6:903:38::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.22; Thu, 29 Apr\n 2021 15:49:04 +0000", "from CO1NAM11FT020.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:8e:cafe::74) by MW4PR03CA0035.outlook.office365.com\n (2603:10b6:303:8e::10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.27 via Frontend\n Transport; Thu, 29 Apr 2021 15:49:04 +0000", "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT020.mail.protection.outlook.com (10.13.174.149) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:49:04 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr\n 2021 15:49:02 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Jg3lOSNSnCpXXPKj3o0RzIPu4UGI6NaMn0Vpclm3czf07lGUSjqMP/NuZK/4JJOmRp34vkppKNwMtClUwh2eLvZIYIbVa0VtDG6yDmge5Gq+OK9IDBva73oDVw5HOk7clisCloui9yC/nPO14B8a7YZYz8x9veJV7IWQucRPthJmHJNGSJ5SRf3nIzrKU+8eo0gH0vLAMz13f07/VB151XopSkKkEqM917EhwB1CwtiakHahO3n81HtJshu/MsrkU5tW2fPAKSw5zszkOgg1CUtBuoVDDOZE7bVKcW97DKnOhDvfStbkGYMEFXJwWSYkEaBH/xrYSOvC0hwsaaf95A==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=pJZZmMU93XFAimwQSz/daGBLoWI/n/Qoqci/0M5/JxM=;\n b=DsBR/lK6B+4pb/OIKC6GfAP/xmcwdc6G6oIDg+MZtzus/92ci2cUCwZ94OE5llr18I5sk7qEQ+FKTWPENxyCkSW2B/fpdOLO9U4jLZm1PhNgQHotElbbEh+vqHy2frUC3xFIVCXXXRtWtK1OOTnbMRcdQZVQbNm6UR2b6pPaJU9JkSG5VO+UjRhf6fvPbXMuflfEzP/u2YXPt3KVlS67o74rDY9kD2RwW1oZWNoXBnO2+md3rimPH6/VnFmFqodU2WZm3AxRYucc2T3P+Nq40enIjxvM9ibQ7gaO2QWR3Bx5bk8AE/D126SbpELooZ7HlkD8I7X+em7ob8//8Ib+RQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=pJZZmMU93XFAimwQSz/daGBLoWI/n/Qoqci/0M5/JxM=;\n b=ObmUnLOdQex9zmQHB8U2nYpq1TUNU6Zi/oNnH4R0lcaT+Jp/Q/bjLblu82rnoSgG3sC1L8Zt7wV8fpMEhwSl0pQLb07dXJkYcOTCKrd+Xju+z3ZddN5Xcdz39zd/tgxrW6Z930hCMP6QJWXwBf6wtgHGwbH8XcVTZ0ktb/F71OVbVt3G7E8Lp2MTm0riDXejCoVPI+3hGdtFrS2yYCmHmE1RsBkeDkyitE8AQ9YC59Ae8lC2sn8ows3ZqjHBKzuxW8XUQwbY0pE9Ue8zsVu94ltsQIJPsX/Er6RS3Ddl/aOBvqnvvuqIi1snwLJp8xaHfBcyk1Y0UFv2d2lzvWJybg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed)\n header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Shiri\n Kuzin\" <shirik@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:12 +0300", "Message-ID": "<20210429154712.2820159-16-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "66ef60c5-ea9d-4042-964c-08d90b265117", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1143:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB114375CA9B86CDF7AA4E2682DF5F9@CY4PR12MB1143.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8882;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n edAPmZRR4pAF6Arces34rUf/EAFmjLAI86Mp07J7y1eMi5wtNIvEUh34a8bREoo6O49D01pW7PzjgoKgidNmuqncvXypNzMmSXqM6bXX80N5L9B8KE6Wn6keiGhJac3lDB2Xhsagm0nF/Ty+7NGFnYfI++oLUwvfcNljVgdRQwk4emHu6kRvCU+NPFhzQCR2Yn+DbCm+UVl14FZU0aggoG+JBAm36E5BhNoGX2vtDRyZFkjeJOpMxkxbnNbyP+Xu0C9vD6SGMLW5ndIzIEx9YNx9iR5I8ZeB5M9m9cO/VxvUjcfmx+oJco/WCW6m0R2NV44qwTeJBnVLY79e5tW7VCZrRklryHwRlmm2uAwXvMCd60EqXqgrp/GtaSUbKuUa06ewBit6bUSd9N9zZP4Bz0PIkOqfC42W8tRAG1bKG2KoNXmryjA5hVMt2EaS0Acy7EUvaJZpNnXj8uGwq8k5w+7jsTFo7QjhVcjXUnPf1WEspAUrxgXfLzHxwEdPJsziOfyHBcOwdegRRTeIuHZlv9rcNMHYpYWqGBifBfDBMoQyk9762B/JBrsxV2ZASZq02GwJg9M4gW3E0imKMndgNi0xuoavkwxtuDF+zcarXx7tgMl8zx9mshP9uk1zB/PYntqiXx1xHoMuGlEjUMmNBxfYHMHrRbslgXOGiZTNnkM=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(39860400002)(376002)(396003)(46966006)(36840700001)(54906003)(36860700001)(82310400003)(36906005)(47076005)(36756003)(316002)(336012)(8936002)(2906002)(6916009)(83380400001)(82740400003)(30864003)(356005)(186003)(1076003)(6666004)(16526019)(4326008)(26005)(478600001)(2616005)(7696005)(6286002)(8676002)(55016002)(70586007)(426003)(5660300002)(86362001)(107886003)(70206006)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:49:04.5659 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 66ef60c5-ea9d-4042-964c-08d90b265117", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1143", "Subject": "[dpdk-dev] [PATCH v2 15/15] crypto/mlx5: set feature flags and\n capabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nAdd the supported capabilities to the crypto driver.\n\nAdd supported feature flags.\n\nAdd crypto driver documentation.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/features/mlx5.ini | 37 ++++++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/mlx5.rst | 152 ++++++++++++++++++++++++\n doc/guides/rel_notes/release_21_05.rst | 5 +\n drivers/crypto/mlx5/mlx5_crypto.c | 39 +++++-\n 5 files changed, 231 insertions(+), 3 deletions(-)\n create mode 100644 doc/guides/cryptodevs/features/mlx5.ini\n create mode 100644 doc/guides/cryptodevs/mlx5.rst", "diff": "diff --git a/doc/guides/cryptodevs/features/mlx5.ini b/doc/guides/cryptodevs/features/mlx5.ini\nnew file mode 100644\nindex 0000000000..a89526add0\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/mlx5.ini\n@@ -0,0 +1,37 @@\n+;\n+; Features of a mlx5 crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In SGL Out = Y\n+OOP SGL In LB Out = Y\n+OOP LB In SGL Out = Y\n+OOP LB In LB Out = Y\n+Cipher multiple data units = Y\n+Cipher wrapped key = Y\n+\n+;\n+; Supported crypto algorithms of a mlx5 crypto driver.\n+;\n+[Cipher]\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n+\n+;\n+; Supported authentication algorithms of a mlx5 crypto driver.\n+;\n+[Auth]\n+\n+;\n+; Supported AEAD algorithms of a mlx5 crypto driver.\n+;\n+[AEAD]\n+\n+;\n+; Supported Asymmetric algorithms of a mlx5 crypto driver.\n+;\n+[Asymmetric]\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 279f56a002..747409c441 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -22,6 +22,7 @@ Crypto Device Drivers\n octeontx\n octeontx2\n openssl\n+ mlx5\n mvsam\n nitrox\n null\ndiff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nnew file mode 100644\nindex 0000000000..4ccec78be8\n--- /dev/null\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -0,0 +1,152 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright 2021 Mellanox Technologies, Ltd\n+\n+.. include:: <isonum.txt>\n+\n+MLX5 Crypto Driver\n+==================\n+\n+The MLX5 crypto driver library\n+(**librte_crypto_mlx5**) provides support for **Mellanox ConnectX-6**\n+family adapters.\n+\n+Overview\n+--------\n+\n+The device can provide disk encryption services, allowing data encryption\n+and decryption towards a disk. Having all encryption/decryption\n+operations done in a single device can reduce cost and overheads of the related\n+FIPS certification, as ConnectX-6 is FIPS 140-2 level-2 ready.\n+The encryption cipher is AES-XTS of 256/512 key size.\n+\n+MKEY is a memory region object in the hardware, that holds address translation information and\n+attributes per memory area. Its ID must be tied to addresses provided to the hardware.\n+The encryption operations are performed with MKEY read\\write transactions, when\n+the MKEY is configured to perform crypto operations.\n+\n+The encryption does not require text to be aligned to the AES block size (128b).\n+\n+In order to move the device to crypto operational mode, credential and KEK\n+(Key Encrypting Key) should be set as the first step.\n+The credential will be used by the software in order to perform crypto login, and the KEK is\n+the AES Key Wrap Algorithm (rfc3394) key that will be used for sensitive data\n+wrapping.\n+The credential and the AES-XTS keys should be provided to the hardware, as ciphertext\n+encrypted by the KEK.\n+\n+A keytag (64 bits) should be appended to the AES-XTS keys (before wrapping),\n+and will be validated when the hardware attempts to access it.\n+\n+For security reasons and to increase robustness, this driver only deals with virtual\n+memory addresses. The way resources allocations are handled by the kernel,\n+combined with hardware specifications that allow handling virtual memory\n+addresses directly, ensure that DPDK applications cannot access random\n+physical memory (or memory that does not belong to the current process).\n+\n+The PMD uses libibverbs and libmlx5 to access the device firmware or to\n+access the hardware components directly.\n+There are different levels of objects and bypassing abilities.\n+To get the best performances:\n+\n+- Verbs is a complete high-level generic API.\n+- Direct Verbs is a device-specific API.\n+- DevX allows to access firmware objects.\n+\n+Enabling librte_crypto_mlx5 causes DPDK applications to be linked against\n+libibverbs.\n+\n+Mellanox mlx5 PCI device can be probed by a number of different PCI devices, such as\n+net / vDPA / RegEx. To select the crypto PMD, ``class=crypto``\n+should be specified as a device parameter. The crypto device can be probed and\n+used with other Mellanox classes by adding more options in the class.\n+For example: ``class=net:crypto`` will probe both the net PMD and the crypto\n+PMD.\n+\n+When crypto engines are defined to work in wrapped import method, they come out\n+of the factory in Commissioning mode, and thus, cannot be used for crypto operations\n+yet. A dedicated tool is used for changing the mode from Commissioning to\n+Operational, while setting the first import_KEK and credential in plaintext.\n+The mlxreg dedicated tool should be used as follows:\n+\n+- Set CRYPTO_OPERATIONAL register to set the device in crypto operational mode.\n+\n+ The input to this tool is:\n+ The first credential in plaintext, 40B.\n+ The first import_KEK in plaintext: kek size 0 for 16B or 1 for 32B, kek data.\n+\n+ Example:\n+ mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL --get\n+\n+ The \"wrapped_crypto_operational\" value will be \"0x00000000\".\n+ The command to set the register should be executed only once, and all the\n+ values mentioned above should be specified in the same command.\n+\n+ Example:\n+ mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL\n+ --set \"credential[0]=0x10000000, credential[1]=0x10000000, kek[0]=0x00000000\"\n+\n+ All values not specified will remain 0.\n+ \"wrapped_crypto_going_to_commissioning\" and \"wrapped_crypto_operational\"\n+ should not be specified.\n+\n+ All the device ports should set it in order to move to operational mode.\n+\n+- Query CRYPTO_OPERATIONAL register to make sure the device is in Operational\n+ mode.\n+\n+ Example:\n+ mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL --get\n+ The \"wrapped_crypto_operational\" value will be \"0x00000001\" if the mode was\n+ successfully changed to operational mode.\n+\n+\n+Driver options\n+--------------\n+\n+- ``class`` parameter [string]\n+\n+ Select the class of the driver that should probe the device.\n+ `crypto` for the mlx5 crypto driver.\n+\n+- ``wcs_file`` parameter [string] - mandatory\n+\n+ File path including only the wrapped credential in string format of hexadecimal\n+ numbers, represent 48 bytes (8 bytes IV added by the AES key wrap algorithm).\n+\n+- ``import_kek_id`` parameter [int]\n+\n+ The identifier of the KEK, default value is 0 represents the operational\n+ register import_kek..\n+\n+- ``credential_id`` parameter [int]\n+\n+ The identifier of the credential, default value is 0 represents the operational\n+ register credential.\n+\n+- ``max_segs_num`` parameter [int]\n+\n+ Maximum number of mbuf chain segments(src or dest), default value is 8.\n+\n+- ``keytag`` parameter [int]\n+\n+ The plaintext of the keytag appanded to the AES-XTS keys, default value is 0.\n+\n+\n+Limitations\n+-----------\n+\n+- AES-XTS keys provided in Xform must include keytag and should be wrappend.\n+- The supported data-unit lengths are: 512B, 1KB, 1MB. In case the `dataunit_len`\n+ is not provided in the cipher Xform, the OP length is limitted to the above values.\n+\n+\n+Supported NICs\n+--------------\n+\n+* Mellanox\\ |reg| ConnectX\\ |reg|-6 200G MCX654106A-HCAT (2x200G)\n+\n+Prerequisites\n+-------------\n+\n+- Mellanox OFED version: **5.3**\n+ see :doc:`../../nics/mlx5` guide for more Mellanox OFED details.\ndiff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst\nindex 133a0dbbf2..dc508fc63c 100644\n--- a/doc/guides/rel_notes/release_21_05.rst\n+++ b/doc/guides/rel_notes/release_21_05.rst\n@@ -273,6 +273,11 @@ New Features\n * Added support for crypto adapter forward mode in octeontx2 event and crypto\n device driver.\n \n+* **Added support for Nvidia crypto device driver.**\n+\n+ * Added mlx5 crypto driver to support AES-XTS cipher operations.\n+ the first device to support it is ConnectX-6.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex af8985939e..c2e75905fd 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -22,6 +22,14 @@\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n #define MLX5_CRYPTO_MAX_QPS 1024\n #define MLX5_CRYPTO_MAX_SEGS 56\n+#define MLX5_CRYPTO_FEATURE_FLAGS \\\n+\t(RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \\\n+\tRTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | \\\n+\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | \\\n+\tRTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | \\\n+\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | \\\n+\tRTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \\\n+\tRTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS)\n \n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n@@ -31,8 +39,32 @@ int mlx5_crypto_logtype;\n \n uint8_t mlx5_crypto_driver_id;\n \n-const struct rte_cryptodev_capabilities\n-\t\tmlx5_crypto_caps[RTE_CRYPTO_OP_TYPE_UNDEFINED];\n+const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = {\n+\t{\t\t/* AES XTS */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_XTS,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 32,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 32\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.dataunit_set =\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES |\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES,\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n \n static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);\n \n@@ -67,7 +99,7 @@ mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n \tRTE_SET_USED(dev);\n \tif (dev_info != NULL) {\n \t\tdev_info->driver_id = mlx5_crypto_driver_id;\n-\t\tdev_info->feature_flags = 0;\n+\t\tdev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n \t\tdev_info->capabilities = mlx5_crypto_caps;\n \t\tdev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS;\n \t\tdev_info->min_mbuf_headroom_req = 0;\n@@ -954,6 +986,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n \tcrypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;\n \tcrypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;\n+\tcrypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n \tcrypto_dev->driver_id = mlx5_crypto_driver_id;\n \tpriv = crypto_dev->data->dev_private;\n \tpriv->ctx = ctx;\n", "prefixes": [ "v2", "15/15" ] }