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GET /api/patches/92446/?format=api
{ "id": 92446, "url": "https://patches.dpdk.org/api/patches/92446/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-15-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-15-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-15-matan@nvidia.com", "date": "2021-04-29T15:47:11", "name": "[v2,14/15] crypto/mlx5: add statistic get and reset operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d5347ce2c4c1a5fa60d5f335d9781a6c3c080cac", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-15-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92446/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92446/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE746A0547;\n\tThu, 29 Apr 2021 17:49:13 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6B1F141351;\n\tThu, 29 Apr 2021 17:49:01 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2040.outbound.protection.outlook.com [40.107.223.40])\n by mails.dpdk.org (Postfix) with ESMTP id 65D5D41362\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:11 +0300", "Message-ID": "<20210429154712.2820159-15-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "05fa8ba0-2465-4991-6204-08d90b264d99", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3450:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB3450FA00CD6C21E4EB19D826DF5F9@DM6PR12MB3450.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:158;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n CHRtDzzzHGg+m6FAh9w4jh+Sb7ILMPPyuDDiPLz0yi0B/pd9fw3HIVguaGPggUOpLWs6ACujVFQQl/G9qJFPbampx9womyWnYDFL8Xm/v6fj8ZCdDFx7nM4YvAGpJCXn4qVGYoIknq6K2CXbV68PlA/sGh83u8E1mh8GY8v9coGXqZOxLSUuLJV/VKjmgdAbeSJoto1OGzVKiupDb3wwT4k+ULrk5jUDMVD5j47UayMt0A9VPzJRda3cE4VY2tIYYpi8eyxKrlELmNPyuSeB+NodHUCOunNJ4L4IZUnw3BrFlp7AFOxD0HPVG2VWmNkGxoPv6HvqeZGZ2k/WPwJN/3+ndnk9dJIrdKFZhO7wDcjS99yS+k3oX4TlHecXKfoWd5Q2MMFJaENF/OlXKRBp5946ZHBtu6nYpM8BKG6Q5cHtu9nfIgTTrx/EJ15x5Up23mYqKtgwh7SuTl3MoPNTGlK7vNXYiZ2OSYtVOqoEV+YL52k6q58mrOOG4NNysOOtUpUMAdVAFDzODfZFpc/DgertPVKjkTICPbjdczg9iRsxD1v1l3/svHUMtDMWj0jpvnhOmMjelfZmNYUbuiYroqYwufetUDW+MCKeki/m2DbTdEs6nbT3U6dWSyck97aRc/rmg5jjM5vQmjl7FBVLNw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(39860400002)(376002)(396003)(136003)(46966006)(36840700001)(4326008)(36906005)(316002)(54906003)(6286002)(6666004)(5660300002)(55016002)(86362001)(16526019)(356005)(70586007)(70206006)(2906002)(7696005)(26005)(186003)(478600001)(82310400003)(36860700001)(47076005)(8676002)(107886003)(6916009)(1076003)(336012)(7636003)(82740400003)(426003)(8936002)(2616005)(36756003)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:48:58.7127 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 05fa8ba0-2465-4991-6204-08d90b264d99", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT053.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3450", "Subject": "[dpdk-dev] [PATCH v2 14/15] crypto/mlx5: add statistic get and\n reset operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nThis commit adds mlx5 crypto statistic get and reset operations.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 39 ++++++++++++++++++++++++++++---\n 1 file changed, 36 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 08a8c1e925..af8985939e 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -437,11 +437,14 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,\n \tdo {\n \t\top = *ops++;\n \t\tumr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);\n-\t\tif (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0))\n+\t\tif (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {\n+\t\t\tqp->stats.enqueue_err_count++;\n \t\t\tbreak;\n+\t\t}\n \t\tqp->ops[qp->pi] = op;\n \t\tqp->pi = (qp->pi + 1) & mask;\n \t} while (--remain);\n+\tqp->stats.enqueued_count += nb_ops;\n \trte_io_wmb();\n \tqp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);\n \trte_wmb();\n@@ -458,6 +461,7 @@ mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op)\n \t\t\t\t\t\t\t&qp->cq_obj.cqes[idx];\n \n \top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\tqp->stats.dequeue_err_count++;\n \tDRV_LOG(ERR, \"CQE ERR:%x.\\n\", rte_be_to_cpu_32(cqe->syndrome));\n }\n \n@@ -497,6 +501,7 @@ mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,\n \tif (likely(i != 0)) {\n \t\trte_io_wmb();\n \t\tqp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci);\n+\t\tqp->stats.dequeued_count += i;\n \t}\n \treturn i;\n }\n@@ -655,14 +660,42 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \treturn -1;\n }\n \n+static void\n+mlx5_crypto_stats_get(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_stats *stats)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tstats->enqueued_count += qp->stats.enqueued_count;\n+\t\tstats->dequeued_count += qp->stats.dequeued_count;\n+\t\tstats->enqueue_err_count += qp->stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp->stats.dequeue_err_count;\n+\t}\n+}\n+\n+static void\n+mlx5_crypto_stats_reset(struct rte_cryptodev *dev)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tmemset(&qp->stats, 0, sizeof(qp->stats));\n+\t}\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= mlx5_crypto_dev_start,\n \t.dev_stop\t\t\t= mlx5_crypto_dev_stop,\n \t.dev_close\t\t\t= mlx5_crypto_dev_close,\n \t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n-\t.stats_get\t\t\t= NULL,\n-\t.stats_reset\t\t\t= NULL,\n+\t.stats_get\t\t\t= mlx5_crypto_stats_get,\n+\t.stats_reset\t\t\t= mlx5_crypto_stats_reset,\n \t.queue_pair_setup\t\t= mlx5_crypto_queue_pair_setup,\n \t.queue_pair_release\t\t= mlx5_crypto_queue_pair_release,\n \t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n", "prefixes": [ "v2", "14/15" ] }