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GET /api/patches/92441/?format=api
{ "id": 92441, "url": "https://patches.dpdk.org/api/patches/92441/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-10-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-10-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-10-matan@nvidia.com", "date": "2021-04-29T15:47:06", "name": "[v2,09/15] crypto/mlx5: adjust to the multiple data unit API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "69eefa2711b2361e2c800e628ef2d0c41fee7060", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-10-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92441/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92441/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 94FF6A0547;\n\tThu, 29 Apr 2021 17:48:39 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A01654134A;\n\tThu, 29 Apr 2021 17:48:31 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2075.outbound.protection.outlook.com [40.107.237.75])\n by mails.dpdk.org (Postfix) with ESMTP id 292484135F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Shiri\n Kuzin\" <shirik@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:06 +0300", "Message-ID": "<20210429154712.2820159-10-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "fa3673d0-fb63-4501-58a5-08d90b263a84", "X-MS-TrafficTypeDiagnostic": "CH0PR12MB5267:", "X-Microsoft-Antispam-PRVS": "\n <CH0PR12MB52678F5B13621F071B8F3111DF5F9@CH0PR12MB5267.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VqK18ruD2teFyY8kHsTmJmESFjOR7yic4WDDji17NHYz2c64gGDuc6RUdezUrAfaK3XC6u7epe/WBbbI2xjtqocvL0duwSdl4Lnu379LnisAo4RMeRQQCGO4BDbBG/fHg76vuAJKmHZ4OmrG1O1jRDRbit88hYA+aOLWzFAjWnHWC4f85GtV0gKqDausLEkayzXay5tYsVe3GWWYCY6oKb8bGnJFEIZQazneaTZuvUmFP3nTYflAzu4VBEifgAC1plwusY5GJTXudip/yc5ve4x6RPtySGUEEzuJqJvvhLE/KwgephvyNMniuQ7PcAR4Rz+DxfSZGkHRc3x2royJ03nEl9OkI6mLvORmGzWjzn6Vio2LE6GikvsYHKFytlrjCfBUKt62jo5wpYIh4bMJcQSdSoKZk0ZLfyCH2/D3A7GxEY21FSzTkTDUThpmC1FdTQySOc0OS8t8dRl2HpTCE/T/yCVdRnLG4yJLh7dpuBscWwiwq/SYgWpxb0EHVa3sZkoNEA0LjbxLeKHsiF7i2+8LaY6cBeQXPFPIDApt1YV32M5mWLrUp1EEx5tT8uJWHgwbp3bw76iUknIfRvmXHtlLVwNSmfJF6WUlhJlupHBX0sOLtMQfPAQYhYYAquzR/TAwE03NZAW4DvfkdYhl3Hq4q0XYEFeiPWyCdXtQteVYusUvbeSbwUnoMsywOhEEKTzxL82TX8Fc9UlZHPHXIbS+OPmR88Pblby/KkuE+s8=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(396003)(39860400002)(376002)(36840700001)(46966006)(966005)(4326008)(70586007)(7636003)(54906003)(86362001)(316002)(55016002)(6916009)(1076003)(83380400001)(8936002)(82310400003)(2616005)(36860700001)(478600001)(7696005)(16526019)(186003)(356005)(2906002)(70206006)(47076005)(336012)(5660300002)(6666004)(8676002)(82740400003)(36906005)(26005)(107886003)(6286002)(36756003)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:48:26.6251 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fa3673d0-fb63-4501-58a5-08d90b263a84", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5267", "Subject": "[dpdk-dev] [PATCH v2 09/15] crypto/mlx5: adjust to the multiple\n data unit API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nIn AES-XTS the data to be encrypted\\decrypted does not have to be\nin multiples of 16B size, the unit of data is called data-unit.\n\nAs a result of patch [1] a new field is added to the cipher capability,\ncalled dataunit_set, where the devices can report the range of\nsupported data-unit sizes.\n\nThe new field enables saving the data-unit size in the session\nstructure to the block size pointer variable in order to support\nseveral data-unit sizes.\n\n[1] https://www.mail-archive.com/dev@dpdk.org/msg205337.html\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 44038f0e05..1dcebce04c 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -48,6 +48,11 @@ struct mlx5_crypto_session {\n \t * bsf_size, bsf_p_type, encryption_order and encryption standard,\n \t * saved in big endian format.\n \t */\n+\tuint32_t bsp_res;\n+\t/*\n+\t * crypto_block_size_pointer and reserved 24 bits saved in big endian\n+\t * format.\n+\t */\n \tuint32_t iv_offset:16;\n \t/* Starting point for Initialisation Vector. */\n \tstruct mlx5_crypto_dek *dek; /* Pointer to dek struct. */\n@@ -171,6 +176,24 @@ mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n \t\t\t MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |\n \t\t\t encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |\n \t\t\t MLX5_ENCRYPTION_STANDARD_AES_XTS);\n+\tswitch (xform->cipher.dataunit_len) {\n+\tcase 0:\n+\t\tsess_private_data->bsp_res = 0;\n+\t\tbreak;\n+\tcase 512:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_512B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tcase 4096:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_4096B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Cipher data unit length is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n \tsess_private_data->iv_offset = cipher->iv.offset;\n \tsess_private_data->dek_id =\n \t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n", "prefixes": [ "v2", "09/15" ] }