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GET /api/patches/92439/?format=api
{ "id": 92439, "url": "https://patches.dpdk.org/api/patches/92439/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-8-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-8-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-8-matan@nvidia.com", "date": "2021-04-29T15:47:04", "name": "[v2,07/15] crypto/mlx5: add memory region management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d9bda8bc294ed6f34f88e4d7b48a36e3ac64ec8f", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-8-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92439/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=gQqzmvI/ghOinzdZlqC0h3O9t/8X2apd1BOZW5jqDy4=;\n b=XxYPvO0hV4Hg9lZnv88zcjeVNDeGcJyw70r8TL5qrIqUggqkZ3Pi9MJ5AhnWO64KaAbdJRlnebxO80tr04mG3Wf6xkEQbEHQHR6SpqrgOhaDsFM3FtVc0UQ//AsP2xZG/eqrJNb3p4abu8JSF9Ls8MHuukQS91UiH8ZXSmi+IBazp1ol2+lAvPgnnXKVVrlg6mqf4hKDbdB/XdgArCdlSBpfzfIoH+BY/DGnyZ8WAo+3ao8y6sg9ZAY/zGarhLOnMkZUlsOdzf0k1ph7yZobCFlRSpv/jqpmWvkMeyZZO2gaGEjs2o2pyNL4ilyC1nDLADXMbrFNVfP2tf8pGrFRgg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed)\n header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Shiri\n Kuzin\" <shirik@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:04 +0300", "Message-ID": "<20210429154712.2820159-8-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", 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SFS:(4636009)(396003)(376002)(346002)(39860400002)(136003)(46966006)(36840700001)(36906005)(86362001)(316002)(4326008)(2906002)(36860700001)(6286002)(8936002)(6916009)(8676002)(7696005)(26005)(7636003)(2616005)(54906003)(82740400003)(70206006)(55016002)(6666004)(107886003)(16526019)(5660300002)(47076005)(70586007)(186003)(426003)(36756003)(336012)(478600001)(82310400003)(1076003)(356005)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:48:15.1031 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 949b7fd4-d7dc-4345-664a-08d90b26339b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT006.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN1PR12MB2526", "Subject": "[dpdk-dev] [PATCH v2 07/15] crypto/mlx5: add memory region\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nMellanox user space drivers don't deal with physical addresses as part\nof a memory protection mechanism.\nThe device translates the given virtual address to a physical address\nusing the given memory key as an address space identifier.\nThat's why any mbuf virtual address is moved directly to the HW\ndescriptor(WQE).\n\nThe mapping between the virtual address to the physical address is saved\nin MR configured by the kernel to the HW.\n\nEach MR has a key that should also be moved to the WQE by the SW.\n\nWhen the SW sees an unmapped address, it extends the address range and\ncreates a MR using a system call.\n\nAdd memory region cache management:\n\t- 2 level cache per queue-pair - no locks.\n\t- 1 shared cache between all the queues using a lock.\n\nUsing this way, the MR key search per data-path address is optimized.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 20 ++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto.h | 3 +++\n 2 files changed, 23 insertions(+)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 495d5448b2..79e3d3ee45 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -209,6 +209,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n \t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n \tif (qp->umem_buf != NULL)\n \t\trte_free(qp->umem_buf);\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n \tmlx5_devx_cq_destroy(&qp->cq_obj);\n \trte_free(qp);\n \tdev->data->queue_pairs[qp_id] = NULL;\n@@ -288,6 +289,13 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n \t\tgoto error;\n \t}\n+\tif (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n+\t\t\t priv->dev_config.socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n \tattr.pd = priv->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n \tattr.cqn = qp->cq_obj.cq->id;\n@@ -476,6 +484,17 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n+\tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n+\t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n+\t\tmlx5_crypto_hw_global_release(priv);\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n+\tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n@@ -495,6 +514,7 @@ mlx5_crypto_pci_remove(struct rte_pci_device *pdev)\n \t\tTAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n \tif (priv) {\n+\t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex f5313b89f2..397267d249 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -12,6 +12,7 @@\n \n #include <mlx5_common_utils.h>\n #include <mlx5_common_devx.h>\n+#include <mlx5_common_mr.h>\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n@@ -27,6 +28,7 @@ struct mlx5_crypto_priv {\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n+\tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n };\n \n struct mlx5_crypto_qp {\n@@ -36,6 +38,7 @@ struct mlx5_crypto_qp {\n \tvoid *umem_buf;\n \tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n+\tstruct mlx5_mr_ctrl mr_ctrl;\n };\n \n struct mlx5_crypto_dek {\n", "prefixes": [ "v2", "07/15" ] }