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GET /api/patches/92435/?format=api
{ "id": 92435, "url": "https://patches.dpdk.org/api/patches/92435/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-4-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210429154712.2820159-4-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210429154712.2820159-4-matan@nvidia.com", "date": "2021-04-29T15:47:00", "name": "[v2,03/15] crypto/mlx5: support session operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b8ef2bd24baad36f0d8483fa88217d463c629c9f", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210429154712.2820159-4-matan@nvidia.com/mbox/", "series": [ { "id": 16765, "url": "https://patches.dpdk.org/api/series/16765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16765", "date": "2021-04-29T15:46:57", "name": "drivers: introduce mlx5 crypto PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16765/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92435/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92435/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4E2F5A0547;\n\tThu, 29 Apr 2021 17:47:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 68E2B41341;\n\tThu, 29 Apr 2021 17:47:53 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2066.outbound.protection.outlook.com [40.107.93.66])\n by mails.dpdk.org (Postfix) with ESMTP id 0AC0241341\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Matan Azrad <matan@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>, \"Shiri\n Kuzin\" <shirik@nvidia.com>", "Date": "Thu, 29 Apr 2021 18:47:00 +0300", "Message-ID": "<20210429154712.2820159-4-matan@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210429154712.2820159-1-matan@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210429154712.2820159-1-matan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d7a3bf5e-6dff-49cb-abe4-08d90b2624e4", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB4093:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB40933B8A1CE84D7D7EB30D43DF5F9@MN2PR12MB4093.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4303;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n AOj+hlxFncdJr8ve4E4e1mXVJpp8VTnMaOfA4JwJwLmqEcdvk54RphU4RXwX/b4ZGDL+sJ9SXzlo7g4rDnsL9GQc1Q0ga6ZbYmeP9mmbQAxp4KhxwoO03CJGsIwbGOdESpn334JmqLE0BGrN4hskmEfmIfdbIqh32VPveOArpT7xUp6mMJVivCqeHoOoXViPA9TLvpp7N8yq3nEOXU8oqTUMOeGa2pZ0cHqCNJYbf0rAAZkoe/E86B8DjKTqz26+QOlGrxlPFtc00o4OGyhDFWiRsfruzuKtgEymZUD75tspwPZsP8X6G7Qwp/CcZQfffBGrKL9HYUgkRPyqpqRZfUYcT39aoXmonrdoYVS9dskW7/Y/x4TBE97fXTWct6iVCd1J3hEF1dfufBmbopVM0CeI/7N7TjTybT6y8pmF9N/FAFtukZuVDV+FbRmdsFKP0Fn5/V/l63Ch+FwijfN3x6oCQ7JBlkKMgRREmFqbVpPvfiIujulH4cInUeRLaGWl40Mft1DqXWp8Bfrz8Et1X8caWk0/ns/LBlFyqPyVFz2M1Bi5M32j8B0Ov8tFQ5hdDAdfiKloBcWtR+7jCmYeZGvBLuxfWIq9RI8ivym+h4SU31ICAlLXeEE4uc6KwqNPcgRCqBg27KqEwHxmuFa0jLOVai8TsV2mYUUp3UgdLxo=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(346002)(39860400002)(136003)(396003)(46966006)(36840700001)(82740400003)(55016002)(316002)(1076003)(54906003)(2616005)(6666004)(426003)(36906005)(8676002)(16526019)(4326008)(107886003)(6286002)(2906002)(83380400001)(70586007)(8936002)(336012)(356005)(6916009)(26005)(5660300002)(7696005)(86362001)(36860700001)(478600001)(70206006)(47076005)(7636003)(36756003)(186003)(82310400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2021 15:47:50.4265 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d7a3bf5e-6dff-49cb-abe4-08d90b2624e4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT065.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4093", "Subject": "[dpdk-dev] [PATCH v2 03/15] crypto/mlx5: support session operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nSessions are used in symmetric transformations in order to prepare\nobjects and data for packet processing stage.\n\nA mlx5 session includes iv_offset, pointer to mlx5_crypto_dek struct,\nbsf_size, bsf_p_type, encryption_order and encryption standard.\n\nImplement the next session operations:\n mlx5_crypto_sym_session_get_size- returns the size of the mlx5\n\tsession struct.\n\tmlx5_crypto_sym_session_configure- prepares the DEK hash-list\n\tand saves all the session data.\n\tmlx5_crypto_sym_session_clear - destroys the DEK hash-list.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 96 ++++++++++++++++++++++++++++++-\n 1 file changed, 93 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex e7c70c521f..c494ed00d1 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -3,6 +3,7 @@\n */\n \n #include <rte_malloc.h>\n+#include <rte_mempool.h>\n #include <rte_errno.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n@@ -36,6 +37,24 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n+struct mlx5_crypto_session {\n+\tuint32_t bs_bpt_eo_es;\n+\t/*\n+\t * bsf_size, bsf_p_type, encryption_order and encryption standard,\n+\t * saved in big endian format.\n+\t */\n+\tuint32_t iv_offset:16;\n+\t/* Starting point for Initialisation Vector. */\n+\tstruct mlx5_crypto_dek *dek; /* Pointer to dek struct. */\n+\tuint32_t dek_id; /* DEK ID */\n+} __rte_packed;\n+\n+static unsigned int\n+mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct mlx5_crypto_session);\n+}\n+\n static int\n mlx5_crypto_dev_configure(struct rte_cryptodev *dev,\n \t\tstruct rte_cryptodev_config *config __rte_unused)\n@@ -58,6 +77,77 @@ mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n \treturn 0;\n }\n \n+static int\n+mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t\t struct rte_cryptodev_sym_session *session,\n+\t\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data;\n+\tstruct rte_crypto_cipher_xform *cipher;\n+\tuint8_t encryption_order;\n+\tint ret;\n+\n+\tif (unlikely(xform->next != NULL)) {\n+\t\tDRV_LOG(ERR, \"Xform next is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) ||\n+\t\t (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) {\n+\t\tDRV_LOG(ERR, \"Only AES-XTS algorithm is supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tret = rte_mempool_get(mp, (void *)&sess_private_data);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Failed to get session %p private data from mempool.\",\n+\t\t\tsess_private_data);\n+\t\treturn -ENOMEM;\n+\t}\n+\tcipher = &xform->cipher;\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);\n+\tif (sess_private_data->dek == NULL) {\n+\t\trte_mempool_put(mp, sess_private_data);\n+\t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tif (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY;\n+\telse\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE;\n+\tsess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32\n+\t\t\t(MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET |\n+\t\t\t MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |\n+\t\t\t encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |\n+\t\t\t MLX5_ENCRYPTION_STANDARD_AES_XTS);\n+\tsess_private_data->iv_offset = cipher->iv.offset;\n+\tsess_private_data->dek_id =\n+\t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n+\t\t\t\t\t 0xffffff);\n+\tset_sym_session_private_data(session, dev->driver_id,\n+\t\t\t\t sess_private_data);\n+\tDRV_LOG(DEBUG, \"Session %p was configured.\", sess_private_data);\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_sym_session *sess)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data =\n+\t\t\tget_sym_session_private_data(sess, dev->driver_id);\n+\n+\tif (unlikely(sess_private_data == NULL)) {\n+\t\tDRV_LOG(ERR, \"Failed to get session %p private data.\",\n+\t\t\t\tsess_private_data);\n+\t\treturn;\n+\t}\n+\tmlx5_crypto_dek_destroy(priv, sess_private_data->dek);\n+\tDRV_LOG(DEBUG, \"Session %p was cleared.\", sess_private_data);\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= NULL,\n@@ -68,9 +158,9 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.stats_reset\t\t\t= NULL,\n \t.queue_pair_setup\t\t= NULL,\n \t.queue_pair_release\t\t= NULL,\n-\t.sym_session_get_size\t\t= NULL,\n-\t.sym_session_configure\t\t= NULL,\n-\t.sym_session_clear\t\t= NULL,\n+\t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n+\t.sym_session_configure\t\t= mlx5_crypto_sym_session_configure,\n+\t.sym_session_clear\t\t= mlx5_crypto_sym_session_clear,\n \t.sym_get_raw_dp_ctx_size\t= NULL,\n \t.sym_configure_raw_dp_ctx\t= NULL,\n };\n", "prefixes": [ "v2", "03/15" ] }