Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92269/?format=api
{ "id": 92269, "url": "https://patches.dpdk.org/api/patches/92269/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-5-bingz@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210427153811.11554-5-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210427153811.11554-5-bingz@nvidia.com", "date": "2021-04-27T15:37:58", "name": "[04/17] net/mlx5: initialization of CT management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0eca772f65579e24642d095dbfb06cb040ffcadc", "submitter": { "id": 1976, "url": "https://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-5-bingz@nvidia.com/mbox/", "series": [ { "id": 16705, "url": "https://patches.dpdk.org/api/series/16705/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16705", "date": "2021-04-27T15:37:54", "name": "conntrack support in mlx5 PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/16705/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/92269/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/92269/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2254EA0A02;\n\tTue, 27 Apr 2021 17:39:01 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 68DF94126C;\n\tTue, 27 Apr 2021 17:38:51 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2050.outbound.protection.outlook.com [40.107.243.50])\n by mails.dpdk.org (Postfix) with ESMTP id 7FF6E4126C\n for <dev@dpdk.org>; Tue, 27 Apr 2021 17:38:49 +0200 (CEST)", "from MWHPR14CA0062.namprd14.prod.outlook.com (2603:10b6:300:81::24)\n by MWHPR12MB1405.namprd12.prod.outlook.com (2603:10b6:300:13::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.25; Tue, 27 Apr\n 2021 15:38:47 +0000", "from CO1NAM11FT005.eop-nam11.prod.protection.outlook.com\n (2603:10b6:300:81:cafe::b) by MWHPR14CA0062.outlook.office365.com\n (2603:10b6:300:81::24) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.22 via Frontend\n Transport; Tue, 27 Apr 2021 15:38:47 +0000", "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4065.21 via Frontend Transport; Tue, 27 Apr 2021 15:38:47 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Apr\n 2021 15:38:45 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=GwSNVgadCr4Z9zkP4wz1YL7s0bR23qmtOi9r9oHSXP3Ct1XMgfPDrhcLhAMFIet1ENk9jp9Vj2J3nRyxuo6SuR4awXkNjM3NfTqFIRS3ogto7q5IgsaInj5iPpbsngLwaSicub8919EeSvJhc8yU2NUQ+3bnq+QIuXvimuloVfNqBPwbcYbwXEuI88VyEM+s/iRmM12DAsqFAui9vyC0RUCvoiD6w8LOpA0IQ/6jGsoyVde+8GBIONIPUb/gLWwF73/SL42IhVijDKUMSabNWIZRoEq3Suj34y2SbIx7kHyrlGuxIP2Jlvra5h8ainN/IvRktTuv9KmeoTglLH1bVA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=8cCTDgLAM12wnsXL4y3ndg7ivDmQmMKZ8aDoWj8baIs=;\n b=VX3VGP8z35ukqrMvYSYK67o2/UWCjoiBO5MyUaLgKdTrIJVgJGUZ1yZu4Vdzvd5DusfgE3UKNfEBE0noqa2g/Mj26YwcYdQ61DgZqmt+j4GYAh/3I3rjQ1dvgAoTw3pZP26D/iZ5D94vB+zlNPYKJDaeKgfyAp0Wv9U1B0HdnTqDQYLkSJj6w9u8IUZoGLnQs0QEM/auqkXreEck35kDkXH6w4btZyaQehG0GXUEqGMn25e7B8xYGgywgwWci8AH4tfbCXcoL5vzEAozIEDi8aZXwKObymdBT/9py+jV52w8zveO8QUobt6Mq0V70GuFlcfKQHRTNtv1/J20wtrptw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=8cCTDgLAM12wnsXL4y3ndg7ivDmQmMKZ8aDoWj8baIs=;\n b=Ss7pgCG4C2FhngkY62T19kQphUpBkPgftd453b5G2m2HY/2wR3NwUDcgQ/Gtn9Hm7Kcq9Bnw1LEynma3fBGoVivOeLrWsIq5FcKiYok407oLWx2yLhxuyvWhtlkWOUesERsFCTe3kySCiG4hwn8kHXJsNypD365sA2IxHygzwTB5rwFrSZvza0NOzMMn2JbalDLcKT0tI6WNtbK8/eQE2wtLuGbGmZ/AUW6NKxH9AlYmKggAhITCVH5spPcqzyMYTpcnGHIYm/L3puxXrHq5QvNxmu+AfSJNEhCDKbZWxxZOvUcz9RqWiX4n/U6TIqCly/vlCTTDFm0+qh0qs81IPg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Tue, 27 Apr 2021 18:37:58 +0300", "Message-ID": "<20210427153811.11554-5-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210427153811.11554-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b8e4056c-181b-46d6-270c-08d909928c65", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1405:", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB140545B5228582087AB1D217D0419@MWHPR12MB1405.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4941;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n q//W5QNGNZi+Kzfdo+QqWqQKsD+9HxLQr52N+nTXKB7hZ/jZbDxR3ymc7BfGTVG9H822eLx05S1ww775I58TQh7iULURnp5NsWzaEjZhVzkspqwgaLTz6LKvuQ6JuGPK6zynpj5/CRykEWSdVSSl7JTcC4U0ZcSeSJjnV/zPCOdiXyuFHN4G35QOR5PPz4rqkzTPOlpu0g8Wle5Qs/CGuybstDRb1MjBwDV4NibsjoyuYP1xY1kdHCls33cWi0OMZKYDaK20dI7HUtz7FKYZYlDrUBaXMZLV0YeECLng0ShjyAc6+hvnQD+X1paSg2om9JRC3SF0yENClQ8bNNVB7lVNBtCg4pXxAM7HnCmLNyMajpjqCBUuOn5jOLFeonU/dH83cPmfCMvlr+gcyFbjoROuh7RjQKXd7Qg/DcR2bi4E5egbTrrKgbPj0Wf+os3Q6TsvkatO0/gqicdwO/b5AP2gDpc3eNkCd4yZ7f2cMN1dXzNzaP+4gxy1cuILNspp6yhxTexFfeZYNbXje1VLpx75pB80R/xuT4gorzpcQtOGh7mDUmlZGsVXr41A2lPyMVSBttOTpoRi2yffy2pYhz/lUqBiNEj4CNqpBlGOyVDh8SWEtIVNVh88FGEx5JOBnB/QMt5ZbkQaEanfUycsfr/hiWues3l/cJjfJJQzT4A=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(376002)(346002)(136003)(39860400002)(36840700001)(46966006)(8676002)(426003)(82740400003)(6286002)(186003)(82310400003)(86362001)(6636002)(2906002)(47076005)(107886003)(5660300002)(70206006)(478600001)(6666004)(26005)(4326008)(70586007)(7696005)(8936002)(7636003)(336012)(83380400001)(54906003)(110136005)(2616005)(36756003)(36906005)(316002)(55016002)(356005)(16526019)(1076003)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2021 15:38:47.3691 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b8e4056c-181b-46d6-270c-08d909928c65", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT005.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1405", "Subject": "[dpdk-dev] [PATCH 04/17] net/mlx5: initialization of CT management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The definitions of ASO connection tracking objects management\nstructures are added.\n\nConsidering performance, the bulk allocation of ASO CT objects\nshould be used. The maximal value per bulk and the granularity could\nbe fetched from HCA capabilities 2. Right now, a fixed number of 64\nis used for each bulk for a better management purpose.\n\nThe ASO QP for CT is initialized, the SQ will be used for both\nmodify and query command.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 13 +++++++++++\n drivers/net/mlx5/mlx5.c | 36 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 50 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_aso.c | 49 +++++++++++++++++++++++++++++++++++++++\n 4 files changed, 148 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 17d0533..e3a40ac 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1322,6 +1322,19 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tDRV_LOG(DEBUG, \"Flow Hit ASO is supported.\");\n \t\t}\n #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */\n+#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \\\n+\tdefined(HAVE_MLX5_DR_ACTION_ASO_CT)\n+\t\tif (config->hca_attr.ct_offload &&\n+\t\t priv->mtr_color_reg == REG_C_3) {\n+\t\t\terr = mlx5_flow_aso_ct_mng_init(sh);\n+\t\t\tif (err) {\n+\t\t\t\terr = -err;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\tDRV_LOG(DEBUG, \"CT ASO is supported.\");\n+\t\t\tsh->ct_aso_en = 1;\n+\t\t}\n+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */\n #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)\n \t\tif (config->hca_attr.log_max_ft_sampler_num > 0 &&\n \t\t config->dv_flow_en) {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 19ffa16..a884234 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -670,6 +670,42 @@ mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)\n \t}\n }\n \n+/*\n+ * Initialize the ASO connection tracking structure.\n+ *\n+ * @param[in] sh\n+ * Pointer to mlx5_dev_ctx_shared object.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tint err;\n+\n+\tif (sh->ct_mng)\n+\t\treturn 0;\n+\tsh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n+\tif (!sh->ct_mng) {\n+\t\tDRV_LOG(ERR, \"ASO CT management allocation failed.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\terr = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);\n+\tif (err) {\n+\t\tmlx5_free(sh->ct_mng);\n+\t\t/* rte_errno should be extracted from the failure. */\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\trte_spinlock_init(&sh->ct_mng->ct_sl);\n+\trte_rwlock_init(&sh->ct_mng->resize_rwl);\n+\tLIST_INIT(&sh->ct_mng->free_cts);\n+\treturn 0;\n+}\n+\n /**\n * Initialize the flow resources' indexed mempool.\n *\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 378b68e..0a7e03e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -991,6 +991,52 @@ struct mlx5_bond_info {\n \t} ports[MLX5_BOND_MAX_PORTS];\n };\n \n+/* Number of connection tracking objects per pool: must be a power of 2. */\n+#define MLX5_ASO_CT_ACTIONS_PER_POOL 64\n+\n+/* ASO Conntrack state. */\n+enum mlx5_aso_ct_state {\n+\tASO_CONNTRACK_FREE, /* Inactive, in the free list. */\n+\tASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */\n+\tASO_CONNTRACK_READY, /* CQE received w/o error. */\n+\tASO_CONNTRACK_QUERY, /* WQE for query sent. */\n+\tASO_CONNTRACK_MAX, /* Guard. */\n+};\n+\n+/* Generic ASO connection tracking structure. */\n+struct mlx5_aso_ct_action {\n+\tLIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */\n+\tvoid *dr_action_orig; /* General action object for original dir. */\n+\tvoid *dr_action_rply; /* General action object for reply dir. */\n+\tuint32_t refcnt; /* Action used count in device flows. */\n+\tuint16_t offset; /* Offset of ASO CT in DevX objects bulk. */\n+\tuint16_t peer; /* The only peer port index could also use this CT. */\n+\tuint8_t state; /* ASO CT state. */\n+\tbool is_original; /* The direction of the DR action to be used. */\n+};\n+\n+/* ASO connection tracking software pool definition. */\n+struct mlx5_aso_ct_pool {\n+\tuint16_t index; /* Pool index in pools array. */\n+\tstruct mlx5_devx_obj *devx_obj;\n+\t/* The first devx object in the bulk, used for freeing (not yet). */\n+\tstruct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];\n+\t/* CT action structures bulk. */\n+};\n+\n+LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);\n+\n+/* Pools management structure for ASO connection tracking pools. */\n+struct mlx5_aso_ct_pools_mng {\n+\tstruct mlx5_aso_ct_pool **pools;\n+\tuint16_t n; /* Total number of pools. */\n+\tuint16_t next; /* Number of pools in use, index of next free pool. */\n+\trte_spinlock_t ct_sl; /* The ASO CT free list lock. */\n+\trte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */\n+\tstruct aso_ct_list free_cts; /* Free ASO CT objects list. */\n+\tstruct mlx5_aso_sq aso_sq; /* ASO queue objects. */\n+};\n+\n /*\n * Shared Infiniband device context for Master/Representors\n * which belong to same IB device with multiple IB ports.\n@@ -1004,6 +1050,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t sq_ts_format:2; /* SQ timestamp formats supported. */\n \tuint32_t qp_ts_format:2; /* QP timestamp formats supported. */\n \tuint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */\n+\tuint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tvoid *ctx; /* Verbs/DV/DevX context. */\n@@ -1066,6 +1113,8 @@ struct mlx5_dev_ctx_shared {\n \trte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */\n \tstruct mlx5_flow_mtr_mng *mtrmng;\n \t/* Meter management structure. */\n+\tstruct mlx5_aso_ct_pools_mng *ct_mng;\n+\t/* Management data for ASO connection tracking. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \n@@ -1363,6 +1412,7 @@ bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);\n int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);\n int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);\n int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);\n+int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);\n \n /* mlx5_ethdev.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex 20cd4fe..d0aa09f 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -212,6 +212,44 @@ mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)\n \t}\n }\n \n+/*\n+ * Initialize Send Queue used for ASO connection tracking.\n+ *\n+ * @param[in] sq\n+ * ASO SQ to initialize.\n+ */\n+static void\n+mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)\n+{\n+\tvolatile struct mlx5_aso_wqe *restrict wqe;\n+\tint i;\n+\tint size = 1 << sq->log_desc_n;\n+\tuint64_t addr;\n+\n+\t/* All the next fields state should stay constant. */\n+\tfor (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {\n+\t\twqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |\n+\t\t\t\t\t\t\t (sizeof(*wqe) >> 4));\n+\t\t/* One unique MR for the query data. */\n+\t\twqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);\n+\t\t/* Magic number 64 represents the length of a ASO CT obj. */\n+\t\taddr = (uint64_t)((uintptr_t)sq->mr.buf + i * 64);\n+\t\twqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));\n+\t\twqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);\n+\t\twqe->aso_cseg.operand_masks = rte_cpu_to_be_32\n+\t\t\t(0u |\n+\t\t\t (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |\n+\t\t\t (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |\n+\t\t\t (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |\n+\t\t\t (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));\n+\t\t/*\n+\t\t * Data mask may be different for each modification.\n+\t\t * In most cases, a full modification with mask UINT64_MAX is\n+\t\t * used to update all 64 bytes.\n+\t\t */\n+\t}\n+}\n+\n /**\n * Create Send Queue used for ASO access.\n *\n@@ -317,6 +355,17 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\t\treturn -1;\n \t\tmlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);\n \t\tbreak;\n+\tcase ASO_OPC_MOD_CONNECTION_TRACKING:\n+\t\t/* 64B per object for query. */\n+\t\tif (mlx5_aso_devx_reg_mr(sh->ctx, 64 * sq_desc_n,\n+\t\t\t&sh->ct_mng->aso_sq.mr, 0, sh->pdn))\n+\t\t\treturn -1;\n+\t\tif (mlx5_aso_sq_create(sh->ctx, &sh->ct_mng->aso_sq, 0,\n+\t\t\t\tsh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n+\t\t\t\tsh->sq_ts_format))\n+\t\t\treturn -1;\n+\t\tmlx5_aso_ct_init_sq(&sh->ct_mng->aso_sq);\n+\t\tbreak;\n \tdefault:\n \t\tDRV_LOG(ERR, \"Unknown ASO operation mode\");\n \t\treturn -1;\n", "prefixes": [ "04/17" ] }