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{
    "id": 91582,
    "url": "https://patches.dpdk.org/api/patches/91582/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210415151135.2098674-7-lizh@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210415151135.2098674-7-lizh@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210415151135.2098674-7-lizh@nvidia.com",
    "date": "2021-04-15T15:11:26",
    "name": "[v5,06/14] common/mlx5: add definitions for ASO flow meter",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "cce5a066c9bd3cb7fbd9a6d5dec19c66442a2753",
    "submitter": {
        "id": 1967,
        "url": "https://patches.dpdk.org/api/people/1967/?format=api",
        "name": "Li Zhang",
        "email": "lizh@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210415151135.2098674-7-lizh@nvidia.com/mbox/",
    "series": [
        {
            "id": 16417,
            "url": "https://patches.dpdk.org/api/series/16417/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16417",
            "date": "2021-04-15T15:11:20",
            "name": "Add ASO meter support in MLX5 PMD",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/16417/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/91582/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/91582/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB61BA0C3F;\n\tThu, 15 Apr 2021 17:12:13 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 10D6D162317;\n\tThu, 15 Apr 2021 17:11:57 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 50185162300\n for <dev@dpdk.org>; Thu, 15 Apr 2021 17:11:51 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 15 Apr 2021 18:11:47 +0300",
            "from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13FFBjPL032677;\n Thu, 15 Apr 2021 18:11:47 +0300"
        ],
        "From": "Li Zhang <lizh@nvidia.com>",
        "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com, shahafs@nvidia.com",
        "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com",
        "Date": "Thu, 15 Apr 2021 18:11:26 +0300",
        "Message-Id": "<20210415151135.2098674-7-lizh@nvidia.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20210415151135.2098674-1-lizh@nvidia.com>",
        "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <20210415151135.2098674-1-lizh@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v5 06/14] common/mlx5: add definitions for ASO\n flow meter",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds different PRM definitions, related to ASO flow meter\nfeature, in MLX5 PMD code.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 75 ++++++++++++++++++++++++++++++++--\n 1 file changed, 71 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 403ba80978..c6d8060bb9 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1129,6 +1129,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n \t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n \n@@ -1514,7 +1516,15 @@ struct mlx5_ifc_qos_cap_bits {\n \tu8 reserved_at_c0[0x10];\n \tu8 max_qos_para_vport[0x10];\n \tu8 max_tsar_bw_share[0x20];\n-\tu8 reserved_at_100[0x6e8];\n+\tu8 nic_element_type[0x10];\n+\tu8 nic_tsar_type[0x10];\n+\tu8 reserved_at_120[0x3];\n+\tu8 log_meter_aso_granularity[0x5];\n+\tu8 reserved_at_128[0x3];\n+\tu8 log_meter_aso_max_alloc[0x5];\n+\tu8 reserved_at_130[0x3];\n+\tu8 log_max_num_meter_aso[0x5];\n+\tu8 reserved_at_138[0x6b0];\n };\n \n struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n@@ -2284,6 +2294,8 @@ struct mlx5_ifc_flow_meter_parameters_bits {\n \tu8         eir_mantissa[0x8];\n \tu8         reserved_at_8[0x60];\t\t// 14h-1Ch\n };\n+#define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)\n+#define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8\n \n enum {\n \tMLX5_CQE_SIZE_64B = 0x0,\n@@ -2411,6 +2423,7 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n+\tMLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,\n };\n \n@@ -2419,7 +2432,9 @@ struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n \tu8 reserved_at_10[0x20];\n \tu8 obj_type[0x10];\n \tu8 obj_id[0x20];\n-\tu8 reserved_at_60[0x20];\n+\tu8 reserved_at_60[0x3];\n+\tu8 log_obj_range[0x5];\n+\tu8 reserved_at_58[0x18];\n };\n \n struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n@@ -2565,6 +2580,18 @@ struct mlx5_ifc_create_flow_hit_aso_in_bits {\n \tstruct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;\n };\n \n+struct mlx5_ifc_flow_meter_aso_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x48];\n+\tu8 access_pd[0x18];\n+\tu8 reserved_at_a0[0x160];\n+\tu8 parameters[0x200];\n+};\n+\n+struct mlx5_ifc_create_flow_meter_aso_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;\n+};\n enum mlx5_access_aso_opc_mod {\n \tASO_OPC_MOD_IPSEC = 0x0,\n \tASO_OPC_MOD_CONNECTION_TRACKING = 0x1,\n@@ -2618,11 +2645,51 @@ struct mlx5_aso_cseg {\n \tuint64_t data_mask;\n } __rte_packed;\n \n+/* A meter data segment - 2 per ASO WQE. */\n+struct mlx5_aso_mtr_dseg {\n+\tuint32_t v_bo_sc_bbog_mm;\n+\t/*\n+\t * bit 31: valid, 30: bucket overflow, 28-29: start color,\n+\t * 27: both buckets on green, 24-25: meter mode.\n+\t */\n+\tuint32_t reserved;\n+\tuint32_t cbs_cir;\n+\t/*\n+\t * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,\n+\t * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.\n+\t */\n+\tuint32_t c_tokens;\n+\tuint32_t ebs_eir;\n+\t/*\n+\t * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,\n+\t * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.\n+\t */\n+\tuint32_t e_tokens;\n+\tuint64_t timestamp;\n+} __rte_packed;\n+\n+#define ASO_DSEG_VALID_OFFSET 31\n+#define ASO_DSEG_BO_OFFSET 30\n+#define ASO_DSEG_SC_OFFSET 28\n+#define ASO_DSEG_CBS_EXP_OFFSET 24\n+#define ASO_DSEG_CBS_MAN_OFFSET 16\n+#define ASO_DSEG_CIR_EXP_MASK 0x1F\n+#define ASO_DSEG_CIR_EXP_OFFSET 8\n+#define ASO_DSEG_EBS_EXP_OFFSET 24\n+#define ASO_DSEG_EBS_MAN_OFFSET 16\n+#define ASO_DSEG_EXP_MASK 0x1F\n+#define ASO_DSEG_MAN_MASK 0xFF\n+\n #define MLX5_ASO_WQE_DSEG_SIZE\t0x40\n+#define MLX5_ASO_METERS_PER_WQE 2\n+#define MLX5_ASO_MTRS_PER_POOL 128\n \n-/* ASO WQE Data segment. */\n+/* ASO WQE data segment. */\n struct mlx5_aso_dseg {\n-\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n+\tunion {\n+\t\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n+\t\tstruct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];\n+\t};\n } __rte_packed;\n \n /* ASO WQE. */\n",
    "prefixes": [
        "v5",
        "06/14"
    ]
}