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GET /api/patches/91579/?format=api
{ "id": 91579, "url": "https://patches.dpdk.org/api/patches/91579/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210415151135.2098674-2-lizh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210415151135.2098674-2-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210415151135.2098674-2-lizh@nvidia.com", "date": "2021-04-15T15:11:21", "name": "[v5,01/14] net/mlx5: support three level table walk", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "958777191786f9f13114f84af5591bc5e079b875", "submitter": { "id": 1967, "url": "https://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210415151135.2098674-2-lizh@nvidia.com/mbox/", "series": [ { "id": 16417, "url": "https://patches.dpdk.org/api/series/16417/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16417", "date": "2021-04-15T15:11:20", "name": "Add ASO meter support in MLX5 PMD", "version": 5, "mbox": "https://patches.dpdk.org/series/16417/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91579/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91579/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9B30A0C3F;\n\tThu, 15 Apr 2021 17:11:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C12EA1622FB;\n\tThu, 15 Apr 2021 17:11:52 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 2A7981622FA\n for <dev@dpdk.org>; Thu, 15 Apr 2021 17:11:51 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 15 Apr 2021 18:11:45 +0300", "from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13FFBjPG032677;\n Thu, 15 Apr 2021 18:11:45 +0300" ], "From": "Li Zhang <lizh@nvidia.com>", "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com, shahafs@nvidia.com", "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com,\n Suanming Mou <suanmingm@nvidia.com>", "Date": "Thu, 15 Apr 2021 18:11:21 +0300", "Message-Id": "<20210415151135.2098674-2-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20210415151135.2098674-1-lizh@nvidia.com>", "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <20210415151135.2098674-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 01/14] net/mlx5: support three level table walk", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nThis commit adds table entry walk for the three level table.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.h | 90 +++++++++++++++++++++++++++++++++++\n 1 file changed, 90 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 5088c95e86..289941cebc 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -834,6 +834,91 @@ int32_t mlx5_l3t_clear_entry(struct mlx5_l3t_tbl *tbl, uint32_t idx);\n int32_t mlx5_l3t_set_entry(struct mlx5_l3t_tbl *tbl, uint32_t idx,\n \t\t\t union mlx5_l3t_data *data);\n \n+static inline void *\n+mlx5_l3t_get_next(struct mlx5_l3t_tbl *tbl, uint32_t *pos)\n+{\n+\tstruct mlx5_l3t_level_tbl *g_tbl, *m_tbl;\n+\tuint32_t i, j, k, g_start, m_start, e_start;\n+\tuint32_t idx = *pos;\n+\tvoid *e_tbl;\n+\tstruct mlx5_l3t_entry_word *w_e_tbl;\n+\tstruct mlx5_l3t_entry_dword *dw_e_tbl;\n+\tstruct mlx5_l3t_entry_qword *qw_e_tbl;\n+\tstruct mlx5_l3t_entry_ptr *ptr_e_tbl;\n+\n+\tif (!tbl)\n+\t\treturn NULL;\n+\tg_tbl = tbl->tbl;\n+\tif (!g_tbl)\n+\t\treturn NULL;\n+\tg_start = (idx >> MLX5_L3T_GT_OFFSET) & MLX5_L3T_GT_MASK;\n+\tm_start = (idx >> MLX5_L3T_MT_OFFSET) & MLX5_L3T_MT_MASK;\n+\te_start = idx & MLX5_L3T_ET_MASK;\n+\tfor (i = g_start; i < MLX5_L3T_GT_SIZE; i++) {\n+\t\tm_tbl = g_tbl->tbl[i];\n+\t\tif (!m_tbl) {\n+\t\t\t/* Jump to new table, reset the sub table start. */\n+\t\t\tm_start = 0;\n+\t\t\te_start = 0;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tfor (j = m_start; j < MLX5_L3T_MT_SIZE; j++) {\n+\t\t\tif (!m_tbl->tbl[j]) {\n+\t\t\t\t/*\n+\t\t\t\t * Jump to new table, reset the sub table\n+\t\t\t\t * start.\n+\t\t\t\t */\n+\t\t\t\te_start = 0;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\te_tbl = m_tbl->tbl[j];\n+\t\t\tswitch (tbl->type) {\n+\t\t\tcase MLX5_L3T_TYPE_WORD:\n+\t\t\t\tw_e_tbl = (struct mlx5_l3t_entry_word *)e_tbl;\n+\t\t\t\tfor (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {\n+\t\t\t\t\tif (!w_e_tbl->entry[k].data)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t*pos = (i << MLX5_L3T_GT_OFFSET) |\n+\t\t\t\t\t (j << MLX5_L3T_MT_OFFSET) | k;\n+\t\t\t\t\treturn (void *)&w_e_tbl->entry[k].data;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tcase MLX5_L3T_TYPE_DWORD:\n+\t\t\t\tdw_e_tbl = (struct mlx5_l3t_entry_dword *)e_tbl;\n+\t\t\t\tfor (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {\n+\t\t\t\t\tif (!dw_e_tbl->entry[k].data)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t*pos = (i << MLX5_L3T_GT_OFFSET) |\n+\t\t\t\t\t (j << MLX5_L3T_MT_OFFSET) | k;\n+\t\t\t\t\treturn (void *)&dw_e_tbl->entry[k].data;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tcase MLX5_L3T_TYPE_QWORD:\n+\t\t\t\tqw_e_tbl = (struct mlx5_l3t_entry_qword *)e_tbl;\n+\t\t\t\tfor (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {\n+\t\t\t\t\tif (!qw_e_tbl->entry[k].data)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t*pos = (i << MLX5_L3T_GT_OFFSET) |\n+\t\t\t\t\t (j << MLX5_L3T_MT_OFFSET) | k;\n+\t\t\t\t\treturn (void *)&qw_e_tbl->entry[k].data;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tptr_e_tbl = (struct mlx5_l3t_entry_ptr *)e_tbl;\n+\t\t\t\tfor (k = e_start; k < MLX5_L3T_ET_SIZE; k++) {\n+\t\t\t\t\tif (!ptr_e_tbl->entry[k].data)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t*pos = (i << MLX5_L3T_GT_OFFSET) |\n+\t\t\t\t\t (j << MLX5_L3T_MT_OFFSET) | k;\n+\t\t\t\t\treturn ptr_e_tbl->entry[k].data;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n /*\n * Macros for linked list based on indexed memory.\n * Example data structure:\n@@ -909,4 +994,9 @@ struct {\t\t\t\t\t\t\t\t\\\n \t idx = (elem)->field.next, (elem) =\t\t\t\t\\\n \t (idx) ? mlx5_ipool_get(pool, idx) : NULL)\n \n+#define MLX5_L3T_FOREACH(tbl, idx, entry)\t\t\t\t\\\n+\tfor (idx = 0, (entry) = mlx5_l3t_get_next((tbl), &idx);\t\t\\\n+\t (entry);\t\t\t\t\t\t\t\\\n+\t idx++, (entry) = mlx5_l3t_get_next((tbl), &idx))\n+\n #endif /* RTE_PMD_MLX5_UTILS_H_ */\n", "prefixes": [ "v5", "01/14" ] }