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Update a patch.

GET /api/patches/91508/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 91508,
    "url": "https://patches.dpdk.org/api/patches/91508/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-25-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1618451359-20693-25-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-25-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2021-04-15T01:49:16",
    "name": "[v4,24/27] event/dlb2: update xstats for v2.5",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c087bd7bc1254115bb97a91a20532686180168c1",
    "submitter": {
        "id": 826,
        "url": "https://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-25-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 16383,
            "url": "https://patches.dpdk.org/api/series/16383/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383",
            "date": "2021-04-15T01:48:52",
            "name": "Add DLB v2.5",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/16383/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/91508/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/91508/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9B88A0562;\n\tThu, 15 Apr 2021 03:53:36 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B5453161EC1;\n\tThu, 15 Apr 2021 03:51:08 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id A17F4161E56\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:48 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:46 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:45 -0700"
        ],
        "IronPort-SDR": [
            "\n +MkRgG8xwTuYjm47ARHeKg0F3/HcLUVAPeWtQqAnwP/7p54q/xHgUeP3YMyuM1arfM8GHZaJKv\n /QZZIImlDjNw==",
            "\n OlJx0Zbwc85u+E6pWc9ZNf7aDQuwdQLWe5lU1Bakt0bKmIhhotuZO0HbOeTLeKffHs1a/uVRJB\n C0azxVVAa4Lg=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9954\"; a=\"194881863\"",
            "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"194881863\"",
            "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569915\""
        ],
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net",
        "Date": "Wed, 14 Apr 2021 20:49:16 -0500",
        "Message-Id": "<1618451359-20693-25-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4 24/27] event/dlb2: update xstats for v2.5",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add DLB v2.5 specific information to xstats, such as metrics for the new\ncredit scheme.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2_xstats.c | 41 ++++++++++++++++++++++++++++----\n 1 file changed, 37 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/event/dlb2/dlb2_xstats.c b/drivers/event/dlb2/dlb2_xstats.c\nindex b62e62060..d4c8d9903 100644\n--- a/drivers/event/dlb2/dlb2_xstats.c\n+++ b/drivers/event/dlb2/dlb2_xstats.c\n@@ -9,6 +9,7 @@\n \n #include \"dlb2_priv.h\"\n #include \"dlb2_inline_fns.h\"\n+#include \"pf/base/dlb2_regs.h\"\n \n enum dlb2_xstats_type {\n \t/* common to device and port */\n@@ -21,6 +22,7 @@ enum dlb2_xstats_type {\n \tzero_polls,\t\t\t/**< Call dequeue burst and return 0 */\n \ttx_nospc_ldb_hw_credits,\t/**< Insufficient LDB h/w credits */\n \ttx_nospc_dir_hw_credits,\t/**< Insufficient DIR h/w credits */\n+\ttx_nospc_hw_credits,\t\t/**< Insufficient h/w credits */\n \ttx_nospc_inflight_max,\t\t/**< Reach the new_event_threshold */\n \ttx_nospc_new_event_limit,\t/**< Insufficient s/w credits */\n \ttx_nospc_inflight_credits,\t/**< Port has too few s/w credits */\n@@ -29,6 +31,7 @@ enum dlb2_xstats_type {\n \tinflight_events,\n \tldb_pool_size,\n \tdir_pool_size,\n+\tpool_size,\n \t/* port specific */\n \ttx_new,\t\t\t\t/**< Send an OP_NEW event */\n \ttx_fwd,\t\t\t\t/**< Send an OP_FORWARD event */\n@@ -129,6 +132,9 @@ dlb2_device_traffic_stat_get(struct dlb2_eventdev *dlb2,\n \t\tcase tx_nospc_dir_hw_credits:\n \t\t\tval += port->stats.traffic.tx_nospc_dir_hw_credits;\n \t\t\tbreak;\n+\t\tcase tx_nospc_hw_credits:\n+\t\t\tval += port->stats.traffic.tx_nospc_hw_credits;\n+\t\t\tbreak;\n \t\tcase tx_nospc_inflight_max:\n \t\t\tval += port->stats.traffic.tx_nospc_inflight_max;\n \t\t\tbreak;\n@@ -159,6 +165,7 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,\n \tcase zero_polls:\n \tcase tx_nospc_ldb_hw_credits:\n \tcase tx_nospc_dir_hw_credits:\n+\tcase tx_nospc_hw_credits:\n \tcase tx_nospc_inflight_max:\n \tcase tx_nospc_new_event_limit:\n \tcase tx_nospc_inflight_credits:\n@@ -171,6 +178,8 @@ get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,\n \t\treturn dlb2->num_ldb_credits;\n \tcase dir_pool_size:\n \t\treturn dlb2->num_dir_credits;\n+\tcase pool_size:\n+\t\treturn dlb2->num_credits;\n \tdefault: return -1;\n \t}\n }\n@@ -203,6 +212,9 @@ get_port_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx,\n \tcase tx_nospc_dir_hw_credits:\n \t\treturn ev_port->stats.traffic.tx_nospc_dir_hw_credits;\n \n+\tcase tx_nospc_hw_credits:\n+\t\treturn ev_port->stats.traffic.tx_nospc_hw_credits;\n+\n \tcase tx_nospc_inflight_max:\n \t\treturn ev_port->stats.traffic.tx_nospc_inflight_max;\n \n@@ -357,6 +369,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t\"zero_polls\",\n \t\t\"tx_nospc_ldb_hw_credits\",\n \t\t\"tx_nospc_dir_hw_credits\",\n+\t\t\"tx_nospc_hw_credits\",\n \t\t\"tx_nospc_inflight_max\",\n \t\t\"tx_nospc_new_event_limit\",\n \t\t\"tx_nospc_inflight_credits\",\n@@ -364,6 +377,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t\"inflight_events\",\n \t\t\"ldb_pool_size\",\n \t\t\"dir_pool_size\",\n+\t\t\"pool_size\",\n \t};\n \tstatic const enum dlb2_xstats_type dev_types[] = {\n \t\trx_ok,\n@@ -375,6 +389,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\tzero_polls,\n \t\ttx_nospc_ldb_hw_credits,\n \t\ttx_nospc_dir_hw_credits,\n+\t\ttx_nospc_hw_credits,\n \t\ttx_nospc_inflight_max,\n \t\ttx_nospc_new_event_limit,\n \t\ttx_nospc_inflight_credits,\n@@ -382,6 +397,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\tinflight_events,\n \t\tldb_pool_size,\n \t\tdir_pool_size,\n+\t\tpool_size,\n \t};\n \t/* Note: generated device stats are not allowed to be reset. */\n \tstatic const uint8_t dev_reset_allowed[] = {\n@@ -394,6 +410,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t0, /* zero_polls */\n \t\t0, /* tx_nospc_ldb_hw_credits */\n \t\t0, /* tx_nospc_dir_hw_credits */\n+\t\t0, /* tx_nospc_hw_credits */\n \t\t0, /* tx_nospc_inflight_max */\n \t\t0, /* tx_nospc_new_event_limit */\n \t\t0, /* tx_nospc_inflight_credits */\n@@ -401,6 +418,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t0, /* inflight_events */\n \t\t0, /* ldb_pool_size */\n \t\t0, /* dir_pool_size */\n+\t\t0, /* pool_size */\n \t};\n \tstatic const char * const port_stats[] = {\n \t\t\"is_configured\",\n@@ -415,6 +433,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t\"zero_polls\",\n \t\t\"tx_nospc_ldb_hw_credits\",\n \t\t\"tx_nospc_dir_hw_credits\",\n+\t\t\"tx_nospc_hw_credits\",\n \t\t\"tx_nospc_inflight_max\",\n \t\t\"tx_nospc_new_event_limit\",\n \t\t\"tx_nospc_inflight_credits\",\n@@ -448,6 +467,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\tzero_polls,\n \t\ttx_nospc_ldb_hw_credits,\n \t\ttx_nospc_dir_hw_credits,\n+\t\ttx_nospc_hw_credits,\n \t\ttx_nospc_inflight_max,\n \t\ttx_nospc_new_event_limit,\n \t\ttx_nospc_inflight_credits,\n@@ -481,6 +501,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t\t1, /* zero_polls */\n \t\t1, /* tx_nospc_ldb_hw_credits */\n \t\t1, /* tx_nospc_dir_hw_credits */\n+\t\t1, /* tx_nospc_hw_credits */\n \t\t1, /* tx_nospc_inflight_max */\n \t\t1, /* tx_nospc_new_event_limit */\n \t\t1, /* tx_nospc_inflight_credits */\n@@ -935,8 +956,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_PORT:\n \t\tif (queue_port_id == -1) {\n-\t\t\tfor (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version);\n-\t\t\t\t\ti++) {\n+\t\t\tfor (i = 0;\n+\t\t\t     i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {\n \t\t\t\tif (dlb2_xstats_reset_port(dlb2, i,\n \t\t\t\t\t\t\t   ids, nb_ids))\n \t\t\t\t\treturn -EINVAL;\n@@ -949,8 +970,8 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n \t\tif (queue_port_id == -1) {\n-\t\t\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES(dlb2->version);\n-\t\t\t\t\ti++) {\n+\t\t\tfor (i = 0;\n+\t\t\t     i < DLB2_MAX_NUM_QUEUES(dlb2->version); i++) {\n \t\t\t\tif (dlb2_xstats_reset_queue(dlb2, i,\n \t\t\t\t\t\t\t    ids, nb_ids))\n \t\t\t\t\treturn -EINVAL;\n@@ -1048,6 +1069,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)\n \tfprintf(f, \"\\tnum_dir_credits = %u\\n\",\n \t\tdlb2->hw_rsrc_query_results.num_dir_credits);\n \n+\tfprintf(f, \"\\tnum_credits = %u\\n\",\n+\t\tdlb2->hw_rsrc_query_results.num_credits);\n+\n \t/* Port level information */\n \n \tfor (i = 0; i < dlb2->num_ports; i++) {\n@@ -1102,6 +1126,12 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)\n \t\tfprintf(f, \"\\tdir_credits = %u\\n\",\n \t\t\tp->qm_port.dir_credits);\n \n+\t\tfprintf(f, \"\\tcached_credits = %u\\n\",\n+\t\t\tp->qm_port.cached_credits);\n+\n+\t\tfprintf(f, \"\\tdir_credits = %u\\n\",\n+\t\t\tp->qm_port.credits);\n+\n \t\tfprintf(f, \"\\tgenbit=%d, cq_idx=%d, cq_depth=%d\\n\",\n \t\t\tp->qm_port.gen_bit,\n \t\t\tp->qm_port.cq_idx,\n@@ -1139,6 +1169,9 @@ dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)\n \t\tfprintf(f, \"\\t\\ttx_nospc_dir_hw_credits %\" PRIu64 \"\\n\",\n \t\t\tp->stats.traffic.tx_nospc_dir_hw_credits);\n \n+\t\tfprintf(f, \"\\t\\ttx_nospc_hw_credits %\" PRIu64 \"\\n\",\n+\t\t\tp->stats.traffic.tx_nospc_hw_credits);\n+\n \t\tfprintf(f, \"\\t\\ttx_nospc_inflight_max %\" PRIu64 \"\\n\",\n \t\t\tp->stats.traffic.tx_nospc_inflight_max);\n \n",
    "prefixes": [
        "v4",
        "24/27"
    ]
}