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{
    "id": 91507,
    "url": "https://patches.dpdk.org/api/patches/91507/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-24-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1618451359-20693-24-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-24-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2021-04-15T01:49:15",
    "name": "[v4,23/27] event/dlb2: use new combined register map",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8a6441c47ec6edf5678a0e4e3dda36a7afa09f05",
    "submitter": {
        "id": 826,
        "url": "https://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-24-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 16383,
            "url": "https://patches.dpdk.org/api/series/16383/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383",
            "date": "2021-04-15T01:48:52",
            "name": "Add DLB v2.5",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/16383/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/91507/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/91507/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 46035A0562;\n\tThu, 15 Apr 2021 03:53:27 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6F3E8161EBF;\n\tThu, 15 Apr 2021 03:51:07 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 81AAF161E4E\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:47 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:46 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:44 -0700"
        ],
        "IronPort-SDR": [
            "\n Up7EdJ4LBd+UgeZeeSDE1Vfvvh5DP2KsbUjWHrvhFI3bxGPd1FaGpKLdkWGm8X90/rFlY+kTJI\n Yd2m3ToDZ6wA==",
            "\n GhoKUn0vFOOFEffsZWEejt+WcbzbCDQZ7QqC+Hq1RtWT7Ls5Z1hxCwl2Uxw6VMRwygss2/B7De\n /nNHjCJAddrQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9954\"; a=\"194881862\"",
            "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"194881862\"",
            "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569909\""
        ],
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net",
        "Date": "Wed, 14 Apr 2021 20:49:15 -0500",
        "Message-Id": "<1618451359-20693-24-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4 23/27] event/dlb2: use new combined register\n map",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "All references to the old register map have been removed,\nso it is safe to rename the new combined file that supports\nboth DLB v2.0 and DLB v2.5. Also fixed all places where this\nfile is included.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_hw_types.h |    2 +-\n drivers/event/dlb2/pf/base/dlb2_regs.h     | 5955 +++++++++++++-------\n drivers/event/dlb2/pf/base/dlb2_regs_new.h | 4304 --------------\n drivers/event/dlb2/pf/base/dlb2_resource.c |    2 +-\n drivers/event/dlb2/pf/dlb2_main.c          |    2 +-\n 5 files changed, 3869 insertions(+), 6396 deletions(-)\n delete mode 100644 drivers/event/dlb2/pf/base/dlb2_regs_new.h",
    "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nindex 4a6037775..6b8fee341 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -10,7 +10,7 @@\n \n #include \"dlb2_osdep_list.h\"\n #include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs_new.h\"\n+#include \"dlb2_regs.h\"\n \n #define DLB2_BITS_SET(x, val, mask)\t(x = ((x) & ~(mask))     \\\n \t\t\t\t | (((val) << (mask##_LOC)) & (mask)))\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_regs.h b/drivers/event/dlb2/pf/base/dlb2_regs.h\nindex 43ecad4f8..7167f3d2f 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_regs.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_regs.h\n@@ -7,553 +7,550 @@\n \n #include \"dlb2_osdep_types.h\"\n \n-#define DLB2_FUNC_PF_VF2PF_MAILBOX_BYTES 256\n-#define DLB2_FUNC_PF_VF2PF_MAILBOX(vf_id, x) \\\n+#define DLB2_PF_VF2PF_MAILBOX_BYTES 256\n+#define DLB2_PF_VF2PF_MAILBOX(vf_id, x) \\\n \t(0x1000 + 0x4 * (x) + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_VF2PF_MAILBOX_RST 0x0\n-union dlb2_func_pf_vf2pf_mailbox {\n-\tstruct {\n-\t\tu32 msg : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR(vf_id) \\\n+#define DLB2_PF_VF2PF_MAILBOX_RST 0x0\n+\n+#define DLB2_PF_VF2PF_MAILBOX_MSG\t0xFFFFFFFF\n+#define DLB2_PF_VF2PF_MAILBOX_MSG_LOC\t0\n+\n+#define DLB2_PF_VF2PF_MAILBOX_ISR(vf_id) \\\n \t(0x1f00 + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR_RST 0x0\n-union dlb2_func_pf_vf2pf_mailbox_isr {\n-\tstruct {\n-\t\tu32 vf0_isr : 1;\n-\t\tu32 vf1_isr : 1;\n-\t\tu32 vf2_isr : 1;\n-\t\tu32 vf3_isr : 1;\n-\t\tu32 vf4_isr : 1;\n-\t\tu32 vf5_isr : 1;\n-\t\tu32 vf6_isr : 1;\n-\t\tu32 vf7_isr : 1;\n-\t\tu32 vf8_isr : 1;\n-\t\tu32 vf9_isr : 1;\n-\t\tu32 vf10_isr : 1;\n-\t\tu32 vf11_isr : 1;\n-\t\tu32 vf12_isr : 1;\n-\t\tu32 vf13_isr : 1;\n-\t\tu32 vf14_isr : 1;\n-\t\tu32 vf15_isr : 1;\n-\t\tu32 rsvd0 : 16;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_VF2PF_FLR_ISR(vf_id) \\\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_RST 0x0\n+\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF0_ISR\t0x00000001\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF1_ISR\t0x00000002\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF2_ISR\t0x00000004\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF3_ISR\t0x00000008\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF4_ISR\t0x00000010\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF5_ISR\t0x00000020\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF6_ISR\t0x00000040\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF7_ISR\t0x00000080\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF8_ISR\t0x00000100\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF9_ISR\t0x00000200\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF10_ISR\t0x00000400\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF11_ISR\t0x00000800\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF12_ISR\t0x00001000\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF13_ISR\t0x00002000\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF14_ISR\t0x00004000\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF15_ISR\t0x00008000\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_RSVD0\t0xFFFF0000\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF0_ISR_LOC\t0\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF1_ISR_LOC\t1\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF2_ISR_LOC\t2\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF3_ISR_LOC\t3\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF4_ISR_LOC\t4\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF5_ISR_LOC\t5\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF6_ISR_LOC\t6\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF7_ISR_LOC\t7\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF8_ISR_LOC\t8\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF9_ISR_LOC\t9\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF10_ISR_LOC\t10\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF11_ISR_LOC\t11\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF12_ISR_LOC\t12\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF13_ISR_LOC\t13\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF14_ISR_LOC\t14\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_VF15_ISR_LOC\t15\n+#define DLB2_PF_VF2PF_MAILBOX_ISR_RSVD0_LOC\t\t16\n+\n+#define DLB2_PF_VF2PF_FLR_ISR(vf_id) \\\n \t(0x1f04 + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_VF2PF_FLR_ISR_RST 0x0\n-union dlb2_func_pf_vf2pf_flr_isr {\n-\tstruct {\n-\t\tu32 vf0_isr : 1;\n-\t\tu32 vf1_isr : 1;\n-\t\tu32 vf2_isr : 1;\n-\t\tu32 vf3_isr : 1;\n-\t\tu32 vf4_isr : 1;\n-\t\tu32 vf5_isr : 1;\n-\t\tu32 vf6_isr : 1;\n-\t\tu32 vf7_isr : 1;\n-\t\tu32 vf8_isr : 1;\n-\t\tu32 vf9_isr : 1;\n-\t\tu32 vf10_isr : 1;\n-\t\tu32 vf11_isr : 1;\n-\t\tu32 vf12_isr : 1;\n-\t\tu32 vf13_isr : 1;\n-\t\tu32 vf14_isr : 1;\n-\t\tu32 vf15_isr : 1;\n-\t\tu32 rsvd0 : 16;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_VF2PF_ISR_PEND(vf_id) \\\n+#define DLB2_PF_VF2PF_FLR_ISR_RST 0x0\n+\n+#define DLB2_PF_VF2PF_FLR_ISR_VF0_ISR\t0x00000001\n+#define DLB2_PF_VF2PF_FLR_ISR_VF1_ISR\t0x00000002\n+#define DLB2_PF_VF2PF_FLR_ISR_VF2_ISR\t0x00000004\n+#define DLB2_PF_VF2PF_FLR_ISR_VF3_ISR\t0x00000008\n+#define DLB2_PF_VF2PF_FLR_ISR_VF4_ISR\t0x00000010\n+#define DLB2_PF_VF2PF_FLR_ISR_VF5_ISR\t0x00000020\n+#define DLB2_PF_VF2PF_FLR_ISR_VF6_ISR\t0x00000040\n+#define DLB2_PF_VF2PF_FLR_ISR_VF7_ISR\t0x00000080\n+#define DLB2_PF_VF2PF_FLR_ISR_VF8_ISR\t0x00000100\n+#define DLB2_PF_VF2PF_FLR_ISR_VF9_ISR\t0x00000200\n+#define DLB2_PF_VF2PF_FLR_ISR_VF10_ISR\t0x00000400\n+#define DLB2_PF_VF2PF_FLR_ISR_VF11_ISR\t0x00000800\n+#define DLB2_PF_VF2PF_FLR_ISR_VF12_ISR\t0x00001000\n+#define DLB2_PF_VF2PF_FLR_ISR_VF13_ISR\t0x00002000\n+#define DLB2_PF_VF2PF_FLR_ISR_VF14_ISR\t0x00004000\n+#define DLB2_PF_VF2PF_FLR_ISR_VF15_ISR\t0x00008000\n+#define DLB2_PF_VF2PF_FLR_ISR_RSVD0\t\t0xFFFF0000\n+#define DLB2_PF_VF2PF_FLR_ISR_VF0_ISR_LOC\t0\n+#define DLB2_PF_VF2PF_FLR_ISR_VF1_ISR_LOC\t1\n+#define DLB2_PF_VF2PF_FLR_ISR_VF2_ISR_LOC\t2\n+#define DLB2_PF_VF2PF_FLR_ISR_VF3_ISR_LOC\t3\n+#define DLB2_PF_VF2PF_FLR_ISR_VF4_ISR_LOC\t4\n+#define DLB2_PF_VF2PF_FLR_ISR_VF5_ISR_LOC\t5\n+#define DLB2_PF_VF2PF_FLR_ISR_VF6_ISR_LOC\t6\n+#define DLB2_PF_VF2PF_FLR_ISR_VF7_ISR_LOC\t7\n+#define DLB2_PF_VF2PF_FLR_ISR_VF8_ISR_LOC\t8\n+#define DLB2_PF_VF2PF_FLR_ISR_VF9_ISR_LOC\t9\n+#define DLB2_PF_VF2PF_FLR_ISR_VF10_ISR_LOC\t10\n+#define DLB2_PF_VF2PF_FLR_ISR_VF11_ISR_LOC\t11\n+#define DLB2_PF_VF2PF_FLR_ISR_VF12_ISR_LOC\t12\n+#define DLB2_PF_VF2PF_FLR_ISR_VF13_ISR_LOC\t13\n+#define DLB2_PF_VF2PF_FLR_ISR_VF14_ISR_LOC\t14\n+#define DLB2_PF_VF2PF_FLR_ISR_VF15_ISR_LOC\t15\n+#define DLB2_PF_VF2PF_FLR_ISR_RSVD0_LOC\t16\n+\n+#define DLB2_PF_VF2PF_ISR_PEND(vf_id) \\\n \t(0x1f10 + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_VF2PF_ISR_PEND_RST 0x0\n-union dlb2_func_pf_vf2pf_isr_pend {\n-\tstruct {\n-\t\tu32 isr_pend : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_PF2VF_MAILBOX_BYTES 64\n-#define DLB2_FUNC_PF_PF2VF_MAILBOX(vf_id, x) \\\n+#define DLB2_PF_VF2PF_ISR_PEND_RST 0x0\n+\n+#define DLB2_PF_VF2PF_ISR_PEND_ISR_PEND\t0x00000001\n+#define DLB2_PF_VF2PF_ISR_PEND_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_PF_VF2PF_ISR_PEND_ISR_PEND_LOC\t0\n+#define DLB2_PF_VF2PF_ISR_PEND_RSVD0_LOC\t1\n+\n+#define DLB2_PF_PF2VF_MAILBOX_BYTES 64\n+#define DLB2_PF_PF2VF_MAILBOX(vf_id, x) \\\n \t(0x2000 + 0x4 * (x) + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_PF2VF_MAILBOX_RST 0x0\n-union dlb2_func_pf_pf2vf_mailbox {\n-\tstruct {\n-\t\tu32 msg : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR(vf_id) \\\n+#define DLB2_PF_PF2VF_MAILBOX_RST 0x0\n+\n+#define DLB2_PF_PF2VF_MAILBOX_MSG\t0xFFFFFFFF\n+#define DLB2_PF_PF2VF_MAILBOX_MSG_LOC\t0\n+\n+#define DLB2_PF_PF2VF_MAILBOX_ISR(vf_id) \\\n \t(0x2f00 + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR_RST 0x0\n-union dlb2_func_pf_pf2vf_mailbox_isr {\n-\tstruct {\n-\t\tu32 vf0_isr : 1;\n-\t\tu32 vf1_isr : 1;\n-\t\tu32 vf2_isr : 1;\n-\t\tu32 vf3_isr : 1;\n-\t\tu32 vf4_isr : 1;\n-\t\tu32 vf5_isr : 1;\n-\t\tu32 vf6_isr : 1;\n-\t\tu32 vf7_isr : 1;\n-\t\tu32 vf8_isr : 1;\n-\t\tu32 vf9_isr : 1;\n-\t\tu32 vf10_isr : 1;\n-\t\tu32 vf11_isr : 1;\n-\t\tu32 vf12_isr : 1;\n-\t\tu32 vf13_isr : 1;\n-\t\tu32 vf14_isr : 1;\n-\t\tu32 vf15_isr : 1;\n-\t\tu32 rsvd0 : 16;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS(vf_id) \\\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_RST 0x0\n+\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF0_ISR\t0x00000001\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF1_ISR\t0x00000002\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF2_ISR\t0x00000004\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF3_ISR\t0x00000008\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF4_ISR\t0x00000010\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF5_ISR\t0x00000020\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF6_ISR\t0x00000040\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF7_ISR\t0x00000080\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF8_ISR\t0x00000100\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF9_ISR\t0x00000200\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF10_ISR\t0x00000400\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF11_ISR\t0x00000800\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF12_ISR\t0x00001000\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF13_ISR\t0x00002000\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF14_ISR\t0x00004000\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF15_ISR\t0x00008000\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_RSVD0\t0xFFFF0000\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF0_ISR_LOC\t0\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF1_ISR_LOC\t1\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF2_ISR_LOC\t2\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF3_ISR_LOC\t3\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF4_ISR_LOC\t4\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF5_ISR_LOC\t5\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF6_ISR_LOC\t6\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF7_ISR_LOC\t7\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF8_ISR_LOC\t8\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF9_ISR_LOC\t9\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF10_ISR_LOC\t10\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF11_ISR_LOC\t11\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF12_ISR_LOC\t12\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF13_ISR_LOC\t13\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF14_ISR_LOC\t14\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_VF15_ISR_LOC\t15\n+#define DLB2_PF_PF2VF_MAILBOX_ISR_RSVD0_LOC\t\t16\n+\n+#define DLB2_PF_VF_RESET_IN_PROGRESS(vf_id) \\\n \t(0x3000 + (vf_id) * 0x10000)\n-#define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS_RST 0xffff\n-union dlb2_func_pf_vf_reset_in_progress {\n-\tstruct {\n-\t\tu32 vf0_reset_in_progress : 1;\n-\t\tu32 vf1_reset_in_progress : 1;\n-\t\tu32 vf2_reset_in_progress : 1;\n-\t\tu32 vf3_reset_in_progress : 1;\n-\t\tu32 vf4_reset_in_progress : 1;\n-\t\tu32 vf5_reset_in_progress : 1;\n-\t\tu32 vf6_reset_in_progress : 1;\n-\t\tu32 vf7_reset_in_progress : 1;\n-\t\tu32 vf8_reset_in_progress : 1;\n-\t\tu32 vf9_reset_in_progress : 1;\n-\t\tu32 vf10_reset_in_progress : 1;\n-\t\tu32 vf11_reset_in_progress : 1;\n-\t\tu32 vf12_reset_in_progress : 1;\n-\t\tu32 vf13_reset_in_progress : 1;\n-\t\tu32 vf14_reset_in_progress : 1;\n-\t\tu32 vf15_reset_in_progress : 1;\n-\t\tu32 rsvd0 : 16;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_MSIX_MEM_VECTOR_CTRL(x) \\\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_RST 0xffff\n+\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF0_RESET_IN_PROGRESS\t0x00000001\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF1_RESET_IN_PROGRESS\t0x00000002\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF2_RESET_IN_PROGRESS\t0x00000004\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF3_RESET_IN_PROGRESS\t0x00000008\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF4_RESET_IN_PROGRESS\t0x00000010\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF5_RESET_IN_PROGRESS\t0x00000020\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF6_RESET_IN_PROGRESS\t0x00000040\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF7_RESET_IN_PROGRESS\t0x00000080\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF8_RESET_IN_PROGRESS\t0x00000100\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF9_RESET_IN_PROGRESS\t0x00000200\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF10_RESET_IN_PROGRESS\t0x00000400\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF11_RESET_IN_PROGRESS\t0x00000800\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF12_RESET_IN_PROGRESS\t0x00001000\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF13_RESET_IN_PROGRESS\t0x00002000\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF14_RESET_IN_PROGRESS\t0x00004000\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF15_RESET_IN_PROGRESS\t0x00008000\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_RSVD0\t\t\t0xFFFF0000\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF0_RESET_IN_PROGRESS_LOC\t0\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF1_RESET_IN_PROGRESS_LOC\t1\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF2_RESET_IN_PROGRESS_LOC\t2\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF3_RESET_IN_PROGRESS_LOC\t3\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF4_RESET_IN_PROGRESS_LOC\t4\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF5_RESET_IN_PROGRESS_LOC\t5\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF6_RESET_IN_PROGRESS_LOC\t6\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF7_RESET_IN_PROGRESS_LOC\t7\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF8_RESET_IN_PROGRESS_LOC\t8\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF9_RESET_IN_PROGRESS_LOC\t9\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF10_RESET_IN_PROGRESS_LOC\t10\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF11_RESET_IN_PROGRESS_LOC\t11\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF12_RESET_IN_PROGRESS_LOC\t12\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF13_RESET_IN_PROGRESS_LOC\t13\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF14_RESET_IN_PROGRESS_LOC\t14\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_VF15_RESET_IN_PROGRESS_LOC\t15\n+#define DLB2_PF_VF_RESET_IN_PROGRESS_RSVD0_LOC\t\t\t16\n+\n+#define DLB2_MSIX_VECTOR_CTRL(x) \\\n \t(0x100000c + (x) * 0x10)\n-#define DLB2_MSIX_MEM_VECTOR_CTRL_RST 0x1\n-union dlb2_msix_mem_vector_ctrl {\n-\tstruct {\n-\t\tu32 vec_mask : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+#define DLB2_MSIX_VECTOR_CTRL_RST 0x1\n+\n+#define DLB2_MSIX_VECTOR_CTRL_VEC_MASK\t0x00000001\n+#define DLB2_MSIX_VECTOR_CTRL_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_MSIX_VECTOR_CTRL_VEC_MASK_LOC\t0\n+#define DLB2_MSIX_VECTOR_CTRL_RSVD0_LOC\t1\n \n #define DLB2_IOSF_FUNC_VF_BAR_DSBL(x) \\\n \t(0x20 + (x) * 0x4)\n #define DLB2_IOSF_FUNC_VF_BAR_DSBL_RST 0x0\n-union dlb2_iosf_func_vf_bar_dsbl {\n-\tstruct {\n-\t\tu32 func_vf_bar_dis : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_TOTAL_VAS 0x1000011c\n+\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL_FUNC_VF_BAR_DIS\t0x00000001\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL_FUNC_VF_BAR_DIS_LOC\t0\n+#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RSVD0_LOC\t\t\t1\n+\n+#define DLB2_V2SYS_TOTAL_VAS 0x1000011c\n+#define DLB2_V2_5SYS_TOTAL_VAS 0x10000114\n+#define DLB2_SYS_TOTAL_VAS(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2SYS_TOTAL_VAS : \\\n+\t DLB2_V2_5SYS_TOTAL_VAS)\n #define DLB2_SYS_TOTAL_VAS_RST 0x20\n-union dlb2_sys_total_vas {\n-\tstruct {\n-\t\tu32 total_vas : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_TOTAL_DIR_PORTS 0x10000118\n-#define DLB2_SYS_TOTAL_DIR_PORTS_RST 0x40\n-union dlb2_sys_total_dir_ports {\n-\tstruct {\n-\t\tu32 total_dir_ports : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_TOTAL_LDB_PORTS 0x10000114\n-#define DLB2_SYS_TOTAL_LDB_PORTS_RST 0x40\n-union dlb2_sys_total_ldb_ports {\n-\tstruct {\n-\t\tu32 total_ldb_ports : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_TOTAL_DIR_QID 0x10000110\n-#define DLB2_SYS_TOTAL_DIR_QID_RST 0x40\n-union dlb2_sys_total_dir_qid {\n-\tstruct {\n-\t\tu32 total_dir_qid : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_TOTAL_LDB_QID 0x1000010c\n-#define DLB2_SYS_TOTAL_LDB_QID_RST 0x20\n-union dlb2_sys_total_ldb_qid {\n-\tstruct {\n-\t\tu32 total_ldb_qid : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_TOTAL_VAS_TOTAL_VAS\t0xFFFFFFFF\n+#define DLB2_SYS_TOTAL_VAS_TOTAL_VAS_LOC\t0\n \n #define DLB2_SYS_TOTAL_DIR_CRDS 0x10000108\n #define DLB2_SYS_TOTAL_DIR_CRDS_RST 0x1000\n-union dlb2_sys_total_dir_crds {\n-\tstruct {\n-\t\tu32 total_dir_credits : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_TOTAL_DIR_CRDS_TOTAL_DIR_CREDITS\t0xFFFFFFFF\n+#define DLB2_SYS_TOTAL_DIR_CRDS_TOTAL_DIR_CREDITS_LOC\t0\n \n #define DLB2_SYS_TOTAL_LDB_CRDS 0x10000104\n #define DLB2_SYS_TOTAL_LDB_CRDS_RST 0x2000\n-union dlb2_sys_total_ldb_crds {\n-\tstruct {\n-\t\tu32 total_ldb_credits : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_TOTAL_LDB_CRDS_TOTAL_LDB_CREDITS\t0xFFFFFFFF\n+#define DLB2_SYS_TOTAL_LDB_CRDS_TOTAL_LDB_CREDITS_LOC\t0\n \n #define DLB2_SYS_ALARM_PF_SYND2 0x10000508\n #define DLB2_SYS_ALARM_PF_SYND2_RST 0x0\n-union dlb2_sys_alarm_pf_synd2 {\n-\tstruct {\n-\t\tu32 lock_id : 16;\n-\t\tu32 meas : 1;\n-\t\tu32 debug : 7;\n-\t\tu32 cq_pop : 1;\n-\t\tu32 qe_uhl : 1;\n-\t\tu32 qe_orsp : 1;\n-\t\tu32 qe_valid : 1;\n-\t\tu32 cq_int_rearm : 1;\n-\t\tu32 dsi_error : 1;\n-\t\tu32 rsvd0 : 2;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_PF_SYND2_LOCK_ID\t0x0000FFFF\n+#define DLB2_SYS_ALARM_PF_SYND2_MEAS\t\t0x00010000\n+#define DLB2_SYS_ALARM_PF_SYND2_DEBUG\t0x00FE0000\n+#define DLB2_SYS_ALARM_PF_SYND2_CQ_POP\t0x01000000\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_UHL\t0x02000000\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_ORSP\t0x04000000\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_VALID\t0x08000000\n+#define DLB2_SYS_ALARM_PF_SYND2_CQ_INT_REARM\t0x10000000\n+#define DLB2_SYS_ALARM_PF_SYND2_DSI_ERROR\t0x20000000\n+#define DLB2_SYS_ALARM_PF_SYND2_RSVD0\t0xC0000000\n+#define DLB2_SYS_ALARM_PF_SYND2_LOCK_ID_LOC\t\t0\n+#define DLB2_SYS_ALARM_PF_SYND2_MEAS_LOC\t\t16\n+#define DLB2_SYS_ALARM_PF_SYND2_DEBUG_LOC\t\t17\n+#define DLB2_SYS_ALARM_PF_SYND2_CQ_POP_LOC\t\t24\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_UHL_LOC\t\t25\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_ORSP_LOC\t\t26\n+#define DLB2_SYS_ALARM_PF_SYND2_QE_VALID_LOC\t\t27\n+#define DLB2_SYS_ALARM_PF_SYND2_CQ_INT_REARM_LOC\t28\n+#define DLB2_SYS_ALARM_PF_SYND2_DSI_ERROR_LOC\t29\n+#define DLB2_SYS_ALARM_PF_SYND2_RSVD0_LOC\t\t30\n \n #define DLB2_SYS_ALARM_PF_SYND1 0x10000504\n #define DLB2_SYS_ALARM_PF_SYND1_RST 0x0\n-union dlb2_sys_alarm_pf_synd1 {\n-\tstruct {\n-\t\tu32 dsi : 16;\n-\t\tu32 qid : 8;\n-\t\tu32 qtype : 2;\n-\t\tu32 qpri : 3;\n-\t\tu32 msg_type : 3;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_PF_SYND1_DSI\t\t0x0000FFFF\n+#define DLB2_SYS_ALARM_PF_SYND1_QID\t\t0x00FF0000\n+#define DLB2_SYS_ALARM_PF_SYND1_QTYPE\t0x03000000\n+#define DLB2_SYS_ALARM_PF_SYND1_QPRI\t\t0x1C000000\n+#define DLB2_SYS_ALARM_PF_SYND1_MSG_TYPE\t0xE0000000\n+#define DLB2_SYS_ALARM_PF_SYND1_DSI_LOC\t0\n+#define DLB2_SYS_ALARM_PF_SYND1_QID_LOC\t16\n+#define DLB2_SYS_ALARM_PF_SYND1_QTYPE_LOC\t24\n+#define DLB2_SYS_ALARM_PF_SYND1_QPRI_LOC\t26\n+#define DLB2_SYS_ALARM_PF_SYND1_MSG_TYPE_LOC\t29\n \n #define DLB2_SYS_ALARM_PF_SYND0 0x10000500\n #define DLB2_SYS_ALARM_PF_SYND0_RST 0x0\n-union dlb2_sys_alarm_pf_synd0 {\n-\tstruct {\n-\t\tu32 syndrome : 8;\n-\t\tu32 rtype : 2;\n-\t\tu32 rsvd0 : 3;\n-\t\tu32 is_ldb : 1;\n-\t\tu32 cls : 2;\n-\t\tu32 aid : 6;\n-\t\tu32 unit : 4;\n-\t\tu32 source : 4;\n-\t\tu32 more : 1;\n-\t\tu32 valid : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_PF_SYND0_SYNDROME\t0x000000FF\n+#define DLB2_SYS_ALARM_PF_SYND0_RTYPE\t0x00000300\n+#define DLB2_SYS_ALARM_PF_SYND0_RSVD0\t0x00001C00\n+#define DLB2_SYS_ALARM_PF_SYND0_IS_LDB\t0x00002000\n+#define DLB2_SYS_ALARM_PF_SYND0_CLS\t\t0x0000C000\n+#define DLB2_SYS_ALARM_PF_SYND0_AID\t\t0x003F0000\n+#define DLB2_SYS_ALARM_PF_SYND0_UNIT\t\t0x03C00000\n+#define DLB2_SYS_ALARM_PF_SYND0_SOURCE\t0x3C000000\n+#define DLB2_SYS_ALARM_PF_SYND0_MORE\t\t0x40000000\n+#define DLB2_SYS_ALARM_PF_SYND0_VALID\t0x80000000\n+#define DLB2_SYS_ALARM_PF_SYND0_SYNDROME_LOC\t0\n+#define DLB2_SYS_ALARM_PF_SYND0_RTYPE_LOC\t8\n+#define DLB2_SYS_ALARM_PF_SYND0_RSVD0_LOC\t10\n+#define DLB2_SYS_ALARM_PF_SYND0_IS_LDB_LOC\t13\n+#define DLB2_SYS_ALARM_PF_SYND0_CLS_LOC\t14\n+#define DLB2_SYS_ALARM_PF_SYND0_AID_LOC\t16\n+#define DLB2_SYS_ALARM_PF_SYND0_UNIT_LOC\t22\n+#define DLB2_SYS_ALARM_PF_SYND0_SOURCE_LOC\t26\n+#define DLB2_SYS_ALARM_PF_SYND0_MORE_LOC\t30\n+#define DLB2_SYS_ALARM_PF_SYND0_VALID_LOC\t31\n \n #define DLB2_SYS_VF_LDB_VPP_V(x) \\\n \t(0x10000f00 + (x) * 0x1000)\n #define DLB2_SYS_VF_LDB_VPP_V_RST 0x0\n-union dlb2_sys_vf_ldb_vpp_v {\n-\tstruct {\n-\t\tu32 vpp_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_LDB_VPP_V_VPP_V\t0x00000001\n+#define DLB2_SYS_VF_LDB_VPP_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_VF_LDB_VPP_V_VPP_V_LOC\t0\n+#define DLB2_SYS_VF_LDB_VPP_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_VF_LDB_VPP2PP(x) \\\n \t(0x10000f04 + (x) * 0x1000)\n #define DLB2_SYS_VF_LDB_VPP2PP_RST 0x0\n-union dlb2_sys_vf_ldb_vpp2pp {\n-\tstruct {\n-\t\tu32 pp : 6;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_LDB_VPP2PP_PP\t0x0000003F\n+#define DLB2_SYS_VF_LDB_VPP2PP_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_VF_LDB_VPP2PP_PP_LOC\t0\n+#define DLB2_SYS_VF_LDB_VPP2PP_RSVD0_LOC\t6\n \n #define DLB2_SYS_VF_DIR_VPP_V(x) \\\n \t(0x10000f08 + (x) * 0x1000)\n #define DLB2_SYS_VF_DIR_VPP_V_RST 0x0\n-union dlb2_sys_vf_dir_vpp_v {\n-\tstruct {\n-\t\tu32 vpp_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_DIR_VPP_V_VPP_V\t0x00000001\n+#define DLB2_SYS_VF_DIR_VPP_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_VF_DIR_VPP_V_VPP_V_LOC\t0\n+#define DLB2_SYS_VF_DIR_VPP_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_VF_DIR_VPP2PP(x) \\\n \t(0x10000f0c + (x) * 0x1000)\n #define DLB2_SYS_VF_DIR_VPP2PP_RST 0x0\n-union dlb2_sys_vf_dir_vpp2pp {\n-\tstruct {\n-\t\tu32 pp : 6;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_DIR_VPP2PP_PP\t0x0000003F\n+#define DLB2_SYS_VF_DIR_VPP2PP_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_VF_DIR_VPP2PP_PP_LOC\t0\n+#define DLB2_SYS_VF_DIR_VPP2PP_RSVD0_LOC\t6\n \n #define DLB2_SYS_VF_LDB_VQID_V(x) \\\n \t(0x10000f10 + (x) * 0x1000)\n #define DLB2_SYS_VF_LDB_VQID_V_RST 0x0\n-union dlb2_sys_vf_ldb_vqid_v {\n-\tstruct {\n-\t\tu32 vqid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_LDB_VQID_V_VQID_V\t0x00000001\n+#define DLB2_SYS_VF_LDB_VQID_V_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_SYS_VF_LDB_VQID_V_VQID_V_LOC\t0\n+#define DLB2_SYS_VF_LDB_VQID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_VF_LDB_VQID2QID(x) \\\n \t(0x10000f14 + (x) * 0x1000)\n #define DLB2_SYS_VF_LDB_VQID2QID_RST 0x0\n-union dlb2_sys_vf_ldb_vqid2qid {\n-\tstruct {\n-\t\tu32 qid : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_LDB_VQID2QID_QID\t\t0x0000001F\n+#define DLB2_SYS_VF_LDB_VQID2QID_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_VF_LDB_VQID2QID_QID_LOC\t0\n+#define DLB2_SYS_VF_LDB_VQID2QID_RSVD0_LOC\t5\n \n #define DLB2_SYS_LDB_QID2VQID(x) \\\n \t(0x10000f18 + (x) * 0x1000)\n #define DLB2_SYS_LDB_QID2VQID_RST 0x0\n-union dlb2_sys_ldb_qid2vqid {\n-\tstruct {\n-\t\tu32 vqid : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_QID2VQID_VQID\t0x0000001F\n+#define DLB2_SYS_LDB_QID2VQID_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_LDB_QID2VQID_VQID_LOC\t0\n+#define DLB2_SYS_LDB_QID2VQID_RSVD0_LOC\t5\n \n #define DLB2_SYS_VF_DIR_VQID_V(x) \\\n \t(0x10000f1c + (x) * 0x1000)\n #define DLB2_SYS_VF_DIR_VQID_V_RST 0x0\n-union dlb2_sys_vf_dir_vqid_v {\n-\tstruct {\n-\t\tu32 vqid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_DIR_VQID_V_VQID_V\t0x00000001\n+#define DLB2_SYS_VF_DIR_VQID_V_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_SYS_VF_DIR_VQID_V_VQID_V_LOC\t0\n+#define DLB2_SYS_VF_DIR_VQID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_VF_DIR_VQID2QID(x) \\\n \t(0x10000f20 + (x) * 0x1000)\n #define DLB2_SYS_VF_DIR_VQID2QID_RST 0x0\n-union dlb2_sys_vf_dir_vqid2qid {\n-\tstruct {\n-\t\tu32 qid : 6;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_VF_DIR_VQID2QID_QID\t\t0x0000003F\n+#define DLB2_SYS_VF_DIR_VQID2QID_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_VF_DIR_VQID2QID_QID_LOC\t0\n+#define DLB2_SYS_VF_DIR_VQID2QID_RSVD0_LOC\t6\n \n #define DLB2_SYS_LDB_VASQID_V(x) \\\n \t(0x10000f24 + (x) * 0x1000)\n #define DLB2_SYS_LDB_VASQID_V_RST 0x0\n-union dlb2_sys_ldb_vasqid_v {\n-\tstruct {\n-\t\tu32 vasqid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_VASQID_V_VASQID_V\t0x00000001\n+#define DLB2_SYS_LDB_VASQID_V_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_SYS_LDB_VASQID_V_VASQID_V_LOC\t0\n+#define DLB2_SYS_LDB_VASQID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_DIR_VASQID_V(x) \\\n \t(0x10000f28 + (x) * 0x1000)\n #define DLB2_SYS_DIR_VASQID_V_RST 0x0\n-union dlb2_sys_dir_vasqid_v {\n-\tstruct {\n-\t\tu32 vasqid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_VASQID_V_VASQID_V\t0x00000001\n+#define DLB2_SYS_DIR_VASQID_V_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_SYS_DIR_VASQID_V_VASQID_V_LOC\t0\n+#define DLB2_SYS_DIR_VASQID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_ALARM_VF_SYND2(x) \\\n \t(0x10000f48 + (x) * 0x1000)\n #define DLB2_SYS_ALARM_VF_SYND2_RST 0x0\n-union dlb2_sys_alarm_vf_synd2 {\n-\tstruct {\n-\t\tu32 lock_id : 16;\n-\t\tu32 debug : 8;\n-\t\tu32 cq_pop : 1;\n-\t\tu32 qe_uhl : 1;\n-\t\tu32 qe_orsp : 1;\n-\t\tu32 qe_valid : 1;\n-\t\tu32 isz : 1;\n-\t\tu32 dsi_error : 1;\n-\t\tu32 dlbrsvd : 2;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_VF_SYND2_LOCK_ID\t0x0000FFFF\n+#define DLB2_SYS_ALARM_VF_SYND2_DEBUG\t0x00FF0000\n+#define DLB2_SYS_ALARM_VF_SYND2_CQ_POP\t0x01000000\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_UHL\t0x02000000\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_ORSP\t0x04000000\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_VALID\t0x08000000\n+#define DLB2_SYS_ALARM_VF_SYND2_ISZ\t\t0x10000000\n+#define DLB2_SYS_ALARM_VF_SYND2_DSI_ERROR\t0x20000000\n+#define DLB2_SYS_ALARM_VF_SYND2_DLBRSVD\t0xC0000000\n+#define DLB2_SYS_ALARM_VF_SYND2_LOCK_ID_LOC\t\t0\n+#define DLB2_SYS_ALARM_VF_SYND2_DEBUG_LOC\t\t16\n+#define DLB2_SYS_ALARM_VF_SYND2_CQ_POP_LOC\t\t24\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_UHL_LOC\t\t25\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_ORSP_LOC\t\t26\n+#define DLB2_SYS_ALARM_VF_SYND2_QE_VALID_LOC\t\t27\n+#define DLB2_SYS_ALARM_VF_SYND2_ISZ_LOC\t\t28\n+#define DLB2_SYS_ALARM_VF_SYND2_DSI_ERROR_LOC\t29\n+#define DLB2_SYS_ALARM_VF_SYND2_DLBRSVD_LOC\t\t30\n \n #define DLB2_SYS_ALARM_VF_SYND1(x) \\\n \t(0x10000f44 + (x) * 0x1000)\n #define DLB2_SYS_ALARM_VF_SYND1_RST 0x0\n-union dlb2_sys_alarm_vf_synd1 {\n-\tstruct {\n-\t\tu32 dsi : 16;\n-\t\tu32 qid : 8;\n-\t\tu32 qtype : 2;\n-\t\tu32 qpri : 3;\n-\t\tu32 msg_type : 3;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_VF_SYND1_DSI\t\t0x0000FFFF\n+#define DLB2_SYS_ALARM_VF_SYND1_QID\t\t0x00FF0000\n+#define DLB2_SYS_ALARM_VF_SYND1_QTYPE\t0x03000000\n+#define DLB2_SYS_ALARM_VF_SYND1_QPRI\t\t0x1C000000\n+#define DLB2_SYS_ALARM_VF_SYND1_MSG_TYPE\t0xE0000000\n+#define DLB2_SYS_ALARM_VF_SYND1_DSI_LOC\t0\n+#define DLB2_SYS_ALARM_VF_SYND1_QID_LOC\t16\n+#define DLB2_SYS_ALARM_VF_SYND1_QTYPE_LOC\t24\n+#define DLB2_SYS_ALARM_VF_SYND1_QPRI_LOC\t26\n+#define DLB2_SYS_ALARM_VF_SYND1_MSG_TYPE_LOC\t29\n \n #define DLB2_SYS_ALARM_VF_SYND0(x) \\\n \t(0x10000f40 + (x) * 0x1000)\n #define DLB2_SYS_ALARM_VF_SYND0_RST 0x0\n-union dlb2_sys_alarm_vf_synd0 {\n-\tstruct {\n-\t\tu32 syndrome : 8;\n-\t\tu32 rtype : 2;\n-\t\tu32 vf_synd0_parity : 1;\n-\t\tu32 vf_synd1_parity : 1;\n-\t\tu32 vf_synd2_parity : 1;\n-\t\tu32 is_ldb : 1;\n-\t\tu32 cls : 2;\n-\t\tu32 aid : 6;\n-\t\tu32 unit : 4;\n-\t\tu32 source : 4;\n-\t\tu32 more : 1;\n-\t\tu32 valid : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_ALARM_VF_SYND0_SYNDROME\t\t0x000000FF\n+#define DLB2_SYS_ALARM_VF_SYND0_RTYPE\t\t0x00000300\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND0_PARITY\t0x00000400\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND1_PARITY\t0x00000800\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND2_PARITY\t0x00001000\n+#define DLB2_SYS_ALARM_VF_SYND0_IS_LDB\t\t0x00002000\n+#define DLB2_SYS_ALARM_VF_SYND0_CLS\t\t\t0x0000C000\n+#define DLB2_SYS_ALARM_VF_SYND0_AID\t\t\t0x003F0000\n+#define DLB2_SYS_ALARM_VF_SYND0_UNIT\t\t\t0x03C00000\n+#define DLB2_SYS_ALARM_VF_SYND0_SOURCE\t\t0x3C000000\n+#define DLB2_SYS_ALARM_VF_SYND0_MORE\t\t\t0x40000000\n+#define DLB2_SYS_ALARM_VF_SYND0_VALID\t\t0x80000000\n+#define DLB2_SYS_ALARM_VF_SYND0_SYNDROME_LOC\t\t0\n+#define DLB2_SYS_ALARM_VF_SYND0_RTYPE_LOC\t\t8\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND0_PARITY_LOC\t10\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND1_PARITY_LOC\t11\n+#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND2_PARITY_LOC\t12\n+#define DLB2_SYS_ALARM_VF_SYND0_IS_LDB_LOC\t\t13\n+#define DLB2_SYS_ALARM_VF_SYND0_CLS_LOC\t\t14\n+#define DLB2_SYS_ALARM_VF_SYND0_AID_LOC\t\t16\n+#define DLB2_SYS_ALARM_VF_SYND0_UNIT_LOC\t\t22\n+#define DLB2_SYS_ALARM_VF_SYND0_SOURCE_LOC\t\t26\n+#define DLB2_SYS_ALARM_VF_SYND0_MORE_LOC\t\t30\n+#define DLB2_SYS_ALARM_VF_SYND0_VALID_LOC\t\t31\n \n #define DLB2_SYS_LDB_QID_CFG_V(x) \\\n \t(0x10000f58 + (x) * 0x1000)\n #define DLB2_SYS_LDB_QID_CFG_V_RST 0x0\n-union dlb2_sys_ldb_qid_cfg_v {\n-\tstruct {\n-\t\tu32 sn_cfg_v : 1;\n-\t\tu32 fid_cfg_v : 1;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_QID_CFG_V_SN_CFG_V\t0x00000001\n+#define DLB2_SYS_LDB_QID_CFG_V_FID_CFG_V\t0x00000002\n+#define DLB2_SYS_LDB_QID_CFG_V_RSVD0\t\t0xFFFFFFFC\n+#define DLB2_SYS_LDB_QID_CFG_V_SN_CFG_V_LOC\t0\n+#define DLB2_SYS_LDB_QID_CFG_V_FID_CFG_V_LOC\t1\n+#define DLB2_SYS_LDB_QID_CFG_V_RSVD0_LOC\t2\n \n #define DLB2_SYS_LDB_QID_ITS(x) \\\n \t(0x10000f54 + (x) * 0x1000)\n #define DLB2_SYS_LDB_QID_ITS_RST 0x0\n-union dlb2_sys_ldb_qid_its {\n-\tstruct {\n-\t\tu32 qid_its : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_QID_ITS_QID_ITS\t0x00000001\n+#define DLB2_SYS_LDB_QID_ITS_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_LDB_QID_ITS_QID_ITS_LOC\t0\n+#define DLB2_SYS_LDB_QID_ITS_RSVD0_LOC\t1\n \n #define DLB2_SYS_LDB_QID_V(x) \\\n \t(0x10000f50 + (x) * 0x1000)\n #define DLB2_SYS_LDB_QID_V_RST 0x0\n-union dlb2_sys_ldb_qid_v {\n-\tstruct {\n-\t\tu32 qid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_QID_V_QID_V\t0x00000001\n+#define DLB2_SYS_LDB_QID_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_LDB_QID_V_QID_V_LOC\t0\n+#define DLB2_SYS_LDB_QID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_DIR_QID_ITS(x) \\\n \t(0x10000f64 + (x) * 0x1000)\n #define DLB2_SYS_DIR_QID_ITS_RST 0x0\n-union dlb2_sys_dir_qid_its {\n-\tstruct {\n-\t\tu32 qid_its : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_QID_ITS_QID_ITS\t0x00000001\n+#define DLB2_SYS_DIR_QID_ITS_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_DIR_QID_ITS_QID_ITS_LOC\t0\n+#define DLB2_SYS_DIR_QID_ITS_RSVD0_LOC\t1\n \n #define DLB2_SYS_DIR_QID_V(x) \\\n \t(0x10000f60 + (x) * 0x1000)\n #define DLB2_SYS_DIR_QID_V_RST 0x0\n-union dlb2_sys_dir_qid_v {\n-\tstruct {\n-\t\tu32 qid_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_QID_V_QID_V\t0x00000001\n+#define DLB2_SYS_DIR_QID_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_DIR_QID_V_QID_V_LOC\t0\n+#define DLB2_SYS_DIR_QID_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_LDB_CQ_AI_DATA(x) \\\n \t(0x10000fa8 + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ_AI_DATA_RST 0x0\n-union dlb2_sys_ldb_cq_ai_data {\n-\tstruct {\n-\t\tu32 cq_ai_data : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_AI_DATA_CQ_AI_DATA\t0xFFFFFFFF\n+#define DLB2_SYS_LDB_CQ_AI_DATA_CQ_AI_DATA_LOC\t0\n \n #define DLB2_SYS_LDB_CQ_AI_ADDR(x) \\\n \t(0x10000fa4 + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ_AI_ADDR_RST 0x0\n-union dlb2_sys_ldb_cq_ai_addr {\n-\tstruct {\n-\t\tu32 rsvd1 : 2;\n-\t\tu32 cq_ai_addr : 18;\n-\t\tu32 rsvd0 : 12;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_LDB_CQ_PASID(x) \\\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD1\t0x00000003\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_CQ_AI_ADDR\t0x000FFFFC\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD0\t0xFFF00000\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD1_LOC\t\t0\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_CQ_AI_ADDR_LOC\t2\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD0_LOC\t\t20\n+\n+#define DLB2_V2SYS_LDB_CQ_PASID(x) \\\n \t(0x10000fa0 + (x) * 0x1000)\n+#define DLB2_V2_5SYS_LDB_CQ_PASID(x) \\\n+\t(0x10000f9c + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_PASID(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2SYS_LDB_CQ_PASID(x) : \\\n+\t DLB2_V2_5SYS_LDB_CQ_PASID(x))\n #define DLB2_SYS_LDB_CQ_PASID_RST 0x0\n-union dlb2_sys_ldb_cq_pasid {\n-\tstruct {\n-\t\tu32 pasid : 20;\n-\t\tu32 exe_req : 1;\n-\t\tu32 priv_req : 1;\n-\t\tu32 fmt2 : 1;\n-\t\tu32 rsvd0 : 9;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_PASID_PASID\t\t0x000FFFFF\n+#define DLB2_SYS_LDB_CQ_PASID_EXE_REQ\t0x00100000\n+#define DLB2_SYS_LDB_CQ_PASID_PRIV_REQ\t0x00200000\n+#define DLB2_SYS_LDB_CQ_PASID_FMT2\t\t0x00400000\n+#define DLB2_SYS_LDB_CQ_PASID_RSVD0\t\t0xFF800000\n+#define DLB2_SYS_LDB_CQ_PASID_PASID_LOC\t0\n+#define DLB2_SYS_LDB_CQ_PASID_EXE_REQ_LOC\t20\n+#define DLB2_SYS_LDB_CQ_PASID_PRIV_REQ_LOC\t21\n+#define DLB2_SYS_LDB_CQ_PASID_FMT2_LOC\t22\n+#define DLB2_SYS_LDB_CQ_PASID_RSVD0_LOC\t23\n \n #define DLB2_SYS_LDB_CQ_AT(x) \\\n \t(0x10000f9c + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ_AT_RST 0x0\n-union dlb2_sys_ldb_cq_at {\n-\tstruct {\n-\t\tu32 cq_at : 2;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_AT_CQ_AT\t0x00000003\n+#define DLB2_SYS_LDB_CQ_AT_RSVD0\t0xFFFFFFFC\n+#define DLB2_SYS_LDB_CQ_AT_CQ_AT_LOC\t0\n+#define DLB2_SYS_LDB_CQ_AT_RSVD0_LOC\t2\n \n #define DLB2_SYS_LDB_CQ_ISR(x) \\\n \t(0x10000f98 + (x) * 0x1000)\n@@ -563,497 +560,891 @@ union dlb2_sys_ldb_cq_at {\n #define DLB2_CQ_ISR_MODE_MSI  1\n #define DLB2_CQ_ISR_MODE_MSIX 2\n #define DLB2_CQ_ISR_MODE_ADI  3\n-union dlb2_sys_ldb_cq_isr {\n-\tstruct {\n-\t\tu32 vector : 6;\n-\t\tu32 vf : 4;\n-\t\tu32 en_code : 2;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_ISR_VECTOR\t0x0000003F\n+#define DLB2_SYS_LDB_CQ_ISR_VF\t0x000003C0\n+#define DLB2_SYS_LDB_CQ_ISR_EN_CODE\t0x00000C00\n+#define DLB2_SYS_LDB_CQ_ISR_RSVD0\t0xFFFFF000\n+#define DLB2_SYS_LDB_CQ_ISR_VECTOR_LOC\t0\n+#define DLB2_SYS_LDB_CQ_ISR_VF_LOC\t\t6\n+#define DLB2_SYS_LDB_CQ_ISR_EN_CODE_LOC\t10\n+#define DLB2_SYS_LDB_CQ_ISR_RSVD0_LOC\t12\n \n #define DLB2_SYS_LDB_CQ2VF_PF_RO(x) \\\n \t(0x10000f94 + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ2VF_PF_RO_RST 0x0\n-union dlb2_sys_ldb_cq2vf_pf_ro {\n-\tstruct {\n-\t\tu32 vf : 4;\n-\t\tu32 is_pf : 1;\n-\t\tu32 ro : 1;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_VF\t\t0x0000000F\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_IS_PF\t0x00000010\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_RO\t\t0x00000020\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_VF_LOC\t0\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_IS_PF_LOC\t4\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_RO_LOC\t5\n+#define DLB2_SYS_LDB_CQ2VF_PF_RO_RSVD0_LOC\t6\n \n #define DLB2_SYS_LDB_PP_V(x) \\\n \t(0x10000f90 + (x) * 0x1000)\n #define DLB2_SYS_LDB_PP_V_RST 0x0\n-union dlb2_sys_ldb_pp_v {\n-\tstruct {\n-\t\tu32 pp_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_PP_V_PP_V\t0x00000001\n+#define DLB2_SYS_LDB_PP_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_LDB_PP_V_PP_V_LOC\t0\n+#define DLB2_SYS_LDB_PP_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_LDB_PP2VDEV(x) \\\n \t(0x10000f8c + (x) * 0x1000)\n #define DLB2_SYS_LDB_PP2VDEV_RST 0x0\n-union dlb2_sys_ldb_pp2vdev {\n-\tstruct {\n-\t\tu32 vdev : 4;\n-\t\tu32 rsvd0 : 28;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_PP2VDEV_VDEV\t0x0000000F\n+#define DLB2_SYS_LDB_PP2VDEV_RSVD0\t0xFFFFFFF0\n+#define DLB2_SYS_LDB_PP2VDEV_VDEV_LOC\t0\n+#define DLB2_SYS_LDB_PP2VDEV_RSVD0_LOC\t4\n \n #define DLB2_SYS_LDB_PP2VAS(x) \\\n \t(0x10000f88 + (x) * 0x1000)\n #define DLB2_SYS_LDB_PP2VAS_RST 0x0\n-union dlb2_sys_ldb_pp2vas {\n-\tstruct {\n-\t\tu32 vas : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_PP2VAS_VAS\t0x0000001F\n+#define DLB2_SYS_LDB_PP2VAS_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_LDB_PP2VAS_VAS_LOC\t\t0\n+#define DLB2_SYS_LDB_PP2VAS_RSVD0_LOC\t5\n \n #define DLB2_SYS_LDB_CQ_ADDR_U(x) \\\n \t(0x10000f84 + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ_ADDR_U_RST 0x0\n-union dlb2_sys_ldb_cq_addr_u {\n-\tstruct {\n-\t\tu32 addr_u : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_ADDR_U_ADDR_U\t0xFFFFFFFF\n+#define DLB2_SYS_LDB_CQ_ADDR_U_ADDR_U_LOC\t0\n \n #define DLB2_SYS_LDB_CQ_ADDR_L(x) \\\n \t(0x10000f80 + (x) * 0x1000)\n #define DLB2_SYS_LDB_CQ_ADDR_L_RST 0x0\n-union dlb2_sys_ldb_cq_addr_l {\n-\tstruct {\n-\t\tu32 rsvd0 : 6;\n-\t\tu32 addr_l : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_ADDR_L_RSVD0\t\t0x0000003F\n+#define DLB2_SYS_LDB_CQ_ADDR_L_ADDR_L\t0xFFFFFFC0\n+#define DLB2_SYS_LDB_CQ_ADDR_L_RSVD0_LOC\t0\n+#define DLB2_SYS_LDB_CQ_ADDR_L_ADDR_L_LOC\t6\n \n #define DLB2_SYS_DIR_CQ_FMT(x) \\\n \t(0x10000fec + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_FMT_RST 0x0\n-union dlb2_sys_dir_cq_fmt {\n-\tstruct {\n-\t\tu32 keep_pf_ppid : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_FMT_KEEP_PF_PPID\t0x00000001\n+#define DLB2_SYS_DIR_CQ_FMT_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_SYS_DIR_CQ_FMT_KEEP_PF_PPID_LOC\t0\n+#define DLB2_SYS_DIR_CQ_FMT_RSVD0_LOC\t1\n \n #define DLB2_SYS_DIR_CQ_AI_DATA(x) \\\n \t(0x10000fe8 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_AI_DATA_RST 0x0\n-union dlb2_sys_dir_cq_ai_data {\n-\tstruct {\n-\t\tu32 cq_ai_data : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_AI_DATA_CQ_AI_DATA\t0xFFFFFFFF\n+#define DLB2_SYS_DIR_CQ_AI_DATA_CQ_AI_DATA_LOC\t0\n \n #define DLB2_SYS_DIR_CQ_AI_ADDR(x) \\\n \t(0x10000fe4 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_AI_ADDR_RST 0x0\n-union dlb2_sys_dir_cq_ai_addr {\n-\tstruct {\n-\t\tu32 rsvd1 : 2;\n-\t\tu32 cq_ai_addr : 18;\n-\t\tu32 rsvd0 : 12;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_SYS_DIR_CQ_PASID(x) \\\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD1\t0x00000003\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_CQ_AI_ADDR\t0x000FFFFC\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD0\t0xFFF00000\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD1_LOC\t\t0\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_CQ_AI_ADDR_LOC\t2\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD0_LOC\t\t20\n+\n+#define DLB2_V2SYS_DIR_CQ_PASID(x) \\\n \t(0x10000fe0 + (x) * 0x1000)\n+#define DLB2_V2_5SYS_DIR_CQ_PASID(x) \\\n+\t(0x10000fdc + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_PASID(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2SYS_DIR_CQ_PASID(x) : \\\n+\t DLB2_V2_5SYS_DIR_CQ_PASID(x))\n #define DLB2_SYS_DIR_CQ_PASID_RST 0x0\n-union dlb2_sys_dir_cq_pasid {\n-\tstruct {\n-\t\tu32 pasid : 20;\n-\t\tu32 exe_req : 1;\n-\t\tu32 priv_req : 1;\n-\t\tu32 fmt2 : 1;\n-\t\tu32 rsvd0 : 9;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_PASID_PASID\t\t0x000FFFFF\n+#define DLB2_SYS_DIR_CQ_PASID_EXE_REQ\t0x00100000\n+#define DLB2_SYS_DIR_CQ_PASID_PRIV_REQ\t0x00200000\n+#define DLB2_SYS_DIR_CQ_PASID_FMT2\t\t0x00400000\n+#define DLB2_SYS_DIR_CQ_PASID_RSVD0\t\t0xFF800000\n+#define DLB2_SYS_DIR_CQ_PASID_PASID_LOC\t0\n+#define DLB2_SYS_DIR_CQ_PASID_EXE_REQ_LOC\t20\n+#define DLB2_SYS_DIR_CQ_PASID_PRIV_REQ_LOC\t21\n+#define DLB2_SYS_DIR_CQ_PASID_FMT2_LOC\t22\n+#define DLB2_SYS_DIR_CQ_PASID_RSVD0_LOC\t23\n \n #define DLB2_SYS_DIR_CQ_AT(x) \\\n \t(0x10000fdc + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_AT_RST 0x0\n-union dlb2_sys_dir_cq_at {\n-\tstruct {\n-\t\tu32 cq_at : 2;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_AT_CQ_AT\t0x00000003\n+#define DLB2_SYS_DIR_CQ_AT_RSVD0\t0xFFFFFFFC\n+#define DLB2_SYS_DIR_CQ_AT_CQ_AT_LOC\t0\n+#define DLB2_SYS_DIR_CQ_AT_RSVD0_LOC\t2\n \n #define DLB2_SYS_DIR_CQ_ISR(x) \\\n \t(0x10000fd8 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_ISR_RST 0x0\n-union dlb2_sys_dir_cq_isr {\n-\tstruct {\n-\t\tu32 vector : 6;\n-\t\tu32 vf : 4;\n-\t\tu32 en_code : 2;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_ISR_VECTOR\t0x0000003F\n+#define DLB2_SYS_DIR_CQ_ISR_VF\t0x000003C0\n+#define DLB2_SYS_DIR_CQ_ISR_EN_CODE\t0x00000C00\n+#define DLB2_SYS_DIR_CQ_ISR_RSVD0\t0xFFFFF000\n+#define DLB2_SYS_DIR_CQ_ISR_VECTOR_LOC\t0\n+#define DLB2_SYS_DIR_CQ_ISR_VF_LOC\t\t6\n+#define DLB2_SYS_DIR_CQ_ISR_EN_CODE_LOC\t10\n+#define DLB2_SYS_DIR_CQ_ISR_RSVD0_LOC\t12\n \n #define DLB2_SYS_DIR_CQ2VF_PF_RO(x) \\\n \t(0x10000fd4 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ2VF_PF_RO_RST 0x0\n-union dlb2_sys_dir_cq2vf_pf_ro {\n-\tstruct {\n-\t\tu32 vf : 4;\n-\t\tu32 is_pf : 1;\n-\t\tu32 ro : 1;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_VF\t\t0x0000000F\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_IS_PF\t0x00000010\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_RO\t\t0x00000020\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_VF_LOC\t0\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_IS_PF_LOC\t4\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_RO_LOC\t5\n+#define DLB2_SYS_DIR_CQ2VF_PF_RO_RSVD0_LOC\t6\n \n #define DLB2_SYS_DIR_PP_V(x) \\\n \t(0x10000fd0 + (x) * 0x1000)\n #define DLB2_SYS_DIR_PP_V_RST 0x0\n-union dlb2_sys_dir_pp_v {\n-\tstruct {\n-\t\tu32 pp_v : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_PP_V_PP_V\t0x00000001\n+#define DLB2_SYS_DIR_PP_V_RSVD0\t0xFFFFFFFE\n+#define DLB2_SYS_DIR_PP_V_PP_V_LOC\t0\n+#define DLB2_SYS_DIR_PP_V_RSVD0_LOC\t1\n \n #define DLB2_SYS_DIR_PP2VDEV(x) \\\n \t(0x10000fcc + (x) * 0x1000)\n #define DLB2_SYS_DIR_PP2VDEV_RST 0x0\n-union dlb2_sys_dir_pp2vdev {\n-\tstruct {\n-\t\tu32 vdev : 4;\n-\t\tu32 rsvd0 : 28;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_PP2VDEV_VDEV\t0x0000000F\n+#define DLB2_SYS_DIR_PP2VDEV_RSVD0\t0xFFFFFFF0\n+#define DLB2_SYS_DIR_PP2VDEV_VDEV_LOC\t0\n+#define DLB2_SYS_DIR_PP2VDEV_RSVD0_LOC\t4\n \n #define DLB2_SYS_DIR_PP2VAS(x) \\\n \t(0x10000fc8 + (x) * 0x1000)\n #define DLB2_SYS_DIR_PP2VAS_RST 0x0\n-union dlb2_sys_dir_pp2vas {\n-\tstruct {\n-\t\tu32 vas : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_PP2VAS_VAS\t0x0000001F\n+#define DLB2_SYS_DIR_PP2VAS_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_DIR_PP2VAS_VAS_LOC\t\t0\n+#define DLB2_SYS_DIR_PP2VAS_RSVD0_LOC\t5\n \n #define DLB2_SYS_DIR_CQ_ADDR_U(x) \\\n \t(0x10000fc4 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_ADDR_U_RST 0x0\n-union dlb2_sys_dir_cq_addr_u {\n-\tstruct {\n-\t\tu32 addr_u : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_ADDR_U_ADDR_U\t0xFFFFFFFF\n+#define DLB2_SYS_DIR_CQ_ADDR_U_ADDR_U_LOC\t0\n \n #define DLB2_SYS_DIR_CQ_ADDR_L(x) \\\n \t(0x10000fc0 + (x) * 0x1000)\n #define DLB2_SYS_DIR_CQ_ADDR_L_RST 0x0\n-union dlb2_sys_dir_cq_addr_l {\n-\tstruct {\n-\t\tu32 rsvd0 : 6;\n-\t\tu32 addr_l : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_ADDR_L_RSVD0\t\t0x0000003F\n+#define DLB2_SYS_DIR_CQ_ADDR_L_ADDR_L\t0xFFFFFFC0\n+#define DLB2_SYS_DIR_CQ_ADDR_L_RSVD0_LOC\t0\n+#define DLB2_SYS_DIR_CQ_ADDR_L_ADDR_L_LOC\t6\n+\n+#define DLB2_SYS_PM_SMON_COMP_MASK1 0x10003024\n+#define DLB2_SYS_PM_SMON_COMP_MASK1_RST 0xffffffff\n+\n+#define DLB2_SYS_PM_SMON_COMP_MASK1_COMP_MASK1\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_COMP_MASK1_COMP_MASK1_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_COMP_MASK0 0x10003020\n+#define DLB2_SYS_PM_SMON_COMP_MASK0_RST 0xffffffff\n+\n+#define DLB2_SYS_PM_SMON_COMP_MASK0_COMP_MASK0\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_COMP_MASK0_COMP_MASK0_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_MAX_TMR 0x1000301c\n+#define DLB2_SYS_PM_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_TMR 0x10003018\n+#define DLB2_SYS_PM_SMON_TMR_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_TMR_TIMER_VAL\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_TMR_TIMER_VAL_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1 0x10003014\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0 0x10003010\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_COMPARE1 0x1000300c\n+#define DLB2_SYS_PM_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_COMPARE0 0x10003008\n+#define DLB2_SYS_PM_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_SYS_PM_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_SYS_PM_SMON_CFG1 0x10003004\n+#define DLB2_SYS_PM_SMON_CFG1_RST 0x0\n+\n+#define DLB2_SYS_PM_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_SYS_PM_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_SYS_PM_SMON_CFG1_RSVD\t0xFFFF0000\n+#define DLB2_SYS_PM_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_SYS_PM_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_SYS_PM_SMON_CFG1_RSVD_LOC\t16\n+\n+#define DLB2_SYS_PM_SMON_CFG0 0x10003000\n+#define DLB2_SYS_PM_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_SYS_PM_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD2\t\t\t0x0000000E\n+#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_SYS_PM_SMON_CFG0_SMON_MODE\t\t0x0000F000\n+#define DLB2_SYS_PM_SMON_CFG0_STOPCOUNTEROVFL\t0x00010000\n+#define DLB2_SYS_PM_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER0OVFL\t0x00040000\n+#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER1OVFL\t0x00080000\n+#define DLB2_SYS_PM_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_SYS_PM_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_SYS_PM_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD1\t\t\t0x00800000\n+#define DLB2_SYS_PM_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD0\t\t\t0x20000000\n+#define DLB2_SYS_PM_SMON_CFG0_VERSION\t\t0xC0000000\n+#define DLB2_SYS_PM_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD2_LOC\t\t\t1\n+#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_SYS_PM_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_SYS_PM_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_SYS_PM_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_SYS_PM_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_SYS_PM_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n+#define DLB2_SYS_PM_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD1_LOC\t\t\t23\n+#define DLB2_SYS_PM_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_SYS_PM_SMON_CFG0_RSVD0_LOC\t\t\t29\n+#define DLB2_SYS_PM_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_SYS_SMON_COMP_MASK1(x) \\\n+\t(0x18002024 + (x) * 0x40)\n+#define DLB2_SYS_SMON_COMP_MASK1_RST 0xffffffff\n+\n+#define DLB2_SYS_SMON_COMP_MASK1_COMP_MASK1\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_COMP_MASK1_COMP_MASK1_LOC\t0\n+\n+#define DLB2_SYS_SMON_COMP_MASK0(x) \\\n+\t(0x18002020 + (x) * 0x40)\n+#define DLB2_SYS_SMON_COMP_MASK0_RST 0xffffffff\n+\n+#define DLB2_SYS_SMON_COMP_MASK0_COMP_MASK0\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_COMP_MASK0_COMP_MASK0_LOC\t0\n+\n+#define DLB2_SYS_SMON_MAX_TMR(x) \\\n+\t(0x1800201c + (x) * 0x40)\n+#define DLB2_SYS_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_SYS_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_SYS_SMON_TMR(x) \\\n+\t(0x18002018 + (x) * 0x40)\n+#define DLB2_SYS_SMON_TMR_RST 0x0\n+\n+#define DLB2_SYS_SMON_TMR_TIMER_VAL\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_TMR_TIMER_VAL_LOC\t0\n+\n+#define DLB2_SYS_SMON_ACTIVITYCNTR1(x) \\\n+\t(0x18002014 + (x) * 0x40)\n+#define DLB2_SYS_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_SYS_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_SYS_SMON_ACTIVITYCNTR0(x) \\\n+\t(0x18002010 + (x) * 0x40)\n+#define DLB2_SYS_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_SYS_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_SYS_SMON_COMPARE1(x) \\\n+\t(0x1800200c + (x) * 0x40)\n+#define DLB2_SYS_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_SYS_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_SYS_SMON_COMPARE0(x) \\\n+\t(0x18002008 + (x) * 0x40)\n+#define DLB2_SYS_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_SYS_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_SYS_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_SYS_SMON_CFG1(x) \\\n+\t(0x18002004 + (x) * 0x40)\n+#define DLB2_SYS_SMON_CFG1_RST 0x0\n+\n+#define DLB2_SYS_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_SYS_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_SYS_SMON_CFG1_RSVD\t0xFFFF0000\n+#define DLB2_SYS_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_SYS_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_SYS_SMON_CFG1_RSVD_LOC\t16\n+\n+#define DLB2_SYS_SMON_CFG0(x) \\\n+\t(0x18002000 + (x) * 0x40)\n+#define DLB2_SYS_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_SYS_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_SYS_SMON_CFG0_RSVD2\t\t\t0x0000000E\n+#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_SYS_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_SYS_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_SYS_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_SYS_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_SYS_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_SYS_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_SYS_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_SYS_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_SYS_SMON_CFG0_RSVD1\t\t\t0x00800000\n+#define DLB2_SYS_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_SYS_SMON_CFG0_RSVD0\t\t\t0x20000000\n+#define DLB2_SYS_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_SYS_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_SYS_SMON_CFG0_RSVD2_LOC\t\t\t\t1\n+#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_SYS_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_SYS_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_SYS_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_SYS_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_SYS_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_SYS_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n+#define DLB2_SYS_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_SYS_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n+#define DLB2_SYS_SMON_CFG0_RSVD1_LOC\t\t\t\t23\n+#define DLB2_SYS_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_SYS_SMON_CFG0_RSVD0_LOC\t\t\t\t29\n+#define DLB2_SYS_SMON_CFG0_VERSION_LOC\t\t\t30\n \n #define DLB2_SYS_INGRESS_ALARM_ENBL 0x10000300\n #define DLB2_SYS_INGRESS_ALARM_ENBL_RST 0x0\n-union dlb2_sys_ingress_alarm_enbl {\n-\tstruct {\n-\t\tu32 illegal_hcw : 1;\n-\t\tu32 illegal_pp : 1;\n-\t\tu32 illegal_pasid : 1;\n-\t\tu32 illegal_qid : 1;\n-\t\tu32 disabled_qid : 1;\n-\t\tu32 illegal_ldb_qid_cfg : 1;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_HCW\t\t0x00000001\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PP\t\t0x00000002\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PASID\t\t0x00000004\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_QID\t\t0x00000008\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_DISABLED_QID\t\t0x00000010\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_LDB_QID_CFG\t0x00000020\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_RSVD0\t\t\t0xFFFFFFC0\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_HCW_LOC\t\t0\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PP_LOC\t\t1\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PASID_LOC\t2\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_QID_LOC\t\t3\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_DISABLED_QID_LOC\t\t4\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_LDB_QID_CFG_LOC\t5\n+#define DLB2_SYS_INGRESS_ALARM_ENBL_RSVD0_LOC\t\t6\n \n #define DLB2_SYS_MSIX_ACK 0x10000400\n #define DLB2_SYS_MSIX_ACK_RST 0x0\n-union dlb2_sys_msix_ack {\n-\tstruct {\n-\t\tu32 msix_0_ack : 1;\n-\t\tu32 msix_1_ack : 1;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_MSIX_ACK_MSIX_0_ACK\t0x00000001\n+#define DLB2_SYS_MSIX_ACK_MSIX_1_ACK\t0x00000002\n+#define DLB2_SYS_MSIX_ACK_RSVD0\t0xFFFFFFFC\n+#define DLB2_SYS_MSIX_ACK_MSIX_0_ACK_LOC\t0\n+#define DLB2_SYS_MSIX_ACK_MSIX_1_ACK_LOC\t1\n+#define DLB2_SYS_MSIX_ACK_RSVD0_LOC\t\t2\n \n #define DLB2_SYS_MSIX_PASSTHRU 0x10000404\n #define DLB2_SYS_MSIX_PASSTHRU_RST 0x0\n-union dlb2_sys_msix_passthru {\n-\tstruct {\n-\t\tu32 msix_0_passthru : 1;\n-\t\tu32 msix_1_passthru : 1;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_MSIX_PASSTHRU_MSIX_0_PASSTHRU\t0x00000001\n+#define DLB2_SYS_MSIX_PASSTHRU_MSIX_1_PASSTHRU\t0x00000002\n+#define DLB2_SYS_MSIX_PASSTHRU_RSVD0\t\t\t0xFFFFFFFC\n+#define DLB2_SYS_MSIX_PASSTHRU_MSIX_0_PASSTHRU_LOC\t0\n+#define DLB2_SYS_MSIX_PASSTHRU_MSIX_1_PASSTHRU_LOC\t1\n+#define DLB2_SYS_MSIX_PASSTHRU_RSVD0_LOC\t\t2\n \n #define DLB2_SYS_MSIX_MODE 0x10000408\n #define DLB2_SYS_MSIX_MODE_RST 0x0\n /* MSI-X Modes */\n #define DLB2_MSIX_MODE_PACKED     0\n #define DLB2_MSIX_MODE_COMPRESSED 1\n-union dlb2_sys_msix_mode {\n-\tstruct {\n-\t\tu32 mode : 1;\n-\t\tu32 poll_mode : 1;\n-\t\tu32 poll_mask : 1;\n-\t\tu32 poll_lock : 1;\n-\t\tu32 rsvd0 : 28;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_MSIX_MODE_MODE_V2\t0x00000001\n+#define DLB2_SYS_MSIX_MODE_POLL_MODE_V2\t0x00000002\n+#define DLB2_SYS_MSIX_MODE_POLL_MASK_V2\t0x00000004\n+#define DLB2_SYS_MSIX_MODE_POLL_LOCK_V2\t0x00000008\n+#define DLB2_SYS_MSIX_MODE_RSVD0_V2\t0xFFFFFFF0\n+#define DLB2_SYS_MSIX_MODE_MODE_V2_LOC\t0\n+#define DLB2_SYS_MSIX_MODE_POLL_MODE_V2_LOC\t1\n+#define DLB2_SYS_MSIX_MODE_POLL_MASK_V2_LOC\t2\n+#define DLB2_SYS_MSIX_MODE_POLL_LOCK_V2_LOC\t3\n+#define DLB2_SYS_MSIX_MODE_RSVD0_V2_LOC\t4\n+\n+#define DLB2_SYS_MSIX_MODE_MODE_V2_5\t0x00000001\n+#define DLB2_SYS_MSIX_MODE_IMS_POLLING_V2_5\t0x00000002\n+#define DLB2_SYS_MSIX_MODE_RSVD0_V2_5\t0xFFFFFFFC\n+#define DLB2_SYS_MSIX_MODE_MODE_V2_5_LOC\t\t0\n+#define DLB2_SYS_MSIX_MODE_IMS_POLLING_V2_5_LOC\t1\n+#define DLB2_SYS_MSIX_MODE_RSVD0_V2_5_LOC\t\t2\n \n #define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS 0x10000440\n #define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0\n-union dlb2_sys_dir_cq_31_0_occ_int_sts {\n-\tstruct {\n-\t\tu32 cq_0_occ_int : 1;\n-\t\tu32 cq_1_occ_int : 1;\n-\t\tu32 cq_2_occ_int : 1;\n-\t\tu32 cq_3_occ_int : 1;\n-\t\tu32 cq_4_occ_int : 1;\n-\t\tu32 cq_5_occ_int : 1;\n-\t\tu32 cq_6_occ_int : 1;\n-\t\tu32 cq_7_occ_int : 1;\n-\t\tu32 cq_8_occ_int : 1;\n-\t\tu32 cq_9_occ_int : 1;\n-\t\tu32 cq_10_occ_int : 1;\n-\t\tu32 cq_11_occ_int : 1;\n-\t\tu32 cq_12_occ_int : 1;\n-\t\tu32 cq_13_occ_int : 1;\n-\t\tu32 cq_14_occ_int : 1;\n-\t\tu32 cq_15_occ_int : 1;\n-\t\tu32 cq_16_occ_int : 1;\n-\t\tu32 cq_17_occ_int : 1;\n-\t\tu32 cq_18_occ_int : 1;\n-\t\tu32 cq_19_occ_int : 1;\n-\t\tu32 cq_20_occ_int : 1;\n-\t\tu32 cq_21_occ_int : 1;\n-\t\tu32 cq_22_occ_int : 1;\n-\t\tu32 cq_23_occ_int : 1;\n-\t\tu32 cq_24_occ_int : 1;\n-\t\tu32 cq_25_occ_int : 1;\n-\t\tu32 cq_26_occ_int : 1;\n-\t\tu32 cq_27_occ_int : 1;\n-\t\tu32 cq_28_occ_int : 1;\n-\t\tu32 cq_29_occ_int : 1;\n-\t\tu32 cq_30_occ_int : 1;\n-\t\tu32 cq_31_occ_int : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT\t0x00000001\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT\t0x00000002\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT\t0x00000004\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT\t0x00000008\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT\t0x00000010\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT\t0x00000020\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT\t0x00000040\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT\t0x00000080\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT\t0x00000100\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT\t0x00000200\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT\t0x00000400\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT\t0x00000800\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT\t0x00001000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT\t0x00002000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT\t0x00004000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT\t0x00008000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT\t0x00010000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT\t0x00020000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT\t0x00040000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT\t0x00080000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT\t0x00100000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT\t0x00200000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT\t0x00400000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT\t0x00800000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT\t0x01000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT\t0x02000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT\t0x04000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT\t0x08000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT\t0x10000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT\t0x20000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT\t0x40000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT\t0x80000000\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT_LOC\t0\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT_LOC\t1\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT_LOC\t2\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT_LOC\t3\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT_LOC\t4\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT_LOC\t5\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT_LOC\t6\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT_LOC\t7\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT_LOC\t8\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT_LOC\t9\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT_LOC\t10\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT_LOC\t11\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT_LOC\t12\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT_LOC\t13\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT_LOC\t14\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT_LOC\t15\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT_LOC\t16\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT_LOC\t17\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT_LOC\t18\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT_LOC\t19\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT_LOC\t20\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT_LOC\t21\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT_LOC\t22\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT_LOC\t23\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT_LOC\t24\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT_LOC\t25\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT_LOC\t26\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT_LOC\t27\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT_LOC\t28\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT_LOC\t29\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT_LOC\t30\n+#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT_LOC\t31\n \n #define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS 0x10000444\n #define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0\n-union dlb2_sys_dir_cq_63_32_occ_int_sts {\n-\tstruct {\n-\t\tu32 cq_32_occ_int : 1;\n-\t\tu32 cq_33_occ_int : 1;\n-\t\tu32 cq_34_occ_int : 1;\n-\t\tu32 cq_35_occ_int : 1;\n-\t\tu32 cq_36_occ_int : 1;\n-\t\tu32 cq_37_occ_int : 1;\n-\t\tu32 cq_38_occ_int : 1;\n-\t\tu32 cq_39_occ_int : 1;\n-\t\tu32 cq_40_occ_int : 1;\n-\t\tu32 cq_41_occ_int : 1;\n-\t\tu32 cq_42_occ_int : 1;\n-\t\tu32 cq_43_occ_int : 1;\n-\t\tu32 cq_44_occ_int : 1;\n-\t\tu32 cq_45_occ_int : 1;\n-\t\tu32 cq_46_occ_int : 1;\n-\t\tu32 cq_47_occ_int : 1;\n-\t\tu32 cq_48_occ_int : 1;\n-\t\tu32 cq_49_occ_int : 1;\n-\t\tu32 cq_50_occ_int : 1;\n-\t\tu32 cq_51_occ_int : 1;\n-\t\tu32 cq_52_occ_int : 1;\n-\t\tu32 cq_53_occ_int : 1;\n-\t\tu32 cq_54_occ_int : 1;\n-\t\tu32 cq_55_occ_int : 1;\n-\t\tu32 cq_56_occ_int : 1;\n-\t\tu32 cq_57_occ_int : 1;\n-\t\tu32 cq_58_occ_int : 1;\n-\t\tu32 cq_59_occ_int : 1;\n-\t\tu32 cq_60_occ_int : 1;\n-\t\tu32 cq_61_occ_int : 1;\n-\t\tu32 cq_62_occ_int : 1;\n-\t\tu32 cq_63_occ_int : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT\t0x00000001\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT\t0x00000002\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT\t0x00000004\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT\t0x00000008\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT\t0x00000010\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT\t0x00000020\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT\t0x00000040\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT\t0x00000080\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT\t0x00000100\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT\t0x00000200\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT\t0x00000400\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT\t0x00000800\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT\t0x00001000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT\t0x00002000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT\t0x00004000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT\t0x00008000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT\t0x00010000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT\t0x00020000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT\t0x00040000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT\t0x00080000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT\t0x00100000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT\t0x00200000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT\t0x00400000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT\t0x00800000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT\t0x01000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT\t0x02000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT\t0x04000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT\t0x08000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT\t0x10000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT\t0x20000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT\t0x40000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT\t0x80000000\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT_LOC\t0\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT_LOC\t1\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT_LOC\t2\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT_LOC\t3\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT_LOC\t4\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT_LOC\t5\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT_LOC\t6\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT_LOC\t7\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT_LOC\t8\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT_LOC\t9\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT_LOC\t10\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT_LOC\t11\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT_LOC\t12\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT_LOC\t13\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT_LOC\t14\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT_LOC\t15\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT_LOC\t16\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT_LOC\t17\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT_LOC\t18\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT_LOC\t19\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT_LOC\t20\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT_LOC\t21\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT_LOC\t22\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT_LOC\t23\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT_LOC\t24\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT_LOC\t25\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT_LOC\t26\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT_LOC\t27\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT_LOC\t28\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT_LOC\t29\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT_LOC\t30\n+#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT_LOC\t31\n \n #define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS 0x10000460\n #define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0\n-union dlb2_sys_ldb_cq_31_0_occ_int_sts {\n-\tstruct {\n-\t\tu32 cq_0_occ_int : 1;\n-\t\tu32 cq_1_occ_int : 1;\n-\t\tu32 cq_2_occ_int : 1;\n-\t\tu32 cq_3_occ_int : 1;\n-\t\tu32 cq_4_occ_int : 1;\n-\t\tu32 cq_5_occ_int : 1;\n-\t\tu32 cq_6_occ_int : 1;\n-\t\tu32 cq_7_occ_int : 1;\n-\t\tu32 cq_8_occ_int : 1;\n-\t\tu32 cq_9_occ_int : 1;\n-\t\tu32 cq_10_occ_int : 1;\n-\t\tu32 cq_11_occ_int : 1;\n-\t\tu32 cq_12_occ_int : 1;\n-\t\tu32 cq_13_occ_int : 1;\n-\t\tu32 cq_14_occ_int : 1;\n-\t\tu32 cq_15_occ_int : 1;\n-\t\tu32 cq_16_occ_int : 1;\n-\t\tu32 cq_17_occ_int : 1;\n-\t\tu32 cq_18_occ_int : 1;\n-\t\tu32 cq_19_occ_int : 1;\n-\t\tu32 cq_20_occ_int : 1;\n-\t\tu32 cq_21_occ_int : 1;\n-\t\tu32 cq_22_occ_int : 1;\n-\t\tu32 cq_23_occ_int : 1;\n-\t\tu32 cq_24_occ_int : 1;\n-\t\tu32 cq_25_occ_int : 1;\n-\t\tu32 cq_26_occ_int : 1;\n-\t\tu32 cq_27_occ_int : 1;\n-\t\tu32 cq_28_occ_int : 1;\n-\t\tu32 cq_29_occ_int : 1;\n-\t\tu32 cq_30_occ_int : 1;\n-\t\tu32 cq_31_occ_int : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT\t0x00000001\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT\t0x00000002\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT\t0x00000004\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT\t0x00000008\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT\t0x00000010\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT\t0x00000020\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT\t0x00000040\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT\t0x00000080\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT\t0x00000100\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT\t0x00000200\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT\t0x00000400\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT\t0x00000800\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT\t0x00001000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT\t0x00002000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT\t0x00004000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT\t0x00008000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT\t0x00010000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT\t0x00020000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT\t0x00040000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT\t0x00080000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT\t0x00100000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT\t0x00200000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT\t0x00400000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT\t0x00800000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT\t0x01000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT\t0x02000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT\t0x04000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT\t0x08000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT\t0x10000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT\t0x20000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT\t0x40000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT\t0x80000000\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT_LOC\t0\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT_LOC\t1\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT_LOC\t2\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT_LOC\t3\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT_LOC\t4\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT_LOC\t5\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT_LOC\t6\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT_LOC\t7\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT_LOC\t8\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT_LOC\t9\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT_LOC\t10\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT_LOC\t11\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT_LOC\t12\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT_LOC\t13\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT_LOC\t14\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT_LOC\t15\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT_LOC\t16\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT_LOC\t17\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT_LOC\t18\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT_LOC\t19\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT_LOC\t20\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT_LOC\t21\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT_LOC\t22\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT_LOC\t23\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT_LOC\t24\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT_LOC\t25\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT_LOC\t26\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT_LOC\t27\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT_LOC\t28\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT_LOC\t29\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT_LOC\t30\n+#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT_LOC\t31\n \n #define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS 0x10000464\n #define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0\n-union dlb2_sys_ldb_cq_63_32_occ_int_sts {\n-\tstruct {\n-\t\tu32 cq_32_occ_int : 1;\n-\t\tu32 cq_33_occ_int : 1;\n-\t\tu32 cq_34_occ_int : 1;\n-\t\tu32 cq_35_occ_int : 1;\n-\t\tu32 cq_36_occ_int : 1;\n-\t\tu32 cq_37_occ_int : 1;\n-\t\tu32 cq_38_occ_int : 1;\n-\t\tu32 cq_39_occ_int : 1;\n-\t\tu32 cq_40_occ_int : 1;\n-\t\tu32 cq_41_occ_int : 1;\n-\t\tu32 cq_42_occ_int : 1;\n-\t\tu32 cq_43_occ_int : 1;\n-\t\tu32 cq_44_occ_int : 1;\n-\t\tu32 cq_45_occ_int : 1;\n-\t\tu32 cq_46_occ_int : 1;\n-\t\tu32 cq_47_occ_int : 1;\n-\t\tu32 cq_48_occ_int : 1;\n-\t\tu32 cq_49_occ_int : 1;\n-\t\tu32 cq_50_occ_int : 1;\n-\t\tu32 cq_51_occ_int : 1;\n-\t\tu32 cq_52_occ_int : 1;\n-\t\tu32 cq_53_occ_int : 1;\n-\t\tu32 cq_54_occ_int : 1;\n-\t\tu32 cq_55_occ_int : 1;\n-\t\tu32 cq_56_occ_int : 1;\n-\t\tu32 cq_57_occ_int : 1;\n-\t\tu32 cq_58_occ_int : 1;\n-\t\tu32 cq_59_occ_int : 1;\n-\t\tu32 cq_60_occ_int : 1;\n-\t\tu32 cq_61_occ_int : 1;\n-\t\tu32 cq_62_occ_int : 1;\n-\t\tu32 cq_63_occ_int : 1;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT\t0x00000001\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT\t0x00000002\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT\t0x00000004\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT\t0x00000008\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT\t0x00000010\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT\t0x00000020\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT\t0x00000040\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT\t0x00000080\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT\t0x00000100\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT\t0x00000200\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT\t0x00000400\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT\t0x00000800\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT\t0x00001000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT\t0x00002000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT\t0x00004000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT\t0x00008000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT\t0x00010000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT\t0x00020000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT\t0x00040000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT\t0x00080000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT\t0x00100000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT\t0x00200000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT\t0x00400000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT\t0x00800000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT\t0x01000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT\t0x02000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT\t0x04000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT\t0x08000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT\t0x10000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT\t0x20000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT\t0x40000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT\t0x80000000\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT_LOC\t0\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT_LOC\t1\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT_LOC\t2\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT_LOC\t3\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT_LOC\t4\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT_LOC\t5\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT_LOC\t6\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT_LOC\t7\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT_LOC\t8\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT_LOC\t9\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT_LOC\t10\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT_LOC\t11\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT_LOC\t12\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT_LOC\t13\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT_LOC\t14\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT_LOC\t15\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT_LOC\t16\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT_LOC\t17\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT_LOC\t18\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT_LOC\t19\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT_LOC\t20\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT_LOC\t21\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT_LOC\t22\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT_LOC\t23\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT_LOC\t24\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT_LOC\t25\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT_LOC\t26\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT_LOC\t27\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT_LOC\t28\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT_LOC\t29\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT_LOC\t30\n+#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT_LOC\t31\n \n #define DLB2_SYS_DIR_CQ_OPT_CLR 0x100004c0\n #define DLB2_SYS_DIR_CQ_OPT_CLR_RST 0x0\n-union dlb2_sys_dir_cq_opt_clr {\n-\tstruct {\n-\t\tu32 cq : 6;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_SYS_DIR_CQ_OPT_CLR_CQ\t\t0x0000003F\n+#define DLB2_SYS_DIR_CQ_OPT_CLR_RSVD0\t0xFFFFFFC0\n+#define DLB2_SYS_DIR_CQ_OPT_CLR_CQ_LOC\t0\n+#define DLB2_SYS_DIR_CQ_OPT_CLR_RSVD0_LOC\t6\n \n #define DLB2_SYS_ALARM_HW_SYND 0x1000050c\n #define DLB2_SYS_ALARM_HW_SYND_RST 0x0\n-union dlb2_sys_alarm_hw_synd {\n-\tstruct {\n-\t\tu32 syndrome : 8;\n-\t\tu32 rtype : 2;\n-\t\tu32 alarm : 1;\n-\t\tu32 cwd : 1;\n-\t\tu32 vf_pf_mb : 1;\n-\t\tu32 rsvd0 : 1;\n-\t\tu32 cls : 2;\n-\t\tu32 aid : 6;\n-\t\tu32 unit : 4;\n-\t\tu32 source : 4;\n-\t\tu32 more : 1;\n-\t\tu32 valid : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_AQED_PIPE_QID_FID_LIM(x) \\\n+\n+#define DLB2_SYS_ALARM_HW_SYND_SYNDROME\t0x000000FF\n+#define DLB2_SYS_ALARM_HW_SYND_RTYPE\t\t0x00000300\n+#define DLB2_SYS_ALARM_HW_SYND_ALARM\t\t0x00000400\n+#define DLB2_SYS_ALARM_HW_SYND_CWD\t\t0x00000800\n+#define DLB2_SYS_ALARM_HW_SYND_VF_PF_MB\t0x00001000\n+#define DLB2_SYS_ALARM_HW_SYND_RSVD0\t\t0x00002000\n+#define DLB2_SYS_ALARM_HW_SYND_CLS\t\t0x0000C000\n+#define DLB2_SYS_ALARM_HW_SYND_AID\t\t0x003F0000\n+#define DLB2_SYS_ALARM_HW_SYND_UNIT\t\t0x03C00000\n+#define DLB2_SYS_ALARM_HW_SYND_SOURCE\t0x3C000000\n+#define DLB2_SYS_ALARM_HW_SYND_MORE\t\t0x40000000\n+#define DLB2_SYS_ALARM_HW_SYND_VALID\t\t0x80000000\n+#define DLB2_SYS_ALARM_HW_SYND_SYNDROME_LOC\t0\n+#define DLB2_SYS_ALARM_HW_SYND_RTYPE_LOC\t8\n+#define DLB2_SYS_ALARM_HW_SYND_ALARM_LOC\t10\n+#define DLB2_SYS_ALARM_HW_SYND_CWD_LOC\t11\n+#define DLB2_SYS_ALARM_HW_SYND_VF_PF_MB_LOC\t12\n+#define DLB2_SYS_ALARM_HW_SYND_RSVD0_LOC\t13\n+#define DLB2_SYS_ALARM_HW_SYND_CLS_LOC\t14\n+#define DLB2_SYS_ALARM_HW_SYND_AID_LOC\t16\n+#define DLB2_SYS_ALARM_HW_SYND_UNIT_LOC\t22\n+#define DLB2_SYS_ALARM_HW_SYND_SOURCE_LOC\t26\n+#define DLB2_SYS_ALARM_HW_SYND_MORE_LOC\t30\n+#define DLB2_SYS_ALARM_HW_SYND_VALID_LOC\t31\n+\n+#define DLB2_AQED_QID_FID_LIM(x) \\\n \t(0x20000000 + (x) * 0x1000)\n-#define DLB2_AQED_PIPE_QID_FID_LIM_RST 0x7ff\n-union dlb2_aqed_pipe_qid_fid_lim {\n-\tstruct {\n-\t\tu32 qid_fid_limit : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_AQED_PIPE_QID_HID_WIDTH(x) \\\n+#define DLB2_AQED_QID_FID_LIM_RST 0x7ff\n+\n+#define DLB2_AQED_QID_FID_LIM_QID_FID_LIMIT\t0x00001FFF\n+#define DLB2_AQED_QID_FID_LIM_RSVD0\t\t0xFFFFE000\n+#define DLB2_AQED_QID_FID_LIM_QID_FID_LIMIT_LOC\t0\n+#define DLB2_AQED_QID_FID_LIM_RSVD0_LOC\t\t13\n+\n+#define DLB2_AQED_QID_HID_WIDTH(x) \\\n \t(0x20080000 + (x) * 0x1000)\n-#define DLB2_AQED_PIPE_QID_HID_WIDTH_RST 0x0\n-union dlb2_aqed_pipe_qid_hid_width {\n-\tstruct {\n-\t\tu32 compress_code : 3;\n-\t\tu32 rsvd0 : 29;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004\n-#define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8\n-union dlb2_aqed_pipe_cfg_arb_weights_tqpri_atm_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+#define DLB2_AQED_QID_HID_WIDTH_RST 0x0\n+\n+#define DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE\t0x00000007\n+#define DLB2_AQED_QID_HID_WIDTH_RSVD0\t\t0xFFFFFFF8\n+#define DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE_LOC\t0\n+#define DLB2_AQED_QID_HID_WIDTH_RSVD0_LOC\t\t3\n+\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8\n+\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI0\t0x000000FF\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI1\t0x0000FF00\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI2\t0x00FF0000\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI3\t0xFF000000\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI0_LOC\t0\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI1_LOC\t8\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI2_LOC\t16\n+#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI3_LOC\t24\n+\n+#define DLB2_AQED_SMON_ACTIVITYCNTR0 0x2c00004c\n+#define DLB2_AQED_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_AQED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_AQED_SMON_ACTIVITYCNTR1 0x2c000050\n+#define DLB2_AQED_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_AQED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_AQED_SMON_COMPARE0 0x2c000054\n+#define DLB2_AQED_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_AQED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_AQED_SMON_COMPARE1 0x2c000058\n+#define DLB2_AQED_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_AQED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_AQED_SMON_CFG0 0x2c00005c\n+#define DLB2_AQED_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_AQED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_AQED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_AQED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_AQED_SMON_CFG0_SMON_MODE\t\t0x0000F000\n+#define DLB2_AQED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_AQED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_AQED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_AQED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_AQED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_AQED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_AQED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_AQED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_AQED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_AQED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_AQED_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_AQED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_AQED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_AQED_SMON_CFG0_RSVZ0_LOC\t\t\t2\n+#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_AQED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_AQED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_AQED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_AQED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_AQED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_AQED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_AQED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_AQED_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_AQED_SMON_CFG0_RSVZ1_LOC\t\t\t23\n+#define DLB2_AQED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_AQED_SMON_CFG0_RSVZ2_LOC\t\t\t29\n+#define DLB2_AQED_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_AQED_SMON_CFG1 0x2c000060\n+#define DLB2_AQED_SMON_CFG1_RST 0x0\n+\n+#define DLB2_AQED_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_AQED_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_AQED_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_AQED_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_AQED_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_AQED_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_AQED_SMON_MAX_TMR 0x2c000064\n+#define DLB2_AQED_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_AQED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_AQED_SMON_TMR 0x2c000068\n+#define DLB2_AQED_SMON_TMR_RST 0x0\n+\n+#define DLB2_AQED_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_AQED_SMON_TMR_TIMER_LOC\t0\n \n #define DLB2_ATM_QID2CQIDIX_00(x) \\\n \t(0x30080000 + (x) * 0x1000)\n@@ -1061,1467 +1452,2853 @@ union dlb2_aqed_pipe_cfg_arb_weights_tqpri_atm_0 {\n #define DLB2_ATM_QID2CQIDIX(x, y) \\\n \t(DLB2_ATM_QID2CQIDIX_00(x) + 0x80000 * (y))\n #define DLB2_ATM_QID2CQIDIX_NUM 16\n-union dlb2_atm_qid2cqidix_00 {\n-\tstruct {\n-\t\tu32 cq_p0 : 8;\n-\t\tu32 cq_p1 : 8;\n-\t\tu32 cq_p2 : 8;\n-\t\tu32 cq_p3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P0\t0x000000FF\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P1\t0x0000FF00\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P2\t0x00FF0000\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P3\t0xFF000000\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P0_LOC\t0\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P1_LOC\t8\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P2_LOC\t16\n+#define DLB2_ATM_QID2CQIDIX_00_CQ_P3_LOC\t24\n \n #define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN 0x34000004\n #define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc\n-union dlb2_atm_cfg_arb_weights_rdy_bin {\n-\tstruct {\n-\t\tu32 bin0 : 8;\n-\t\tu32 bin1 : 8;\n-\t\tu32 bin2 : 8;\n-\t\tu32 bin3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN0\t0x000000FF\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN1\t0x0000FF00\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN2\t0x00FF0000\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN3\t0xFF000000\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN0_LOC\t0\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN1_LOC\t8\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN2_LOC\t16\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN3_LOC\t24\n \n #define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN 0x34000008\n #define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc\n-union dlb2_atm_cfg_arb_weights_sched_bin {\n-\tstruct {\n-\t\tu32 bin0 : 8;\n-\t\tu32 bin1 : 8;\n-\t\tu32 bin2 : 8;\n-\t\tu32 bin3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN0\t0x000000FF\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN1\t0x0000FF00\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN2\t0x00FF0000\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN3\t0xFF000000\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN0_LOC\t0\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN1_LOC\t8\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN2_LOC\t16\n+#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN3_LOC\t24\n+\n+#define DLB2_ATM_SMON_ACTIVITYCNTR0 0x3c000050\n+#define DLB2_ATM_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_ATM_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_ATM_SMON_ACTIVITYCNTR1 0x3c000054\n+#define DLB2_ATM_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_ATM_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_ATM_SMON_COMPARE0 0x3c000058\n+#define DLB2_ATM_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_ATM_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_ATM_SMON_COMPARE1 0x3c00005c\n+#define DLB2_ATM_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_ATM_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_ATM_SMON_CFG0 0x3c000060\n+#define DLB2_ATM_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_ATM_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_ATM_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_ATM_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_ATM_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_ATM_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_ATM_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_ATM_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_ATM_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_ATM_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_ATM_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_ATM_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_ATM_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_ATM_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_ATM_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_ATM_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_ATM_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_ATM_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_ATM_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n+#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_ATM_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_ATM_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_ATM_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_ATM_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_ATM_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_ATM_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n+#define DLB2_ATM_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_ATM_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n+#define DLB2_ATM_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n+#define DLB2_ATM_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_ATM_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n+#define DLB2_ATM_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_ATM_SMON_CFG1 0x3c000064\n+#define DLB2_ATM_SMON_CFG1_RST 0x0\n+\n+#define DLB2_ATM_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_ATM_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_ATM_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_ATM_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_ATM_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_ATM_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_ATM_SMON_MAX_TMR 0x3c000068\n+#define DLB2_ATM_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_ATM_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_ATM_SMON_TMR 0x3c00006c\n+#define DLB2_ATM_SMON_TMR_RST 0x0\n+\n+#define DLB2_ATM_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_ATM_SMON_TMR_TIMER_LOC\t0\n \n #define DLB2_CHP_CFG_DIR_VAS_CRD(x) \\\n \t(0x40000000 + (x) * 0x1000)\n #define DLB2_CHP_CFG_DIR_VAS_CRD_RST 0x0\n-union dlb2_chp_cfg_dir_vas_crd {\n-\tstruct {\n-\t\tu32 count : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_CHP_CFG_DIR_VAS_CRD_COUNT\t0x00003FFF\n+#define DLB2_CHP_CFG_DIR_VAS_CRD_RSVD0\t0xFFFFC000\n+#define DLB2_CHP_CFG_DIR_VAS_CRD_COUNT_LOC\t0\n+#define DLB2_CHP_CFG_DIR_VAS_CRD_RSVD0_LOC\t14\n \n #define DLB2_CHP_CFG_LDB_VAS_CRD(x) \\\n \t(0x40080000 + (x) * 0x1000)\n #define DLB2_CHP_CFG_LDB_VAS_CRD_RST 0x0\n-union dlb2_chp_cfg_ldb_vas_crd {\n-\tstruct {\n-\t\tu32 count : 15;\n-\t\tu32 rsvd0 : 17;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_ORD_QID_SN(x) \\\n+\n+#define DLB2_CHP_CFG_LDB_VAS_CRD_COUNT\t0x00007FFF\n+#define DLB2_CHP_CFG_LDB_VAS_CRD_RSVD0\t0xFFFF8000\n+#define DLB2_CHP_CFG_LDB_VAS_CRD_COUNT_LOC\t0\n+#define DLB2_CHP_CFG_LDB_VAS_CRD_RSVD0_LOC\t15\n+\n+#define DLB2_V2CHP_ORD_QID_SN(x) \\\n \t(0x40100000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_ORD_QID_SN(x) \\\n+\t(0x40080000 + (x) * 0x1000)\n+#define DLB2_CHP_ORD_QID_SN(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_ORD_QID_SN(x) : \\\n+\t DLB2_V2_5CHP_ORD_QID_SN(x))\n #define DLB2_CHP_ORD_QID_SN_RST 0x0\n-union dlb2_chp_ord_qid_sn {\n-\tstruct {\n-\t\tu32 sn : 10;\n-\t\tu32 rsvd0 : 22;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_ORD_QID_SN_MAP(x) \\\n+\n+#define DLB2_CHP_ORD_QID_SN_SN\t0x000003FF\n+#define DLB2_CHP_ORD_QID_SN_RSVD0\t0xFFFFFC00\n+#define DLB2_CHP_ORD_QID_SN_SN_LOC\t\t0\n+#define DLB2_CHP_ORD_QID_SN_RSVD0_LOC\t10\n+\n+#define DLB2_V2CHP_ORD_QID_SN_MAP(x) \\\n \t(0x40180000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_ORD_QID_SN_MAP(x) \\\n+\t(0x40100000 + (x) * 0x1000)\n+#define DLB2_CHP_ORD_QID_SN_MAP(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_ORD_QID_SN_MAP(x) : \\\n+\t DLB2_V2_5CHP_ORD_QID_SN_MAP(x))\n #define DLB2_CHP_ORD_QID_SN_MAP_RST 0x0\n-union dlb2_chp_ord_qid_sn_map {\n-\tstruct {\n-\t\tu32 mode : 3;\n-\t\tu32 slot : 4;\n-\t\tu32 rsvz0 : 1;\n-\t\tu32 grp : 1;\n-\t\tu32 rsvz1 : 1;\n-\t\tu32 rsvd0 : 22;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_SN_CHK_ENBL(x) \\\n+\n+#define DLB2_CHP_ORD_QID_SN_MAP_MODE\t\t0x00000007\n+#define DLB2_CHP_ORD_QID_SN_MAP_SLOT\t\t0x00000078\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ0\t0x00000080\n+#define DLB2_CHP_ORD_QID_SN_MAP_GRP\t\t0x00000100\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ1\t0x00000200\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVD0\t0xFFFFFC00\n+#define DLB2_CHP_ORD_QID_SN_MAP_MODE_LOC\t0\n+#define DLB2_CHP_ORD_QID_SN_MAP_SLOT_LOC\t3\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ0_LOC\t7\n+#define DLB2_CHP_ORD_QID_SN_MAP_GRP_LOC\t8\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ1_LOC\t9\n+#define DLB2_CHP_ORD_QID_SN_MAP_RSVD0_LOC\t10\n+\n+#define DLB2_V2CHP_SN_CHK_ENBL(x) \\\n \t(0x40200000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_SN_CHK_ENBL(x) \\\n+\t(0x40180000 + (x) * 0x1000)\n+#define DLB2_CHP_SN_CHK_ENBL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_SN_CHK_ENBL(x) : \\\n+\t DLB2_V2_5CHP_SN_CHK_ENBL(x))\n #define DLB2_CHP_SN_CHK_ENBL_RST 0x0\n-union dlb2_chp_sn_chk_enbl {\n-\tstruct {\n-\t\tu32 en : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_DEPTH(x) \\\n+\n+#define DLB2_CHP_SN_CHK_ENBL_EN\t0x00000001\n+#define DLB2_CHP_SN_CHK_ENBL_RSVD0\t0xFFFFFFFE\n+#define DLB2_CHP_SN_CHK_ENBL_EN_LOC\t\t0\n+#define DLB2_CHP_SN_CHK_ENBL_RSVD0_LOC\t1\n+\n+#define DLB2_V2CHP_DIR_CQ_DEPTH(x) \\\n \t(0x40280000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_DEPTH(x) \\\n+\t(0x40300000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_DEPTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_DEPTH(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_DEPTH(x))\n #define DLB2_CHP_DIR_CQ_DEPTH_RST 0x0\n-union dlb2_chp_dir_cq_depth {\n-\tstruct {\n-\t\tu32 depth : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_DEPTH_DEPTH\t0x00001FFF\n+#define DLB2_CHP_DIR_CQ_DEPTH_RSVD0\t0xFFFFE000\n+#define DLB2_CHP_DIR_CQ_DEPTH_DEPTH_LOC\t0\n+#define DLB2_CHP_DIR_CQ_DEPTH_RSVD0_LOC\t13\n+\n+#define DLB2_V2CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n \t(0x40300000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0x40380000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_INT_DEPTH_THRSH(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_INT_DEPTH_THRSH(x))\n #define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0\n-union dlb2_chp_dir_cq_int_depth_thrsh {\n-\tstruct {\n-\t\tu32 depth_threshold : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_INT_ENB(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD\t0x00001FFF\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RSVD0\t\t0xFFFFE000\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD_LOC\t0\n+#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RSVD0_LOC\t\t13\n+\n+#define DLB2_V2CHP_DIR_CQ_INT_ENB(x) \\\n \t(0x40380000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_INT_ENB(x) \\\n+\t(0x40400000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_INT_ENB(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_INT_ENB(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_INT_ENB(x))\n #define DLB2_CHP_DIR_CQ_INT_ENB_RST 0x0\n-union dlb2_chp_dir_cq_int_enb {\n-\tstruct {\n-\t\tu32 en_tim : 1;\n-\t\tu32 en_depth : 1;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_INT_ENB_EN_TIM\t0x00000001\n+#define DLB2_CHP_DIR_CQ_INT_ENB_EN_DEPTH\t0x00000002\n+#define DLB2_CHP_DIR_CQ_INT_ENB_RSVD0\t0xFFFFFFFC\n+#define DLB2_CHP_DIR_CQ_INT_ENB_EN_TIM_LOC\t0\n+#define DLB2_CHP_DIR_CQ_INT_ENB_EN_DEPTH_LOC\t1\n+#define DLB2_CHP_DIR_CQ_INT_ENB_RSVD0_LOC\t2\n+\n+#define DLB2_V2CHP_DIR_CQ_TMR_THRSH(x) \\\n \t(0x40480000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_TMR_THRSH(x) \\\n+\t(0x40500000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_TMR_THRSH(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_TMR_THRSH(x))\n #define DLB2_CHP_DIR_CQ_TMR_THRSH_RST 0x1\n-union dlb2_chp_dir_cq_tmr_thrsh {\n-\tstruct {\n-\t\tu32 thrsh_0 : 1;\n-\t\tu32 thrsh_13_1 : 13;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_0\t0x00000001\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_13_1\t0x00003FFE\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_RSVD0\t0xFFFFC000\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_0_LOC\t0\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_13_1_LOC\t1\n+#define DLB2_CHP_DIR_CQ_TMR_THRSH_RSVD0_LOC\t\t14\n+\n+#define DLB2_V2CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n \t(0x40500000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0x40580000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_TKN_DEPTH_SEL(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_TKN_DEPTH_SEL(x))\n #define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0\n-union dlb2_chp_dir_cq_tkn_depth_sel {\n-\tstruct {\n-\t\tu32 token_depth_select : 4;\n-\t\tu32 rsvd0 : 28;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_WD_ENB(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT\t0x0000000F\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RSVD0\t\t\t0xFFFFFFF0\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_LOC\t0\n+#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RSVD0_LOC\t\t4\n+\n+#define DLB2_V2CHP_DIR_CQ_WD_ENB(x) \\\n \t(0x40580000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_WD_ENB(x) \\\n+\t(0x40600000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_WD_ENB(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_WD_ENB(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_WD_ENB(x))\n #define DLB2_CHP_DIR_CQ_WD_ENB_RST 0x0\n-union dlb2_chp_dir_cq_wd_enb {\n-\tstruct {\n-\t\tu32 wd_enable : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_WPTR(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_WD_ENB_WD_ENABLE\t0x00000001\n+#define DLB2_CHP_DIR_CQ_WD_ENB_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_CHP_DIR_CQ_WD_ENB_WD_ENABLE_LOC\t0\n+#define DLB2_CHP_DIR_CQ_WD_ENB_RSVD0_LOC\t1\n+\n+#define DLB2_V2CHP_DIR_CQ_WPTR(x) \\\n \t(0x40600000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ_WPTR(x) \\\n+\t(0x40680000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ_WPTR(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_WPTR(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ_WPTR(x))\n #define DLB2_CHP_DIR_CQ_WPTR_RST 0x0\n-union dlb2_chp_dir_cq_wptr {\n-\tstruct {\n-\t\tu32 write_pointer : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ2VAS(x) \\\n+\n+#define DLB2_CHP_DIR_CQ_WPTR_WRITE_POINTER\t0x00001FFF\n+#define DLB2_CHP_DIR_CQ_WPTR_RSVD0\t\t0xFFFFE000\n+#define DLB2_CHP_DIR_CQ_WPTR_WRITE_POINTER_LOC\t0\n+#define DLB2_CHP_DIR_CQ_WPTR_RSVD0_LOC\t\t13\n+\n+#define DLB2_V2CHP_DIR_CQ2VAS(x) \\\n \t(0x40680000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_DIR_CQ2VAS(x) \\\n+\t(0x40700000 + (x) * 0x1000)\n+#define DLB2_CHP_DIR_CQ2VAS(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ2VAS(x) : \\\n+\t DLB2_V2_5CHP_DIR_CQ2VAS(x))\n #define DLB2_CHP_DIR_CQ2VAS_RST 0x0\n-union dlb2_chp_dir_cq2vas {\n-\tstruct {\n-\t\tu32 cq2vas : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_HIST_LIST_BASE(x) \\\n+\n+#define DLB2_CHP_DIR_CQ2VAS_CQ2VAS\t0x0000001F\n+#define DLB2_CHP_DIR_CQ2VAS_RSVD0\t0xFFFFFFE0\n+#define DLB2_CHP_DIR_CQ2VAS_CQ2VAS_LOC\t0\n+#define DLB2_CHP_DIR_CQ2VAS_RSVD0_LOC\t5\n+\n+#define DLB2_V2CHP_HIST_LIST_BASE(x) \\\n \t(0x40700000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_HIST_LIST_BASE(x) \\\n+\t(0x40780000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_BASE(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_HIST_LIST_BASE(x) : \\\n+\t DLB2_V2_5CHP_HIST_LIST_BASE(x))\n #define DLB2_CHP_HIST_LIST_BASE_RST 0x0\n-union dlb2_chp_hist_list_base {\n-\tstruct {\n-\t\tu32 base : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_HIST_LIST_LIM(x) \\\n+\n+#define DLB2_CHP_HIST_LIST_BASE_BASE\t\t0x00001FFF\n+#define DLB2_CHP_HIST_LIST_BASE_RSVD0\t0xFFFFE000\n+#define DLB2_CHP_HIST_LIST_BASE_BASE_LOC\t0\n+#define DLB2_CHP_HIST_LIST_BASE_RSVD0_LOC\t13\n+\n+#define DLB2_V2CHP_HIST_LIST_LIM(x) \\\n \t(0x40780000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_HIST_LIST_LIM(x) \\\n+\t(0x40800000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_LIM(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_HIST_LIST_LIM(x) : \\\n+\t DLB2_V2_5CHP_HIST_LIST_LIM(x))\n #define DLB2_CHP_HIST_LIST_LIM_RST 0x0\n-union dlb2_chp_hist_list_lim {\n-\tstruct {\n-\t\tu32 limit : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_HIST_LIST_POP_PTR(x) \\\n+\n+#define DLB2_CHP_HIST_LIST_LIM_LIMIT\t0x00001FFF\n+#define DLB2_CHP_HIST_LIST_LIM_RSVD0\t0xFFFFE000\n+#define DLB2_CHP_HIST_LIST_LIM_LIMIT_LOC\t0\n+#define DLB2_CHP_HIST_LIST_LIM_RSVD0_LOC\t13\n+\n+#define DLB2_V2CHP_HIST_LIST_POP_PTR(x) \\\n \t(0x40800000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_HIST_LIST_POP_PTR(x) \\\n+\t(0x40880000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_POP_PTR(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_HIST_LIST_POP_PTR(x) : \\\n+\t DLB2_V2_5CHP_HIST_LIST_POP_PTR(x))\n #define DLB2_CHP_HIST_LIST_POP_PTR_RST 0x0\n-union dlb2_chp_hist_list_pop_ptr {\n-\tstruct {\n-\t\tu32 pop_ptr : 13;\n-\t\tu32 generation : 1;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR(x) \\\n+\n+#define DLB2_CHP_HIST_LIST_POP_PTR_POP_PTR\t\t0x00001FFF\n+#define DLB2_CHP_HIST_LIST_POP_PTR_GENERATION\t0x00002000\n+#define DLB2_CHP_HIST_LIST_POP_PTR_RSVD0\t\t0xFFFFC000\n+#define DLB2_CHP_HIST_LIST_POP_PTR_POP_PTR_LOC\t0\n+#define DLB2_CHP_HIST_LIST_POP_PTR_GENERATION_LOC\t13\n+#define DLB2_CHP_HIST_LIST_POP_PTR_RSVD0_LOC\t\t14\n+\n+#define DLB2_V2CHP_HIST_LIST_PUSH_PTR(x) \\\n \t(0x40880000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_HIST_LIST_PUSH_PTR(x) \\\n+\t(0x40900000 + (x) * 0x1000)\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_HIST_LIST_PUSH_PTR(x) : \\\n+\t DLB2_V2_5CHP_HIST_LIST_PUSH_PTR(x))\n #define DLB2_CHP_HIST_LIST_PUSH_PTR_RST 0x0\n-union dlb2_chp_hist_list_push_ptr {\n-\tstruct {\n-\t\tu32 push_ptr : 13;\n-\t\tu32 generation : 1;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_DEPTH(x) \\\n+\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_PUSH_PTR\t\t0x00001FFF\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_GENERATION\t0x00002000\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_RSVD0\t\t0xFFFFC000\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_PUSH_PTR_LOC\t0\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_GENERATION_LOC\t13\n+#define DLB2_CHP_HIST_LIST_PUSH_PTR_RSVD0_LOC\t14\n+\n+#define DLB2_V2CHP_LDB_CQ_DEPTH(x) \\\n \t(0x40900000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_DEPTH(x) \\\n+\t(0x40a80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_DEPTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_DEPTH(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_DEPTH(x))\n #define DLB2_CHP_LDB_CQ_DEPTH_RST 0x0\n-union dlb2_chp_ldb_cq_depth {\n-\tstruct {\n-\t\tu32 depth : 11;\n-\t\tu32 rsvd0 : 21;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_DEPTH_DEPTH\t0x000007FF\n+#define DLB2_CHP_LDB_CQ_DEPTH_RSVD0\t0xFFFFF800\n+#define DLB2_CHP_LDB_CQ_DEPTH_DEPTH_LOC\t0\n+#define DLB2_CHP_LDB_CQ_DEPTH_RSVD0_LOC\t11\n+\n+#define DLB2_V2CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n \t(0x40980000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n+\t(0x40b00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_INT_DEPTH_THRSH(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_INT_DEPTH_THRSH(x))\n #define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0\n-union dlb2_chp_ldb_cq_int_depth_thrsh {\n-\tstruct {\n-\t\tu32 depth_threshold : 11;\n-\t\tu32 rsvd0 : 21;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_INT_ENB(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD\t0x000007FF\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RSVD0\t\t0xFFFFF800\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD_LOC\t0\n+#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RSVD0_LOC\t\t11\n+\n+#define DLB2_V2CHP_LDB_CQ_INT_ENB(x) \\\n \t(0x40a00000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_INT_ENB(x) \\\n+\t(0x40b80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_INT_ENB(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_INT_ENB(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_INT_ENB(x))\n #define DLB2_CHP_LDB_CQ_INT_ENB_RST 0x0\n-union dlb2_chp_ldb_cq_int_enb {\n-\tstruct {\n-\t\tu32 en_tim : 1;\n-\t\tu32 en_depth : 1;\n-\t\tu32 rsvd0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_INT_ENB_EN_TIM\t0x00000001\n+#define DLB2_CHP_LDB_CQ_INT_ENB_EN_DEPTH\t0x00000002\n+#define DLB2_CHP_LDB_CQ_INT_ENB_RSVD0\t0xFFFFFFFC\n+#define DLB2_CHP_LDB_CQ_INT_ENB_EN_TIM_LOC\t0\n+#define DLB2_CHP_LDB_CQ_INT_ENB_EN_DEPTH_LOC\t1\n+#define DLB2_CHP_LDB_CQ_INT_ENB_RSVD0_LOC\t2\n+\n+#define DLB2_V2CHP_LDB_CQ_TMR_THRSH(x) \\\n \t(0x40b00000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_TMR_THRSH(x) \\\n+\t(0x40c80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_TMR_THRSH(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_TMR_THRSH(x))\n #define DLB2_CHP_LDB_CQ_TMR_THRSH_RST 0x1\n-union dlb2_chp_ldb_cq_tmr_thrsh {\n-\tstruct {\n-\t\tu32 thrsh_0 : 1;\n-\t\tu32 thrsh_13_1 : 13;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_0\t0x00000001\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_13_1\t0x00003FFE\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_RSVD0\t0xFFFFC000\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_0_LOC\t0\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_13_1_LOC\t1\n+#define DLB2_CHP_LDB_CQ_TMR_THRSH_RSVD0_LOC\t\t14\n+\n+#define DLB2_V2CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n \t(0x40b80000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n+\t(0x40d00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_TKN_DEPTH_SEL(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_TKN_DEPTH_SEL(x))\n #define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0\n-union dlb2_chp_ldb_cq_tkn_depth_sel {\n-\tstruct {\n-\t\tu32 token_depth_select : 4;\n-\t\tu32 rsvd0 : 28;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_WD_ENB(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT\t0x0000000F\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RSVD0\t\t\t0xFFFFFFF0\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_LOC\t0\n+#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RSVD0_LOC\t\t4\n+\n+#define DLB2_V2CHP_LDB_CQ_WD_ENB(x) \\\n \t(0x40c00000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_WD_ENB(x) \\\n+\t(0x40d80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_WD_ENB(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_WD_ENB(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_WD_ENB(x))\n #define DLB2_CHP_LDB_CQ_WD_ENB_RST 0x0\n-union dlb2_chp_ldb_cq_wd_enb {\n-\tstruct {\n-\t\tu32 wd_enable : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_WPTR(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_WD_ENB_WD_ENABLE\t0x00000001\n+#define DLB2_CHP_LDB_CQ_WD_ENB_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_CHP_LDB_CQ_WD_ENB_WD_ENABLE_LOC\t0\n+#define DLB2_CHP_LDB_CQ_WD_ENB_RSVD0_LOC\t1\n+\n+#define DLB2_V2CHP_LDB_CQ_WPTR(x) \\\n \t(0x40c80000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ_WPTR(x) \\\n+\t(0x40e00000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ_WPTR(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_WPTR(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ_WPTR(x))\n #define DLB2_CHP_LDB_CQ_WPTR_RST 0x0\n-union dlb2_chp_ldb_cq_wptr {\n-\tstruct {\n-\t\tu32 write_pointer : 11;\n-\t\tu32 rsvd0 : 21;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ2VAS(x) \\\n+\n+#define DLB2_CHP_LDB_CQ_WPTR_WRITE_POINTER\t0x000007FF\n+#define DLB2_CHP_LDB_CQ_WPTR_RSVD0\t\t0xFFFFF800\n+#define DLB2_CHP_LDB_CQ_WPTR_WRITE_POINTER_LOC\t0\n+#define DLB2_CHP_LDB_CQ_WPTR_RSVD0_LOC\t\t11\n+\n+#define DLB2_V2CHP_LDB_CQ2VAS(x) \\\n \t(0x40d00000 + (x) * 0x1000)\n+#define DLB2_V2_5CHP_LDB_CQ2VAS(x) \\\n+\t(0x40e80000 + (x) * 0x1000)\n+#define DLB2_CHP_LDB_CQ2VAS(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ2VAS(x) : \\\n+\t DLB2_V2_5CHP_LDB_CQ2VAS(x))\n #define DLB2_CHP_LDB_CQ2VAS_RST 0x0\n-union dlb2_chp_ldb_cq2vas {\n-\tstruct {\n-\t\tu32 cq2vas : 5;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_CHP_LDB_CQ2VAS_CQ2VAS\t0x0000001F\n+#define DLB2_CHP_LDB_CQ2VAS_RSVD0\t0xFFFFFFE0\n+#define DLB2_CHP_LDB_CQ2VAS_CQ2VAS_LOC\t0\n+#define DLB2_CHP_LDB_CQ2VAS_RSVD0_LOC\t5\n \n #define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008\n #define DLB2_CHP_CFG_CHP_CSR_CTRL_RST 0x180002\n-union dlb2_chp_cfg_chp_csr_ctrl {\n-\tstruct {\n-\t\tu32 int_cor_alarm_dis : 1;\n-\t\tu32 int_cor_synd_dis : 1;\n-\t\tu32 int_uncr_alarm_dis : 1;\n-\t\tu32 int_unc_synd_dis : 1;\n-\t\tu32 int_inf0_alarm_dis : 1;\n-\t\tu32 int_inf0_synd_dis : 1;\n-\t\tu32 int_inf1_alarm_dis : 1;\n-\t\tu32 int_inf1_synd_dis : 1;\n-\t\tu32 int_inf2_alarm_dis : 1;\n-\t\tu32 int_inf2_synd_dis : 1;\n-\t\tu32 int_inf3_alarm_dis : 1;\n-\t\tu32 int_inf3_synd_dis : 1;\n-\t\tu32 int_inf4_alarm_dis : 1;\n-\t\tu32 int_inf4_synd_dis : 1;\n-\t\tu32 int_inf5_alarm_dis : 1;\n-\t\tu32 int_inf5_synd_dis : 1;\n-\t\tu32 dlb_cor_alarm_enable : 1;\n-\t\tu32 cfg_64bytes_qe_ldb_cq_mode : 1;\n-\t\tu32 cfg_64bytes_qe_dir_cq_mode : 1;\n-\t\tu32 pad_write_ldb : 1;\n-\t\tu32 pad_write_dir : 1;\n-\t\tu32 pad_first_write_ldb : 1;\n-\t\tu32 pad_first_write_dir : 1;\n-\t\tu32 rsvz0 : 9;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED0 0x4400005c\n+\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_ALARM_DIS\t\t0x00000001\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_SYND_DIS\t\t0x00000002\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNCR_ALARM_DIS\t\t0x00000004\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNC_SYND_DIS\t\t0x00000008\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_ALARM_DIS\t\t0x00000010\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_SYND_DIS\t\t0x00000020\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_ALARM_DIS\t\t0x00000040\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_SYND_DIS\t\t0x00000080\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_ALARM_DIS\t\t0x00000100\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_SYND_DIS\t\t0x00000200\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_ALARM_DIS\t\t0x00000400\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_SYND_DIS\t\t0x00000800\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_ALARM_DIS\t\t0x00001000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_SYND_DIS\t\t0x00002000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_ALARM_DIS\t\t0x00004000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_SYND_DIS\t\t0x00008000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_DLB_COR_ALARM_ENABLE\t0x00010000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE\t0x00020000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE\t0x00040000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_LDB\t\t0x00080000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_DIR\t\t0x00100000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_LDB\t0x00200000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_DIR\t0x00400000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_RSVZ0\t\t\t0xFF800000\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_ALARM_DIS_LOC\t\t0\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_SYND_DIS_LOC\t\t1\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNCR_ALARM_DIS_LOC\t\t2\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNC_SYND_DIS_LOC\t\t3\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_ALARM_DIS_LOC\t\t4\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_SYND_DIS_LOC\t\t5\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_ALARM_DIS_LOC\t\t6\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_SYND_DIS_LOC\t\t7\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_ALARM_DIS_LOC\t\t8\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_SYND_DIS_LOC\t\t9\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_ALARM_DIS_LOC\t\t10\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_SYND_DIS_LOC\t\t11\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_ALARM_DIS_LOC\t\t12\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_SYND_DIS_LOC\t\t13\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_ALARM_DIS_LOC\t\t14\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_SYND_DIS_LOC\t\t15\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_DLB_COR_ALARM_ENABLE_LOC\t\t16\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE_LOC\t17\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE_LOC\t18\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_LDB_LOC\t\t\t19\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_DIR_LOC\t\t\t20\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_LDB_LOC\t\t21\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_DIR_LOC\t\t22\n+#define DLB2_CHP_CFG_CHP_CSR_CTRL_RSVZ0_LOC\t\t\t\t23\n+\n+#define DLB2_V2CHP_DIR_CQ_INTR_ARMED0 0x4400005c\n+#define DLB2_V2_5CHP_DIR_CQ_INTR_ARMED0 0x4400004c\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_INTR_ARMED0 : \\\n+\t DLB2_V2_5CHP_DIR_CQ_INTR_ARMED0)\n #define DLB2_CHP_DIR_CQ_INTR_ARMED0_RST 0x0\n-union dlb2_chp_dir_cq_intr_armed0 {\n-\tstruct {\n-\t\tu32 armed : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED1 0x44000060\n+\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED0_ARMED\t0xFFFFFFFF\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED0_ARMED_LOC\t0\n+\n+#define DLB2_V2CHP_DIR_CQ_INTR_ARMED1 0x44000060\n+#define DLB2_V2_5CHP_DIR_CQ_INTR_ARMED1 0x44000050\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_DIR_CQ_INTR_ARMED1 : \\\n+\t DLB2_V2_5CHP_DIR_CQ_INTR_ARMED1)\n #define DLB2_CHP_DIR_CQ_INTR_ARMED1_RST 0x0\n-union dlb2_chp_dir_cq_intr_armed1 {\n-\tstruct {\n-\t\tu32 armed : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084\n+\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED1_ARMED\t0xFFFFFFFF\n+#define DLB2_CHP_DIR_CQ_INTR_ARMED1_ARMED_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084\n+#define DLB2_V2_5CHP_CFG_DIR_CQ_TIMER_CTL 0x44000088\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_CQ_TIMER_CTL : \\\n+\t DLB2_V2_5CHP_CFG_DIR_CQ_TIMER_CTL)\n #define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RST 0x0\n-union dlb2_chp_cfg_dir_cq_timer_ctl {\n-\tstruct {\n-\t\tu32 sample_interval : 8;\n-\t\tu32 enb : 1;\n-\t\tu32 rsvz0 : 23;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WDTO_0 0x44000088\n+\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_SAMPLE_INTERVAL\t0x000000FF\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_ENB\t\t\t0x00000100\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RSVZ0\t\t\t0xFFFFFE00\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_SAMPLE_INTERVAL_LOC\t0\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_ENB_LOC\t\t8\n+#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RSVZ0_LOC\t\t9\n+\n+#define DLB2_V2CHP_CFG_DIR_WDTO_0 0x44000088\n+#define DLB2_V2_5CHP_CFG_DIR_WDTO_0 0x4400008c\n+#define DLB2_CHP_CFG_DIR_WDTO_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WDTO_0 : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WDTO_0)\n #define DLB2_CHP_CFG_DIR_WDTO_0_RST 0x0\n-union dlb2_chp_cfg_dir_wdto_0 {\n-\tstruct {\n-\t\tu32 wdto : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WDTO_1 0x4400008c\n+\n+#define DLB2_CHP_CFG_DIR_WDTO_0_WDTO\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_DIR_WDTO_0_WDTO_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_DIR_WDTO_1 0x4400008c\n+#define DLB2_V2_5CHP_CFG_DIR_WDTO_1 0x44000090\n+#define DLB2_CHP_CFG_DIR_WDTO_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WDTO_1 : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WDTO_1)\n #define DLB2_CHP_CFG_DIR_WDTO_1_RST 0x0\n-union dlb2_chp_cfg_dir_wdto_1 {\n-\tstruct {\n-\t\tu32 wdto : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE0 0x44000098\n+\n+#define DLB2_CHP_CFG_DIR_WDTO_1_WDTO\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_DIR_WDTO_1_WDTO_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_DIR_WD_DISABLE0 0x44000098\n+#define DLB2_V2_5CHP_CFG_DIR_WD_DISABLE0 0x440000a4\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WD_DISABLE0 : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WD_DISABLE0)\n #define DLB2_CHP_CFG_DIR_WD_DISABLE0_RST 0xffffffff\n-union dlb2_chp_cfg_dir_wd_disable0 {\n-\tstruct {\n-\t\tu32 wd_disable : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE1 0x4400009c\n+\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE0_WD_DISABLE\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE0_WD_DISABLE_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_DIR_WD_DISABLE1 0x4400009c\n+#define DLB2_V2_5CHP_CFG_DIR_WD_DISABLE1 0x440000a8\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WD_DISABLE1 : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WD_DISABLE1)\n #define DLB2_CHP_CFG_DIR_WD_DISABLE1_RST 0xffffffff\n-union dlb2_chp_cfg_dir_wd_disable1 {\n-\tstruct {\n-\t\tu32 wd_disable : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0\n+\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE1_WD_DISABLE\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_DIR_WD_DISABLE1_WD_DISABLE_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0\n+#define DLB2_V2_5CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000b0\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WD_ENB_INTERVAL : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WD_ENB_INTERVAL)\n #define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RST 0x0\n-union dlb2_chp_cfg_dir_wd_enb_interval {\n-\tstruct {\n-\t\tu32 sample_interval : 28;\n-\t\tu32 enb : 1;\n-\t\tu32 rsvz0 : 3;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD 0x440000ac\n+\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_SAMPLE_INTERVAL\t0x0FFFFFFF\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_ENB\t\t\t0x10000000\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RSVZ0\t\t0xE0000000\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_SAMPLE_INTERVAL_LOC\t0\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_ENB_LOC\t\t28\n+#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RSVZ0_LOC\t\t29\n+\n+#define DLB2_V2CHP_CFG_DIR_WD_THRESHOLD 0x440000ac\n+#define DLB2_V2_5CHP_CFG_DIR_WD_THRESHOLD 0x440000c0\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_DIR_WD_THRESHOLD : \\\n+\t DLB2_V2_5CHP_CFG_DIR_WD_THRESHOLD)\n #define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RST 0x0\n-union dlb2_chp_cfg_dir_wd_threshold {\n-\tstruct {\n-\t\tu32 wd_threshold : 8;\n-\t\tu32 rsvz0 : 24;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED0 0x440000b0\n+\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_WD_THRESHOLD\t0x000000FF\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RSVZ0\t\t0xFFFFFF00\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_WD_THRESHOLD_LOC\t0\n+#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RSVZ0_LOC\t\t8\n+\n+#define DLB2_V2CHP_LDB_CQ_INTR_ARMED0 0x440000b0\n+#define DLB2_V2_5CHP_LDB_CQ_INTR_ARMED0 0x440000c4\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_INTR_ARMED0 : \\\n+\t DLB2_V2_5CHP_LDB_CQ_INTR_ARMED0)\n #define DLB2_CHP_LDB_CQ_INTR_ARMED0_RST 0x0\n-union dlb2_chp_ldb_cq_intr_armed0 {\n-\tstruct {\n-\t\tu32 armed : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED1 0x440000b4\n+\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED0_ARMED\t0xFFFFFFFF\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED0_ARMED_LOC\t0\n+\n+#define DLB2_V2CHP_LDB_CQ_INTR_ARMED1 0x440000b4\n+#define DLB2_V2_5CHP_LDB_CQ_INTR_ARMED1 0x440000c8\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_LDB_CQ_INTR_ARMED1 : \\\n+\t DLB2_V2_5CHP_LDB_CQ_INTR_ARMED1)\n #define DLB2_CHP_LDB_CQ_INTR_ARMED1_RST 0x0\n-union dlb2_chp_ldb_cq_intr_armed1 {\n-\tstruct {\n-\t\tu32 armed : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8\n+\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED1_ARMED\t0xFFFFFFFF\n+#define DLB2_CHP_LDB_CQ_INTR_ARMED1_ARMED_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8\n+#define DLB2_V2_5CHP_CFG_LDB_CQ_TIMER_CTL 0x440000ec\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_CQ_TIMER_CTL : \\\n+\t DLB2_V2_5CHP_CFG_LDB_CQ_TIMER_CTL)\n #define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RST 0x0\n-union dlb2_chp_cfg_ldb_cq_timer_ctl {\n-\tstruct {\n-\t\tu32 sample_interval : 8;\n-\t\tu32 enb : 1;\n-\t\tu32 rsvz0 : 23;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WDTO_0 0x440000dc\n+\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_SAMPLE_INTERVAL\t0x000000FF\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_ENB\t\t\t0x00000100\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RSVZ0\t\t\t0xFFFFFE00\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_SAMPLE_INTERVAL_LOC\t0\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_ENB_LOC\t\t8\n+#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RSVZ0_LOC\t\t9\n+\n+#define DLB2_V2CHP_CFG_LDB_WDTO_0 0x440000dc\n+#define DLB2_V2_5CHP_CFG_LDB_WDTO_0 0x440000f0\n+#define DLB2_CHP_CFG_LDB_WDTO_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WDTO_0 : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WDTO_0)\n #define DLB2_CHP_CFG_LDB_WDTO_0_RST 0x0\n-union dlb2_chp_cfg_ldb_wdto_0 {\n-\tstruct {\n-\t\tu32 wdto : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WDTO_1 0x440000e0\n+\n+#define DLB2_CHP_CFG_LDB_WDTO_0_WDTO\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_LDB_WDTO_0_WDTO_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_LDB_WDTO_1 0x440000e0\n+#define DLB2_V2_5CHP_CFG_LDB_WDTO_1 0x440000f4\n+#define DLB2_CHP_CFG_LDB_WDTO_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WDTO_1 : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WDTO_1)\n #define DLB2_CHP_CFG_LDB_WDTO_1_RST 0x0\n-union dlb2_chp_cfg_ldb_wdto_1 {\n-\tstruct {\n-\t\tu32 wdto : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE0 0x440000ec\n+\n+#define DLB2_CHP_CFG_LDB_WDTO_1_WDTO\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_LDB_WDTO_1_WDTO_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_LDB_WD_DISABLE0 0x440000ec\n+#define DLB2_V2_5CHP_CFG_LDB_WD_DISABLE0 0x44000100\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WD_DISABLE0 : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WD_DISABLE0)\n #define DLB2_CHP_CFG_LDB_WD_DISABLE0_RST 0xffffffff\n-union dlb2_chp_cfg_ldb_wd_disable0 {\n-\tstruct {\n-\t\tu32 wd_disable : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE1 0x440000f0\n+\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE0_WD_DISABLE\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE0_WD_DISABLE_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_LDB_WD_DISABLE1 0x440000f0\n+#define DLB2_V2_5CHP_CFG_LDB_WD_DISABLE1 0x44000104\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WD_DISABLE1 : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WD_DISABLE1)\n #define DLB2_CHP_CFG_LDB_WD_DISABLE1_RST 0xffffffff\n-union dlb2_chp_cfg_ldb_wd_disable1 {\n-\tstruct {\n-\t\tu32 wd_disable : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4\n+\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE1_WD_DISABLE\t0xFFFFFFFF\n+#define DLB2_CHP_CFG_LDB_WD_DISABLE1_WD_DISABLE_LOC\t0\n+\n+#define DLB2_V2CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4\n+#define DLB2_V2_5CHP_CFG_LDB_WD_ENB_INTERVAL 0x44000108\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WD_ENB_INTERVAL : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WD_ENB_INTERVAL)\n #define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RST 0x0\n-union dlb2_chp_cfg_ldb_wd_enb_interval {\n-\tstruct {\n-\t\tu32 sample_interval : 28;\n-\t\tu32 enb : 1;\n-\t\tu32 rsvz0 : 3;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD 0x44000100\n+\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_SAMPLE_INTERVAL\t0x0FFFFFFF\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_ENB\t\t\t0x10000000\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RSVZ0\t\t0xE0000000\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_SAMPLE_INTERVAL_LOC\t0\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_ENB_LOC\t\t28\n+#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RSVZ0_LOC\t\t29\n+\n+#define DLB2_V2CHP_CFG_LDB_WD_THRESHOLD 0x44000100\n+#define DLB2_V2_5CHP_CFG_LDB_WD_THRESHOLD 0x44000114\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CHP_CFG_LDB_WD_THRESHOLD : \\\n+\t DLB2_V2_5CHP_CFG_LDB_WD_THRESHOLD)\n #define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RST 0x0\n-union dlb2_chp_cfg_ldb_wd_threshold {\n-\tstruct {\n-\t\tu32 wd_threshold : 8;\n-\t\tu32 rsvz0 : 24;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_WD_THRESHOLD\t0x000000FF\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RSVZ0\t\t0xFFFFFF00\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_WD_THRESHOLD_LOC\t0\n+#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RSVZ0_LOC\t\t8\n+\n+#define DLB2_CHP_SMON_COMPARE0 0x4c000000\n+#define DLB2_CHP_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_CHP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_CHP_SMON_COMPARE1 0x4c000004\n+#define DLB2_CHP_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_CHP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_CHP_SMON_CFG0 0x4c000008\n+#define DLB2_CHP_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_CHP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_CHP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_CHP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_CHP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_CHP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_CHP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_CHP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_CHP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_CHP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_CHP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_CHP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_CHP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_CHP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_CHP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_CHP_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_CHP_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_CHP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_CHP_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n+#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_CHP_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_CHP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_CHP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_CHP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_CHP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_CHP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n+#define DLB2_CHP_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_CHP_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n+#define DLB2_CHP_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n+#define DLB2_CHP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_CHP_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n+#define DLB2_CHP_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_CHP_SMON_CFG1 0x4c00000c\n+#define DLB2_CHP_SMON_CFG1_RST 0x0\n+\n+#define DLB2_CHP_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_CHP_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_CHP_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_CHP_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_CHP_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_CHP_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_CHP_SMON_ACTIVITYCNTR0 0x4c000010\n+#define DLB2_CHP_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_CHP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_CHP_SMON_ACTIVITYCNTR1 0x4c000014\n+#define DLB2_CHP_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_CHP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_CHP_SMON_MAX_TMR 0x4c000018\n+#define DLB2_CHP_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_CHP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_CHP_SMON_TMR 0x4c00001c\n+#define DLB2_CHP_SMON_TMR_RST 0x0\n+\n+#define DLB2_CHP_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_CHP_SMON_TMR_TIMER_LOC\t0\n \n #define DLB2_CHP_CTRL_DIAG_02 0x4c000028\n #define DLB2_CHP_CTRL_DIAG_02_RST 0x1555\n-union dlb2_chp_ctrl_diag_02 {\n-\tstruct {\n-\t\tu32 egress_credit_status_empty : 1;\n-\t\tu32 egress_credit_status_afull : 1;\n-\t\tu32 chp_outbound_hcw_pipe_credit_status_empty : 1;\n-\t\tu32 chp_outbound_hcw_pipe_credit_status_afull : 1;\n-\t\tu32 chp_lsp_ap_cmp_pipe_credit_status_empty : 1;\n-\t\tu32 chp_lsp_ap_cmp_pipe_credit_status_afull : 1;\n-\t\tu32 chp_lsp_tok_pipe_credit_status_empty : 1;\n-\t\tu32 chp_lsp_tok_pipe_credit_status_afull : 1;\n-\t\tu32 chp_rop_pipe_credit_status_empty : 1;\n-\t\tu32 chp_rop_pipe_credit_status_afull : 1;\n-\t\tu32 qed_to_cq_pipe_credit_status_empty : 1;\n-\t\tu32 qed_to_cq_pipe_credit_status_afull : 1;\n-\t\tu32 egress_lsp_token_credit_status_empty : 1;\n-\t\tu32 egress_lsp_token_credit_status_afull : 1;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2\t0x00000001\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2\t0x00000002\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2 0x04\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2 0x08\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2 0x0010\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2 0x0020\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2    0x0040\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2    0x0080\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2\t 0x0100\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2\t 0x0200\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2\t0x0400\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2\t0x0800\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2    0x1000\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2    0x2000\n+#define DLB2_CHP_CTRL_DIAG_02_RSVD0_V2\t\t\t\t    0xFFFFC000\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_LOC\t    0\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_LOC\t    1\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_LOC 2\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_LOC 3\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_LOC 4\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_LOC 5\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_LOC    6\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_LOC    7\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_LOC\t  8\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_LOC\t  9\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_LOC\t  10\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_LOC\t  11\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_LOC 12\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_LOC 13\n+#define DLB2_CHP_CTRL_DIAG_02_RSVD0_V2_LOC\t\t\t\t  14\n+\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_5\t     0x00000001\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_5\t     0x00000002\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_5  4\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_5  8\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x10\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_5 0x20\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_5\t0x0040\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_5\t0x0080\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x00000100\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_5 0x00000200\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x0400\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_5 0x0800\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_5 0x1000\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_5 0x2000\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOKEN_QB_STATUS_SIZE_V2_5\t    0x0001C000\n+#define DLB2_CHP_CTRL_DIAG_02_FREELIST_SIZE_V2_5\t\t    0xFFFE0000\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_5_LOC 0\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_5_LOC 1\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC 2\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 3\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC 4\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 5\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC    6\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 7\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC\t    8\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC\t    9\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC   10\n+#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC   11\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_5_LOC 12\n+#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_5_LOC 13\n+#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOKEN_QB_STATUS_SIZE_V2_5_LOC\t    14\n+#define DLB2_CHP_CTRL_DIAG_02_FREELIST_SIZE_V2_5_LOC\t\t\t    17\n \n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0 0x54000000\n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfefcfaf8\n-union dlb2_dp_cfg_arb_weights_tqpri_dir_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI0\t0x000000FF\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI1\t0x0000FF00\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI2\t0x00FF0000\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI3\t0xFF000000\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI0_LOC\t0\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI1_LOC\t8\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI2_LOC\t16\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI3_LOC\t24\n \n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1 0x54000004\n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RST 0x0\n-union dlb2_dp_cfg_arb_weights_tqpri_dir_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RSVZ0\t0xFFFFFFFF\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RSVZ0_LOC\t0\n \n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x54000008\n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n-union dlb2_dp_cfg_arb_weights_tqpri_replay_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0\t0x000000FF\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1\t0x0000FF00\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2\t0x00FF0000\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3\t0xFF000000\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0_LOC\t0\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1_LOC\t8\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2_LOC\t16\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3_LOC\t24\n \n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x5400000c\n #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n-union dlb2_dp_cfg_arb_weights_tqpri_replay_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n+\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0\t0xFFFFFFFF\n+#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0_LOC\t0\n \n #define DLB2_DP_DIR_CSR_CTRL 0x54000010\n #define DLB2_DP_DIR_CSR_CTRL_RST 0x0\n-union dlb2_dp_dir_csr_ctrl {\n-\tstruct {\n-\t\tu32 int_cor_alarm_dis : 1;\n-\t\tu32 int_cor_synd_dis : 1;\n-\t\tu32 int_uncr_alarm_dis : 1;\n-\t\tu32 int_unc_synd_dis : 1;\n-\t\tu32 int_inf0_alarm_dis : 1;\n-\t\tu32 int_inf0_synd_dis : 1;\n-\t\tu32 int_inf1_alarm_dis : 1;\n-\t\tu32 int_inf1_synd_dis : 1;\n-\t\tu32 int_inf2_alarm_dis : 1;\n-\t\tu32 int_inf2_synd_dis : 1;\n-\t\tu32 int_inf3_alarm_dis : 1;\n-\t\tu32 int_inf3_synd_dis : 1;\n-\t\tu32 int_inf4_alarm_dis : 1;\n-\t\tu32 int_inf4_synd_dis : 1;\n-\t\tu32 int_inf5_alarm_dis : 1;\n-\t\tu32 int_inf5_synd_dis : 1;\n-\t\tu32 rsvz0 : 16;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_0 {\n-\tstruct {\n-\t\tu32 pri0 : 8;\n-\t\tu32 pri1 : 8;\n-\t\tu32 pri2 : 8;\n-\t\tu32 pri3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014\n-#define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n-union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_RO_PIPE_GRP_0_SLT_SHFT(x) \\\n+\n+#define DLB2_DP_DIR_CSR_CTRL_INT_COR_ALARM_DIS\t0x00000001\n+#define DLB2_DP_DIR_CSR_CTRL_INT_COR_SYND_DIS\t0x00000002\n+#define DLB2_DP_DIR_CSR_CTRL_INT_UNCR_ALARM_DIS\t0x00000004\n+#define DLB2_DP_DIR_CSR_CTRL_INT_UNC_SYND_DIS\t0x00000008\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_ALARM_DIS\t0x00000010\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_SYND_DIS\t0x00000020\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_ALARM_DIS\t0x00000040\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_SYND_DIS\t0x00000080\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_ALARM_DIS\t0x00000100\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_SYND_DIS\t0x00000200\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_ALARM_DIS\t0x00000400\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_SYND_DIS\t0x00000800\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_ALARM_DIS\t0x00001000\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_SYND_DIS\t0x00002000\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_ALARM_DIS\t0x00004000\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_SYND_DIS\t0x00008000\n+#define DLB2_DP_DIR_CSR_CTRL_RSVZ0\t\t\t0xFFFF0000\n+#define DLB2_DP_DIR_CSR_CTRL_INT_COR_ALARM_DIS_LOC\t0\n+#define DLB2_DP_DIR_CSR_CTRL_INT_COR_SYND_DIS_LOC\t1\n+#define DLB2_DP_DIR_CSR_CTRL_INT_UNCR_ALARM_DIS_LOC\t2\n+#define DLB2_DP_DIR_CSR_CTRL_INT_UNC_SYND_DIS_LOC\t3\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_ALARM_DIS_LOC\t4\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_SYND_DIS_LOC\t5\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_ALARM_DIS_LOC\t6\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_SYND_DIS_LOC\t7\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_ALARM_DIS_LOC\t8\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_SYND_DIS_LOC\t9\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_ALARM_DIS_LOC\t10\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_SYND_DIS_LOC\t11\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_ALARM_DIS_LOC\t12\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_SYND_DIS_LOC\t13\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_ALARM_DIS_LOC\t14\n+#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_SYND_DIS_LOC\t15\n+#define DLB2_DP_DIR_CSR_CTRL_RSVZ0_LOC\t\t16\n+\n+#define DLB2_DP_SMON_ACTIVITYCNTR0 0x5c000058\n+#define DLB2_DP_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_DP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_DP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_DP_SMON_ACTIVITYCNTR1 0x5c00005c\n+#define DLB2_DP_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_DP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_DP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_DP_SMON_COMPARE0 0x5c000060\n+#define DLB2_DP_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_DP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_DP_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_DP_SMON_COMPARE1 0x5c000064\n+#define DLB2_DP_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_DP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_DP_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_DP_SMON_CFG0 0x5c000068\n+#define DLB2_DP_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_DP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_DP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_DP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_DP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_DP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_DP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_DP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_DP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_DP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_DP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_DP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_DP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_DP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_DP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_DP_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_DP_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n+#define DLB2_DP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t1\n+#define DLB2_DP_SMON_CFG0_RSVZ0_LOC\t\t\t2\n+#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_DP_SMON_CFG0_SMON_MODE_LOC\t\t12\n+#define DLB2_DP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t16\n+#define DLB2_DP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_DP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t18\n+#define DLB2_DP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t19\n+#define DLB2_DP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_DP_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n+#define DLB2_DP_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_DP_SMON_CFG0_RSVZ1_LOC\t\t\t23\n+#define DLB2_DP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_DP_SMON_CFG0_RSVZ2_LOC\t\t\t29\n+#define DLB2_DP_SMON_CFG0_VERSION_LOC\t\t30\n+\n+#define DLB2_DP_SMON_CFG1 0x5c00006c\n+#define DLB2_DP_SMON_CFG1_RST 0x0\n+\n+#define DLB2_DP_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_DP_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_DP_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_DP_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_DP_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_DP_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_DP_SMON_MAX_TMR 0x5c000070\n+#define DLB2_DP_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_DP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_DP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_DP_SMON_TMR 0x5c000074\n+#define DLB2_DP_SMON_TMR_RST 0x0\n+\n+#define DLB2_DP_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_DP_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_DQED_SMON_ACTIVITYCNTR0 0x6c000024\n+#define DLB2_DQED_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_DQED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_DQED_SMON_ACTIVITYCNTR1 0x6c000028\n+#define DLB2_DQED_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_DQED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_DQED_SMON_COMPARE0 0x6c00002c\n+#define DLB2_DQED_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_DQED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_DQED_SMON_COMPARE1 0x6c000030\n+#define DLB2_DQED_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_DQED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_DQED_SMON_CFG0 0x6c000034\n+#define DLB2_DQED_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_DQED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_DQED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_DQED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_DQED_SMON_CFG0_SMON_MODE\t\t0x0000F000\n+#define DLB2_DQED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_DQED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_DQED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_DQED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_DQED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_DQED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_DQED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_DQED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_DQED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_DQED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_DQED_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_DQED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_DQED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_DQED_SMON_CFG0_RSVZ0_LOC\t\t\t2\n+#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_DQED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_DQED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_DQED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_DQED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_DQED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_DQED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_DQED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_DQED_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_DQED_SMON_CFG0_RSVZ1_LOC\t\t\t23\n+#define DLB2_DQED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_DQED_SMON_CFG0_RSVZ2_LOC\t\t\t29\n+#define DLB2_DQED_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_DQED_SMON_CFG1 0x6c000038\n+#define DLB2_DQED_SMON_CFG1_RST 0x0\n+\n+#define DLB2_DQED_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_DQED_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_DQED_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_DQED_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_DQED_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_DQED_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_DQED_SMON_MAX_TMR 0x6c00003c\n+#define DLB2_DQED_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_DQED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_DQED_SMON_TMR 0x6c000040\n+#define DLB2_DQED_SMON_TMR_RST 0x0\n+\n+#define DLB2_DQED_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_DQED_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_QED_SMON_ACTIVITYCNTR0 0x7c000024\n+#define DLB2_QED_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_QED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_QED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_QED_SMON_ACTIVITYCNTR1 0x7c000028\n+#define DLB2_QED_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_QED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_QED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_QED_SMON_COMPARE0 0x7c00002c\n+#define DLB2_QED_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_QED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_QED_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_QED_SMON_COMPARE1 0x7c000030\n+#define DLB2_QED_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_QED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_QED_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_QED_SMON_CFG0 0x7c000034\n+#define DLB2_QED_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_QED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_QED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_QED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_QED_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_QED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_QED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_QED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_QED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_QED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_QED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_QED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_QED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_QED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_QED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_QED_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_QED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_QED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_QED_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n+#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_QED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_QED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_QED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_QED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_QED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_QED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n+#define DLB2_QED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_QED_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n+#define DLB2_QED_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n+#define DLB2_QED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_QED_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n+#define DLB2_QED_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_QED_SMON_CFG1 0x7c000038\n+#define DLB2_QED_SMON_CFG1_RST 0x0\n+\n+#define DLB2_QED_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_QED_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_QED_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_QED_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_QED_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_QED_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_QED_SMON_MAX_TMR 0x7c00003c\n+#define DLB2_QED_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_QED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_QED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_QED_SMON_TMR 0x7c000040\n+#define DLB2_QED_SMON_TMR_RST 0x0\n+\n+#define DLB2_QED_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_QED_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x74000000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI0\t0x000000FF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI1\t0x0000FF00\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI2\t0x00FF0000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI3\t0xFF000000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI0_LOC\t0\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI1_LOC\t8\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI2_LOC\t16\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI3_LOC\t24\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x74000004\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RSVZ0\t0xFFFFFFFF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RSVZ0_LOC\t0\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x74000008\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI0\t0x000000FF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI1\t0x0000FF00\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI2\t0x00FF0000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI3\t0xFF000000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI0_LOC\t0\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI1_LOC\t8\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI2_LOC\t16\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI3_LOC\t24\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x7400000c\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RSVZ0\t0xFFFFFFFF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RSVZ0_LOC\t0\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x74000010\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0\t0x000000FF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1\t0x0000FF00\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2\t0x00FF0000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3\t0xFF000000\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0_LOC\t0\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1_LOC\t8\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2_LOC\t16\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3_LOC\t24\n+\n+#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014\n+#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x74000014\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 : \\\n+\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1)\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n+\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0\t0xFFFFFFFF\n+#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0_LOC\t0\n+\n+#define DLB2_NALB_SMON_ACTIVITYCNTR0 0x8c000064\n+#define DLB2_NALB_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_NALB_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_NALB_SMON_ACTIVITYCNTR1 0x8c000068\n+#define DLB2_NALB_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_NALB_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_NALB_SMON_COMPARE0 0x8c00006c\n+#define DLB2_NALB_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_NALB_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_NALB_SMON_COMPARE1 0x8c000070\n+#define DLB2_NALB_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_NALB_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_NALB_SMON_CFG0 0x8c000074\n+#define DLB2_NALB_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_NALB_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_NALB_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_NALB_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_NALB_SMON_CFG0_SMON_MODE\t\t0x0000F000\n+#define DLB2_NALB_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_NALB_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_NALB_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_NALB_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_NALB_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_NALB_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_NALB_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_NALB_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_NALB_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_NALB_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_NALB_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_NALB_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_NALB_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_NALB_SMON_CFG0_RSVZ0_LOC\t\t\t2\n+#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_NALB_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_NALB_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_NALB_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_NALB_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_NALB_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_NALB_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_NALB_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_NALB_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_NALB_SMON_CFG0_RSVZ1_LOC\t\t\t23\n+#define DLB2_NALB_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_NALB_SMON_CFG0_RSVZ2_LOC\t\t\t29\n+#define DLB2_NALB_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_NALB_SMON_CFG1 0x8c000078\n+#define DLB2_NALB_SMON_CFG1_RST 0x0\n+\n+#define DLB2_NALB_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_NALB_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_NALB_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_NALB_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_NALB_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_NALB_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_NALB_SMON_MAX_TMR 0x8c00007c\n+#define DLB2_NALB_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_NALB_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_NALB_SMON_TMR 0x8c000080\n+#define DLB2_NALB_SMON_TMR_RST 0x0\n+\n+#define DLB2_NALB_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_NALB_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_V2RO_GRP_0_SLT_SHFT(x) \\\n \t(0x96000000 + (x) * 0x4)\n-#define DLB2_RO_PIPE_GRP_0_SLT_SHFT_RST 0x0\n-union dlb2_ro_pipe_grp_0_slt_shft {\n-\tstruct {\n-\t\tu32 change : 10;\n-\t\tu32 rsvd0 : 22;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_RO_PIPE_GRP_1_SLT_SHFT(x) \\\n+#define DLB2_V2_5RO_GRP_0_SLT_SHFT(x) \\\n+\t(0x86000000 + (x) * 0x4)\n+#define DLB2_RO_GRP_0_SLT_SHFT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2RO_GRP_0_SLT_SHFT(x) : \\\n+\t DLB2_V2_5RO_GRP_0_SLT_SHFT(x))\n+#define DLB2_RO_GRP_0_SLT_SHFT_RST 0x0\n+\n+#define DLB2_RO_GRP_0_SLT_SHFT_CHANGE\t0x000003FF\n+#define DLB2_RO_GRP_0_SLT_SHFT_RSVD0\t\t0xFFFFFC00\n+#define DLB2_RO_GRP_0_SLT_SHFT_CHANGE_LOC\t0\n+#define DLB2_RO_GRP_0_SLT_SHFT_RSVD0_LOC\t10\n+\n+#define DLB2_V2RO_GRP_1_SLT_SHFT(x) \\\n \t(0x96010000 + (x) * 0x4)\n-#define DLB2_RO_PIPE_GRP_1_SLT_SHFT_RST 0x0\n-union dlb2_ro_pipe_grp_1_slt_shft {\n-\tstruct {\n-\t\tu32 change : 10;\n-\t\tu32 rsvd0 : 22;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_RO_PIPE_GRP_SN_MODE 0x94000000\n-#define DLB2_RO_PIPE_GRP_SN_MODE_RST 0x0\n-union dlb2_ro_pipe_grp_sn_mode {\n-\tstruct {\n-\t\tu32 sn_mode_0 : 3;\n-\t\tu32 rszv0 : 5;\n-\t\tu32 sn_mode_1 : 3;\n-\t\tu32 rszv1 : 21;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0 0x9c000000\n-#define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0_RST 0x0\n-union dlb2_ro_pipe_cfg_ctrl_general_0 {\n-\tstruct {\n-\t\tu32 unit_single_step_mode : 1;\n-\t\tu32 rr_en : 1;\n-\t\tu32 rszv0 : 30;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ2PRIOV(x) \\\n+#define DLB2_V2_5RO_GRP_1_SLT_SHFT(x) \\\n+\t(0x86010000 + (x) * 0x4)\n+#define DLB2_RO_GRP_1_SLT_SHFT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2RO_GRP_1_SLT_SHFT(x) : \\\n+\t DLB2_V2_5RO_GRP_1_SLT_SHFT(x))\n+#define DLB2_RO_GRP_1_SLT_SHFT_RST 0x0\n+\n+#define DLB2_RO_GRP_1_SLT_SHFT_CHANGE\t0x000003FF\n+#define DLB2_RO_GRP_1_SLT_SHFT_RSVD0\t\t0xFFFFFC00\n+#define DLB2_RO_GRP_1_SLT_SHFT_CHANGE_LOC\t0\n+#define DLB2_RO_GRP_1_SLT_SHFT_RSVD0_LOC\t10\n+\n+#define DLB2_V2RO_GRP_SN_MODE 0x94000000\n+#define DLB2_V2_5RO_GRP_SN_MODE 0x84000000\n+#define DLB2_RO_GRP_SN_MODE(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2RO_GRP_SN_MODE : \\\n+\t DLB2_V2_5RO_GRP_SN_MODE)\n+#define DLB2_RO_GRP_SN_MODE_RST 0x0\n+\n+#define DLB2_RO_GRP_SN_MODE_SN_MODE_0\t0x00000007\n+#define DLB2_RO_GRP_SN_MODE_RSZV0\t\t0x000000F8\n+#define DLB2_RO_GRP_SN_MODE_SN_MODE_1\t0x00000700\n+#define DLB2_RO_GRP_SN_MODE_RSZV1\t\t0xFFFFF800\n+#define DLB2_RO_GRP_SN_MODE_SN_MODE_0_LOC\t0\n+#define DLB2_RO_GRP_SN_MODE_RSZV0_LOC\t3\n+#define DLB2_RO_GRP_SN_MODE_SN_MODE_1_LOC\t8\n+#define DLB2_RO_GRP_SN_MODE_RSZV1_LOC\t11\n+\n+#define DLB2_V2RO_CFG_CTRL_GENERAL_0 0x9c000000\n+#define DLB2_V2_5RO_CFG_CTRL_GENERAL_0 0x8c000000\n+#define DLB2_RO_CFG_CTRL_GENERAL_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2RO_CFG_CTRL_GENERAL_0 : \\\n+\t DLB2_V2_5RO_CFG_CTRL_GENERAL_0)\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_RST 0x0\n+\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_UNIT_SINGLE_STEP_MODE\t0x00000001\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_RR_EN\t\t\t0x00000002\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_RSZV0\t\t\t0xFFFFFFFC\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_UNIT_SINGLE_STEP_MODE_LOC\t0\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_RR_EN_LOC\t\t\t1\n+#define DLB2_RO_CFG_CTRL_GENERAL_0_RSZV0_LOC\t\t\t2\n+\n+#define DLB2_RO_SMON_ACTIVITYCNTR0 0x9c000030\n+#define DLB2_RO_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_RO_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_RO_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_RO_SMON_ACTIVITYCNTR1 0x9c000034\n+#define DLB2_RO_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_RO_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_RO_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_RO_SMON_COMPARE0 0x9c000038\n+#define DLB2_RO_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_RO_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_RO_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_RO_SMON_COMPARE1 0x9c00003c\n+#define DLB2_RO_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_RO_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_RO_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_RO_SMON_CFG0 0x9c000040\n+#define DLB2_RO_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_RO_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_RO_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_RO_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_RO_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_RO_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_RO_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_RO_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_RO_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_RO_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_RO_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_RO_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_RO_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_RO_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_RO_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_RO_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_RO_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n+#define DLB2_RO_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t1\n+#define DLB2_RO_SMON_CFG0_RSVZ0_LOC\t\t\t2\n+#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_RO_SMON_CFG0_SMON_MODE_LOC\t\t12\n+#define DLB2_RO_SMON_CFG0_STOPCOUNTEROVFL_LOC\t16\n+#define DLB2_RO_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_RO_SMON_CFG0_STATCOUNTER0OVFL_LOC\t18\n+#define DLB2_RO_SMON_CFG0_STATCOUNTER1OVFL_LOC\t19\n+#define DLB2_RO_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n+#define DLB2_RO_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n+#define DLB2_RO_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n+#define DLB2_RO_SMON_CFG0_RSVZ1_LOC\t\t\t23\n+#define DLB2_RO_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_RO_SMON_CFG0_RSVZ2_LOC\t\t\t29\n+#define DLB2_RO_SMON_CFG0_VERSION_LOC\t\t30\n+\n+#define DLB2_RO_SMON_CFG1 0x9c000044\n+#define DLB2_RO_SMON_CFG1_RST 0x0\n+\n+#define DLB2_RO_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_RO_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_RO_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_RO_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_RO_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_RO_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_RO_SMON_MAX_TMR 0x9c000048\n+#define DLB2_RO_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_RO_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_RO_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_RO_SMON_TMR 0x9c00004c\n+#define DLB2_RO_SMON_TMR_RST 0x0\n+\n+#define DLB2_RO_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_RO_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_V2LSP_CQ2PRIOV(x) \\\n \t(0xa0000000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ2PRIOV(x) \\\n+\t(0x90000000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2PRIOV(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ2PRIOV(x) : \\\n+\t DLB2_V2_5LSP_CQ2PRIOV(x))\n #define DLB2_LSP_CQ2PRIOV_RST 0x0\n-union dlb2_lsp_cq2priov {\n-\tstruct {\n-\t\tu32 prio : 24;\n-\t\tu32 v : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ2QID0(x) \\\n+\n+#define DLB2_LSP_CQ2PRIOV_PRIO\t0x00FFFFFF\n+#define DLB2_LSP_CQ2PRIOV_V\t\t0xFF000000\n+#define DLB2_LSP_CQ2PRIOV_PRIO_LOC\t0\n+#define DLB2_LSP_CQ2PRIOV_V_LOC\t24\n+\n+#define DLB2_V2LSP_CQ2QID0(x) \\\n \t(0xa0080000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ2QID0(x) \\\n+\t(0x90080000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2QID0(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ2QID0(x) : \\\n+\t DLB2_V2_5LSP_CQ2QID0(x))\n #define DLB2_LSP_CQ2QID0_RST 0x0\n-union dlb2_lsp_cq2qid0 {\n-\tstruct {\n-\t\tu32 qid_p0 : 7;\n-\t\tu32 rsvd3 : 1;\n-\t\tu32 qid_p1 : 7;\n-\t\tu32 rsvd2 : 1;\n-\t\tu32 qid_p2 : 7;\n-\t\tu32 rsvd1 : 1;\n-\t\tu32 qid_p3 : 7;\n-\t\tu32 rsvd0 : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ2QID1(x) \\\n+\n+#define DLB2_LSP_CQ2QID0_QID_P0\t0x0000007F\n+#define DLB2_LSP_CQ2QID0_RSVD3\t0x00000080\n+#define DLB2_LSP_CQ2QID0_QID_P1\t0x00007F00\n+#define DLB2_LSP_CQ2QID0_RSVD2\t0x00008000\n+#define DLB2_LSP_CQ2QID0_QID_P2\t0x007F0000\n+#define DLB2_LSP_CQ2QID0_RSVD1\t0x00800000\n+#define DLB2_LSP_CQ2QID0_QID_P3\t0x7F000000\n+#define DLB2_LSP_CQ2QID0_RSVD0\t0x80000000\n+#define DLB2_LSP_CQ2QID0_QID_P0_LOC\t0\n+#define DLB2_LSP_CQ2QID0_RSVD3_LOC\t7\n+#define DLB2_LSP_CQ2QID0_QID_P1_LOC\t8\n+#define DLB2_LSP_CQ2QID0_RSVD2_LOC\t15\n+#define DLB2_LSP_CQ2QID0_QID_P2_LOC\t16\n+#define DLB2_LSP_CQ2QID0_RSVD1_LOC\t23\n+#define DLB2_LSP_CQ2QID0_QID_P3_LOC\t24\n+#define DLB2_LSP_CQ2QID0_RSVD0_LOC\t31\n+\n+#define DLB2_V2LSP_CQ2QID1(x) \\\n \t(0xa0100000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ2QID1(x) \\\n+\t(0x90100000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ2QID1(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ2QID1(x) : \\\n+\t DLB2_V2_5LSP_CQ2QID1(x))\n #define DLB2_LSP_CQ2QID1_RST 0x0\n-union dlb2_lsp_cq2qid1 {\n-\tstruct {\n-\t\tu32 qid_p4 : 7;\n-\t\tu32 rsvd3 : 1;\n-\t\tu32 qid_p5 : 7;\n-\t\tu32 rsvd2 : 1;\n-\t\tu32 qid_p6 : 7;\n-\t\tu32 rsvd1 : 1;\n-\t\tu32 qid_p7 : 7;\n-\t\tu32 rsvd0 : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_DIR_DSBL(x) \\\n+\n+#define DLB2_LSP_CQ2QID1_QID_P4\t0x0000007F\n+#define DLB2_LSP_CQ2QID1_RSVD3\t0x00000080\n+#define DLB2_LSP_CQ2QID1_QID_P5\t0x00007F00\n+#define DLB2_LSP_CQ2QID1_RSVD2\t0x00008000\n+#define DLB2_LSP_CQ2QID1_QID_P6\t0x007F0000\n+#define DLB2_LSP_CQ2QID1_RSVD1\t0x00800000\n+#define DLB2_LSP_CQ2QID1_QID_P7\t0x7F000000\n+#define DLB2_LSP_CQ2QID1_RSVD0\t0x80000000\n+#define DLB2_LSP_CQ2QID1_QID_P4_LOC\t0\n+#define DLB2_LSP_CQ2QID1_RSVD3_LOC\t7\n+#define DLB2_LSP_CQ2QID1_QID_P5_LOC\t8\n+#define DLB2_LSP_CQ2QID1_RSVD2_LOC\t15\n+#define DLB2_LSP_CQ2QID1_QID_P6_LOC\t16\n+#define DLB2_LSP_CQ2QID1_RSVD1_LOC\t23\n+#define DLB2_LSP_CQ2QID1_QID_P7_LOC\t24\n+#define DLB2_LSP_CQ2QID1_RSVD0_LOC\t31\n+\n+#define DLB2_V2LSP_CQ_DIR_DSBL(x) \\\n \t(0xa0180000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_DIR_DSBL(x) \\\n+\t(0x90180000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_DSBL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_DIR_DSBL(x) : \\\n+\t DLB2_V2_5LSP_CQ_DIR_DSBL(x))\n #define DLB2_LSP_CQ_DIR_DSBL_RST 0x1\n-union dlb2_lsp_cq_dir_dsbl {\n-\tstruct {\n-\t\tu32 disabled : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_DIR_TKN_CNT(x) \\\n+\n+#define DLB2_LSP_CQ_DIR_DSBL_DISABLED\t0x00000001\n+#define DLB2_LSP_CQ_DIR_DSBL_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_LSP_CQ_DIR_DSBL_DISABLED_LOC\t0\n+#define DLB2_LSP_CQ_DIR_DSBL_RSVD0_LOC\t1\n+\n+#define DLB2_V2LSP_CQ_DIR_TKN_CNT(x) \\\n \t(0xa0200000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_DIR_TKN_CNT(x) \\\n+\t(0x90200000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TKN_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_DIR_TKN_CNT(x) : \\\n+\t DLB2_V2_5LSP_CQ_DIR_TKN_CNT(x))\n #define DLB2_LSP_CQ_DIR_TKN_CNT_RST 0x0\n-union dlb2_lsp_cq_dir_tkn_cnt {\n-\tstruct {\n-\t\tu32 count : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n+\n+#define DLB2_LSP_CQ_DIR_TKN_CNT_COUNT\t0x00001FFF\n+#define DLB2_LSP_CQ_DIR_TKN_CNT_RSVD0\t0xFFFFE000\n+#define DLB2_LSP_CQ_DIR_TKN_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_CQ_DIR_TKN_CNT_RSVD0_LOC\t13\n+\n+#define DLB2_V2LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n \t(0xa0280000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n+\t(0x90280000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) : \\\n+\t DLB2_V2_5LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x))\n #define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0\n-union dlb2_lsp_cq_dir_tkn_depth_sel_dsi {\n-\tstruct {\n-\t\tu32 token_depth_select : 4;\n-\t\tu32 disable_wb_opt : 1;\n-\t\tu32 ignore_depth : 1;\n-\t\tu32 rsvd0 : 26;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n+\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2\t0x0000000F\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2\t0x00000010\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_IGNORE_DEPTH_V2\t0x00000020\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2\t\t0xFFFFFFC0\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_LOC\t0\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_LOC\t4\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_IGNORE_DEPTH_V2_LOC\t5\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_LOC\t\t6\n+\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_5 0x0000000F\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_5\t0x00000010\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_5\t\t0xFFFFFFE0\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_5_LOC\t0\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_5_LOC\t4\n+#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_5_LOC\t\t5\n+\n+#define DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n \t(0xa0300000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n+\t(0x90300000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTL(x) : \\\n+\t DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTL(x))\n #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0\n-union dlb2_lsp_cq_dir_tot_sch_cntl {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n+\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n \t(0xa0380000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n+\t(0x90380000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTH(x) : \\\n+\t DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTH(x))\n #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0\n-union dlb2_lsp_cq_dir_tot_sch_cnth {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_DSBL(x) \\\n+\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_CQ_LDB_DSBL(x) \\\n \t(0xa0400000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_DSBL(x) \\\n+\t(0x90400000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_DSBL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_DSBL(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_DSBL(x))\n #define DLB2_LSP_CQ_LDB_DSBL_RST 0x1\n-union dlb2_lsp_cq_ldb_dsbl {\n-\tstruct {\n-\t\tu32 disabled : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_INFL_CNT(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_DSBL_DISABLED\t0x00000001\n+#define DLB2_LSP_CQ_LDB_DSBL_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_LSP_CQ_LDB_DSBL_DISABLED_LOC\t0\n+#define DLB2_LSP_CQ_LDB_DSBL_RSVD0_LOC\t1\n+\n+#define DLB2_V2LSP_CQ_LDB_INFL_CNT(x) \\\n \t(0xa0480000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_INFL_CNT(x) \\\n+\t(0x90480000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_INFL_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_INFL_CNT(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_INFL_CNT(x))\n #define DLB2_LSP_CQ_LDB_INFL_CNT_RST 0x0\n-union dlb2_lsp_cq_ldb_infl_cnt {\n-\tstruct {\n-\t\tu32 count : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_INFL_LIM(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_INFL_CNT_COUNT\t0x00000FFF\n+#define DLB2_LSP_CQ_LDB_INFL_CNT_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_CQ_LDB_INFL_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_CQ_LDB_INFL_CNT_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_CQ_LDB_INFL_LIM(x) \\\n \t(0xa0500000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_INFL_LIM(x) \\\n+\t(0x90500000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_INFL_LIM(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_INFL_LIM(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_INFL_LIM(x))\n #define DLB2_LSP_CQ_LDB_INFL_LIM_RST 0x0\n-union dlb2_lsp_cq_ldb_infl_lim {\n-\tstruct {\n-\t\tu32 limit : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_TKN_CNT(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT\t0x00000FFF\n+#define DLB2_LSP_CQ_LDB_INFL_LIM_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT_LOC\t0\n+#define DLB2_LSP_CQ_LDB_INFL_LIM_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_CQ_LDB_TKN_CNT(x) \\\n \t(0xa0580000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_TKN_CNT(x) \\\n+\t(0x90600000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TKN_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_TKN_CNT(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_TKN_CNT(x))\n #define DLB2_LSP_CQ_LDB_TKN_CNT_RST 0x0\n-union dlb2_lsp_cq_ldb_tkn_cnt {\n-\tstruct {\n-\t\tu32 token_count : 11;\n-\t\tu32 rsvd0 : 21;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_TKN_CNT_TOKEN_COUNT\t0x000007FF\n+#define DLB2_LSP_CQ_LDB_TKN_CNT_RSVD0\t0xFFFFF800\n+#define DLB2_LSP_CQ_LDB_TKN_CNT_TOKEN_COUNT_LOC\t0\n+#define DLB2_LSP_CQ_LDB_TKN_CNT_RSVD0_LOC\t\t11\n+\n+#define DLB2_V2LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n \t(0xa0600000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n+\t(0x90680000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_TKN_DEPTH_SEL(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_TKN_DEPTH_SEL(x))\n #define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0\n-union dlb2_lsp_cq_ldb_tkn_depth_sel {\n-\tstruct {\n-\t\tu32 token_depth_select : 4;\n-\t\tu32 ignore_depth : 1;\n-\t\tu32 rsvd0 : 27;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2\t0x0000000F\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_IGNORE_DEPTH_V2\t0x00000010\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2\t\t0xFFFFFFE0\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_LOC\t0\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_IGNORE_DEPTH_V2_LOC\t\t4\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_LOC\t\t\t5\n+\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_5\t0x0000000F\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_5\t\t0xFFFFFFF0\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_5_LOC\t0\n+#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_5_LOC\t\t\t4\n+\n+#define DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n \t(0xa0680000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n+\t(0x90700000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTL(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTL(x))\n #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0\n-union dlb2_lsp_cq_ldb_tot_sch_cntl {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n \t(0xa0700000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n+\t(0x90780000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTH(x) : \\\n+\t DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTH(x))\n #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0\n-union dlb2_lsp_cq_ldb_tot_sch_cnth {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH(x) \\\n+\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_DIR_MAX_DEPTH(x) \\\n \t(0xa0780000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_DIR_MAX_DEPTH(x) \\\n+\t(0x90800000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_DIR_MAX_DEPTH(x) : \\\n+\t DLB2_V2_5LSP_QID_DIR_MAX_DEPTH(x))\n #define DLB2_LSP_QID_DIR_MAX_DEPTH_RST 0x0\n-union dlb2_lsp_qid_dir_max_depth {\n-\tstruct {\n-\t\tu32 depth : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n+\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH_DEPTH\t0x00001FFF\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH_RSVD0\t0xFFFFE000\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH_DEPTH_LOC\t0\n+#define DLB2_LSP_QID_DIR_MAX_DEPTH_RSVD0_LOC\t13\n+\n+#define DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n \t(0xa0800000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n+\t(0x90880000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTL(x) : \\\n+\t DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTL(x))\n #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST 0x0\n-union dlb2_lsp_qid_dir_tot_enq_cntl {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n+\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n \t(0xa0880000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n+\t(0x90900000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTH(x) : \\\n+\t DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTH(x))\n #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST 0x0\n-union dlb2_lsp_qid_dir_tot_enq_cnth {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT(x) \\\n+\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_DIR_ENQUEUE_CNT(x) \\\n \t(0xa0900000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_DIR_ENQUEUE_CNT(x) \\\n+\t(0x90980000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_DIR_ENQUEUE_CNT(x) : \\\n+\t DLB2_V2_5LSP_QID_DIR_ENQUEUE_CNT(x))\n #define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0\n-union dlb2_lsp_qid_dir_enqueue_cnt {\n-\tstruct {\n-\t\tu32 count : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH(x) \\\n+\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_COUNT\t0x00001FFF\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RSVD0\t0xFFFFE000\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RSVD0_LOC\t13\n+\n+#define DLB2_V2LSP_QID_DIR_DEPTH_THRSH(x) \\\n \t(0xa0980000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_DIR_DEPTH_THRSH(x) \\\n+\t(0x90a00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_DIR_DEPTH_THRSH(x) : \\\n+\t DLB2_V2_5LSP_QID_DIR_DEPTH_THRSH(x))\n #define DLB2_LSP_QID_DIR_DEPTH_THRSH_RST 0x0\n-union dlb2_lsp_qid_dir_depth_thrsh {\n-\tstruct {\n-\t\tu32 thresh : 13;\n-\t\tu32 rsvd0 : 19;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT(x) \\\n+\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH_THRESH\t0x00001FFF\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RSVD0\t0xFFFFE000\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH_THRESH_LOC\t0\n+#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RSVD0_LOC\t13\n+\n+#define DLB2_V2LSP_QID_AQED_ACTIVE_CNT(x) \\\n \t(0xa0a00000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_AQED_ACTIVE_CNT(x) \\\n+\t(0x90b80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_AQED_ACTIVE_CNT(x) : \\\n+\t DLB2_V2_5LSP_QID_AQED_ACTIVE_CNT(x))\n #define DLB2_LSP_QID_AQED_ACTIVE_CNT_RST 0x0\n-union dlb2_lsp_qid_aqed_active_cnt {\n-\tstruct {\n-\t\tu32 count : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM(x) \\\n+\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT_COUNT\t0x00000FFF\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_QID_AQED_ACTIVE_LIM(x) \\\n \t(0xa0a80000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_AQED_ACTIVE_LIM(x) \\\n+\t(0x90c00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_AQED_ACTIVE_LIM(x) : \\\n+\t DLB2_V2_5LSP_QID_AQED_ACTIVE_LIM(x))\n #define DLB2_LSP_QID_AQED_ACTIVE_LIM_RST 0x0\n-union dlb2_lsp_qid_aqed_active_lim {\n-\tstruct {\n-\t\tu32 limit : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n+\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM_LIMIT\t0x00000FFF\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM_LIMIT_LOC\t0\n+#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n \t(0xa0b00000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n+\t(0x90c80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTL(x) : \\\n+\t DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTL(x))\n #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST 0x0\n-union dlb2_lsp_qid_atm_tot_enq_cntl {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n+\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n \t(0xa0b80000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n+\t(0x90d00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTH(x) : \\\n+\t DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTH(x))\n #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST 0x0\n-union dlb2_lsp_qid_atm_tot_enq_cnth {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT(x) \\\n-\t(0xa0c00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_ATQ_ENQUEUE_CNT_RST 0x0\n-union dlb2_lsp_qid_atq_enqueue_cnt {\n-\tstruct {\n-\t\tu32 count : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT(x) \\\n+\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_LDB_ENQUEUE_CNT(x) \\\n \t(0xa0c80000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_LDB_ENQUEUE_CNT(x) \\\n+\t(0x90e00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_LDB_ENQUEUE_CNT(x) : \\\n+\t DLB2_V2_5LSP_QID_LDB_ENQUEUE_CNT(x))\n #define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0\n-union dlb2_lsp_qid_ldb_enqueue_cnt {\n-\tstruct {\n-\t\tu32 count : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_LDB_INFL_CNT(x) \\\n+\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_COUNT\t0x00003FFF\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RSVD0\t0xFFFFC000\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RSVD0_LOC\t14\n+\n+#define DLB2_V2LSP_QID_LDB_INFL_CNT(x) \\\n \t(0xa0d00000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_LDB_INFL_CNT(x) \\\n+\t(0x90e80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_INFL_CNT(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_LDB_INFL_CNT(x) : \\\n+\t DLB2_V2_5LSP_QID_LDB_INFL_CNT(x))\n #define DLB2_LSP_QID_LDB_INFL_CNT_RST 0x0\n-union dlb2_lsp_qid_ldb_infl_cnt {\n-\tstruct {\n-\t\tu32 count : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_LDB_INFL_LIM(x) \\\n+\n+#define DLB2_LSP_QID_LDB_INFL_CNT_COUNT\t0x00000FFF\n+#define DLB2_LSP_QID_LDB_INFL_CNT_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_QID_LDB_INFL_CNT_COUNT_LOC\t0\n+#define DLB2_LSP_QID_LDB_INFL_CNT_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_QID_LDB_INFL_LIM(x) \\\n \t(0xa0d80000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_LDB_INFL_LIM(x) \\\n+\t(0x90f00000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_LDB_INFL_LIM(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_LDB_INFL_LIM(x) : \\\n+\t DLB2_V2_5LSP_QID_LDB_INFL_LIM(x))\n #define DLB2_LSP_QID_LDB_INFL_LIM_RST 0x0\n-union dlb2_lsp_qid_ldb_infl_lim {\n-\tstruct {\n-\t\tu32 limit : 12;\n-\t\tu32 rsvd0 : 20;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID2CQIDIX_00(x) \\\n+\n+#define DLB2_LSP_QID_LDB_INFL_LIM_LIMIT\t0x00000FFF\n+#define DLB2_LSP_QID_LDB_INFL_LIM_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_QID_LDB_INFL_LIM_LIMIT_LOC\t0\n+#define DLB2_LSP_QID_LDB_INFL_LIM_RSVD0_LOC\t12\n+\n+#define DLB2_V2LSP_QID2CQIDIX_00(x) \\\n \t(0xa0e00000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID2CQIDIX_00(x) \\\n+\t(0x90f80000 + (x) * 0x1000)\n+#define DLB2_LSP_QID2CQIDIX_00(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID2CQIDIX_00(x) : \\\n+\t DLB2_V2_5LSP_QID2CQIDIX_00(x))\n #define DLB2_LSP_QID2CQIDIX_00_RST 0x0\n-#define DLB2_LSP_QID2CQIDIX(x, y) \\\n-\t(DLB2_LSP_QID2CQIDIX_00(x) + 0x80000 * (y))\n+#define DLB2_LSP_QID2CQIDIX(ver, x, y) \\\n+\t(DLB2_LSP_QID2CQIDIX_00(ver, x) + 0x80000 * (y))\n #define DLB2_LSP_QID2CQIDIX_NUM 16\n-union dlb2_lsp_qid2cqidix_00 {\n-\tstruct {\n-\t\tu32 cq_p0 : 8;\n-\t\tu32 cq_p1 : 8;\n-\t\tu32 cq_p2 : 8;\n-\t\tu32 cq_p3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID2CQIDIX2_00(x) \\\n+\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P0\t0x000000FF\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P1\t0x0000FF00\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P2\t0x00FF0000\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P3\t0xFF000000\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P0_LOC\t0\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P1_LOC\t8\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P2_LOC\t16\n+#define DLB2_LSP_QID2CQIDIX_00_CQ_P3_LOC\t24\n+\n+#define DLB2_V2LSP_QID2CQIDIX2_00(x) \\\n \t(0xa1600000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID2CQIDIX2_00(x) \\\n+\t(0x91780000 + (x) * 0x1000)\n+#define DLB2_LSP_QID2CQIDIX2_00(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID2CQIDIX2_00(x) : \\\n+\t DLB2_V2_5LSP_QID2CQIDIX2_00(x))\n #define DLB2_LSP_QID2CQIDIX2_00_RST 0x0\n-#define DLB2_LSP_QID2CQIDIX2(x, y) \\\n-\t(DLB2_LSP_QID2CQIDIX2_00(x) + 0x80000 * (y))\n+#define DLB2_LSP_QID2CQIDIX2(ver, x, y) \\\n+\t(DLB2_LSP_QID2CQIDIX2_00(ver, x) + 0x80000 * (y))\n #define DLB2_LSP_QID2CQIDIX2_NUM 16\n-union dlb2_lsp_qid2cqidix2_00 {\n-\tstruct {\n-\t\tu32 cq_p0 : 8;\n-\t\tu32 cq_p1 : 8;\n-\t\tu32 cq_p2 : 8;\n-\t\tu32 cq_p3 : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_LDB_REPLAY_CNT(x) \\\n-\t(0xa1e00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_LDB_REPLAY_CNT_RST 0x0\n-union dlb2_lsp_qid_ldb_replay_cnt {\n-\tstruct {\n-\t\tu32 count : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH(x) \\\n+\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P0\t0x000000FF\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P1\t0x0000FF00\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P2\t0x00FF0000\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P3\t0xFF000000\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P0_LOC\t0\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P1_LOC\t8\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P2_LOC\t16\n+#define DLB2_LSP_QID2CQIDIX2_00_CQ_P3_LOC\t24\n+\n+#define DLB2_V2LSP_QID_NALDB_MAX_DEPTH(x) \\\n \t(0xa1f00000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_NALDB_MAX_DEPTH(x) \\\n+\t(0x92080000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_NALDB_MAX_DEPTH(x) : \\\n+\t DLB2_V2_5LSP_QID_NALDB_MAX_DEPTH(x))\n #define DLB2_LSP_QID_NALDB_MAX_DEPTH_RST 0x0\n-union dlb2_lsp_qid_naldb_max_depth {\n-\tstruct {\n-\t\tu32 depth : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n+\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH_DEPTH\t0x00003FFF\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RSVD0\t0xFFFFC000\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH_DEPTH_LOC\t0\n+#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RSVD0_LOC\t14\n+\n+#define DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n \t(0xa1f80000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n+\t(0x92100000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTL(x) : \\\n+\t DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTL(x))\n #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST 0x0\n-union dlb2_lsp_qid_naldb_tot_enq_cntl {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n+\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n \t(0xa2000000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n+\t(0x92180000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTH(x) : \\\n+\t DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTH(x))\n #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST 0x0\n-union dlb2_lsp_qid_naldb_tot_enq_cnth {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH(x) \\\n+\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_QID_ATM_DEPTH_THRSH(x) \\\n \t(0xa2080000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_ATM_DEPTH_THRSH(x) \\\n+\t(0x92200000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_ATM_DEPTH_THRSH(x) : \\\n+\t DLB2_V2_5LSP_QID_ATM_DEPTH_THRSH(x))\n #define DLB2_LSP_QID_ATM_DEPTH_THRSH_RST 0x0\n-union dlb2_lsp_qid_atm_depth_thrsh {\n-\tstruct {\n-\t\tu32 thresh : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH(x) \\\n+\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH_THRESH\t0x00003FFF\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RSVD0\t0xFFFFC000\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH_THRESH_LOC\t0\n+#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RSVD0_LOC\t14\n+\n+#define DLB2_V2LSP_QID_NALDB_DEPTH_THRSH(x) \\\n \t(0xa2100000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_NALDB_DEPTH_THRSH(x) \\\n+\t(0x92280000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_NALDB_DEPTH_THRSH(x) : \\\n+\t DLB2_V2_5LSP_QID_NALDB_DEPTH_THRSH(x))\n #define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST 0x0\n-union dlb2_lsp_qid_naldb_depth_thrsh {\n-\tstruct {\n-\t\tu32 thresh : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_QID_ATM_ACTIVE(x) \\\n+\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_THRESH\t0x00003FFF\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RSVD0\t\t0xFFFFC000\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_THRESH_LOC\t0\n+#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RSVD0_LOC\t14\n+\n+#define DLB2_V2LSP_QID_ATM_ACTIVE(x) \\\n \t(0xa2180000 + (x) * 0x1000)\n+#define DLB2_V2_5LSP_QID_ATM_ACTIVE(x) \\\n+\t(0x92300000 + (x) * 0x1000)\n+#define DLB2_LSP_QID_ATM_ACTIVE(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_QID_ATM_ACTIVE(x) : \\\n+\t DLB2_V2_5LSP_QID_ATM_ACTIVE(x))\n #define DLB2_LSP_QID_ATM_ACTIVE_RST 0x0\n-union dlb2_lsp_qid_atm_active {\n-\tstruct {\n-\t\tu32 count : 14;\n-\t\tu32 rsvd0 : 18;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008\n+\n+#define DLB2_LSP_QID_ATM_ACTIVE_COUNT\t0x00003FFF\n+#define DLB2_LSP_QID_ATM_ACTIVE_RSVD0\t0xFFFFC000\n+#define DLB2_LSP_QID_ATM_ACTIVE_COUNT_LOC\t0\n+#define DLB2_LSP_QID_ATM_ACTIVE_RSVD0_LOC\t14\n+\n+#define DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008\n+#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0x94000008\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 : \\\n+\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0)\n #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0\n-union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_0 {\n-\tstruct {\n-\t\tu32 pri0_weight : 8;\n-\t\tu32 pri1_weight : 8;\n-\t\tu32 pri2_weight : 8;\n-\t\tu32 pri3_weight : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI0_WEIGHT\t0x000000FF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI1_WEIGHT\t0x0000FF00\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI2_WEIGHT\t0x00FF0000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI3_WEIGHT\t0xFF000000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI0_WEIGHT_LOC\t0\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI1_WEIGHT_LOC\t8\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI2_WEIGHT_LOC\t16\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI3_WEIGHT_LOC\t24\n+\n+#define DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c\n+#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0x9400000c\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 : \\\n+\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1)\n #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0\n-union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RSVZ0_V2\t0xFFFFFFFF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RSVZ0_V2_LOC\t0\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI4_WEIGHT_V2_5\t0x000000FF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI5_WEIGHT_V2_5\t0x0000FF00\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI6_WEIGHT_V2_5\t0x00FF0000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI7_WEIGHT_V2_5\t0xFF000000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI4_WEIGHT_V2_5_LOC\t0\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI5_WEIGHT_V2_5_LOC\t8\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI6_WEIGHT_V2_5_LOC\t16\n+#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI7_WEIGHT_V2_5_LOC\t24\n+\n+#define DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014\n+#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_0 0x94000014\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_0 : \\\n+\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_0)\n #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0\n-union dlb2_lsp_cfg_arb_weight_ldb_qid_0 {\n-\tstruct {\n-\t\tu32 pri0_weight : 8;\n-\t\tu32 pri1_weight : 8;\n-\t\tu32 pri2_weight : 8;\n-\t\tu32 pri3_weight : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI0_WEIGHT\t0x000000FF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI1_WEIGHT\t0x0000FF00\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI2_WEIGHT\t0x00FF0000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI3_WEIGHT\t0xFF000000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI0_WEIGHT_LOC\t0\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI1_WEIGHT_LOC\t8\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI2_WEIGHT_LOC\t16\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI3_WEIGHT_LOC\t24\n+\n+#define DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018\n+#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_1 0x94000018\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_1 : \\\n+\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_1)\n #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0\n-union dlb2_lsp_cfg_arb_weight_ldb_qid_1 {\n-\tstruct {\n-\t\tu32 rsvz0 : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_LDB_SCHED_CTRL 0xa400002c\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RSVZ0_V2\t0xFFFFFFFF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RSVZ0_V2_LOC\t0\n+\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI4_WEIGHT_V2_5\t0x000000FF\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI5_WEIGHT_V2_5\t0x0000FF00\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI6_WEIGHT_V2_5\t0x00FF0000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI7_WEIGHT_V2_5\t0xFF000000\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI4_WEIGHT_V2_5_LOC\t0\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI5_WEIGHT_V2_5_LOC\t8\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI6_WEIGHT_V2_5_LOC\t16\n+#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI7_WEIGHT_V2_5_LOC\t24\n+\n+#define DLB2_V2LSP_LDB_SCHED_CTRL 0xa400002c\n+#define DLB2_V2_5LSP_LDB_SCHED_CTRL 0x9400002c\n+#define DLB2_LSP_LDB_SCHED_CTRL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_LDB_SCHED_CTRL : \\\n+\t DLB2_V2_5LSP_LDB_SCHED_CTRL)\n #define DLB2_LSP_LDB_SCHED_CTRL_RST 0x0\n-union dlb2_lsp_ldb_sched_ctrl {\n-\tstruct {\n-\t\tu32 cq : 8;\n-\t\tu32 qidix : 3;\n-\t\tu32 value : 1;\n-\t\tu32 nalb_haswork_v : 1;\n-\t\tu32 rlist_haswork_v : 1;\n-\t\tu32 slist_haswork_v : 1;\n-\t\tu32 inflight_ok_v : 1;\n-\t\tu32 aqed_nfull_v : 1;\n-\t\tu32 rsvz0 : 15;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_DIR_SCH_CNT_L 0xa4000034\n+\n+#define DLB2_LSP_LDB_SCHED_CTRL_CQ\t\t\t0x000000FF\n+#define DLB2_LSP_LDB_SCHED_CTRL_QIDIX\t\t0x00000700\n+#define DLB2_LSP_LDB_SCHED_CTRL_VALUE\t\t0x00000800\n+#define DLB2_LSP_LDB_SCHED_CTRL_NALB_HASWORK_V\t0x00001000\n+#define DLB2_LSP_LDB_SCHED_CTRL_RLIST_HASWORK_V\t0x00002000\n+#define DLB2_LSP_LDB_SCHED_CTRL_SLIST_HASWORK_V\t0x00004000\n+#define DLB2_LSP_LDB_SCHED_CTRL_INFLIGHT_OK_V\t0x00008000\n+#define DLB2_LSP_LDB_SCHED_CTRL_AQED_NFULL_V\t\t0x00010000\n+#define DLB2_LSP_LDB_SCHED_CTRL_RSVZ0\t\t0xFFFE0000\n+#define DLB2_LSP_LDB_SCHED_CTRL_CQ_LOC\t\t0\n+#define DLB2_LSP_LDB_SCHED_CTRL_QIDIX_LOC\t\t8\n+#define DLB2_LSP_LDB_SCHED_CTRL_VALUE_LOC\t\t11\n+#define DLB2_LSP_LDB_SCHED_CTRL_NALB_HASWORK_V_LOC\t12\n+#define DLB2_LSP_LDB_SCHED_CTRL_RLIST_HASWORK_V_LOC\t13\n+#define DLB2_LSP_LDB_SCHED_CTRL_SLIST_HASWORK_V_LOC\t14\n+#define DLB2_LSP_LDB_SCHED_CTRL_INFLIGHT_OK_V_LOC\t15\n+#define DLB2_LSP_LDB_SCHED_CTRL_AQED_NFULL_V_LOC\t16\n+#define DLB2_LSP_LDB_SCHED_CTRL_RSVZ0_LOC\t\t17\n+\n+#define DLB2_V2LSP_DIR_SCH_CNT_L 0xa4000034\n+#define DLB2_V2_5LSP_DIR_SCH_CNT_L 0x94000034\n+#define DLB2_LSP_DIR_SCH_CNT_L(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_DIR_SCH_CNT_L : \\\n+\t DLB2_V2_5LSP_DIR_SCH_CNT_L)\n #define DLB2_LSP_DIR_SCH_CNT_L_RST 0x0\n-union dlb2_lsp_dir_sch_cnt_l {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_DIR_SCH_CNT_H 0xa4000038\n+\n+#define DLB2_LSP_DIR_SCH_CNT_L_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_DIR_SCH_CNT_L_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_DIR_SCH_CNT_H 0xa4000038\n+#define DLB2_V2_5LSP_DIR_SCH_CNT_H 0x94000038\n+#define DLB2_LSP_DIR_SCH_CNT_H(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_DIR_SCH_CNT_H : \\\n+\t DLB2_V2_5LSP_DIR_SCH_CNT_H)\n #define DLB2_LSP_DIR_SCH_CNT_H_RST 0x0\n-union dlb2_lsp_dir_sch_cnt_h {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_LDB_SCH_CNT_L 0xa400003c\n+\n+#define DLB2_LSP_DIR_SCH_CNT_H_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_DIR_SCH_CNT_H_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_LDB_SCH_CNT_L 0xa400003c\n+#define DLB2_V2_5LSP_LDB_SCH_CNT_L 0x9400003c\n+#define DLB2_LSP_LDB_SCH_CNT_L(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_LDB_SCH_CNT_L : \\\n+\t DLB2_V2_5LSP_LDB_SCH_CNT_L)\n #define DLB2_LSP_LDB_SCH_CNT_L_RST 0x0\n-union dlb2_lsp_ldb_sch_cnt_l {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_LDB_SCH_CNT_H 0xa4000040\n+\n+#define DLB2_LSP_LDB_SCH_CNT_L_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_LDB_SCH_CNT_L_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_LDB_SCH_CNT_H 0xa4000040\n+#define DLB2_V2_5LSP_LDB_SCH_CNT_H 0x94000040\n+#define DLB2_LSP_LDB_SCH_CNT_H(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_LDB_SCH_CNT_H : \\\n+\t DLB2_V2_5LSP_LDB_SCH_CNT_H)\n #define DLB2_LSP_LDB_SCH_CNT_H_RST 0x0\n-union dlb2_lsp_ldb_sch_cnt_h {\n-\tstruct {\n-\t\tu32 count : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_SHDW_CTRL 0xa4000070\n+\n+#define DLB2_LSP_LDB_SCH_CNT_H_COUNT\t0xFFFFFFFF\n+#define DLB2_LSP_LDB_SCH_CNT_H_COUNT_LOC\t0\n+\n+#define DLB2_V2LSP_CFG_SHDW_CTRL 0xa4000070\n+#define DLB2_V2_5LSP_CFG_SHDW_CTRL 0x94000070\n+#define DLB2_LSP_CFG_SHDW_CTRL(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_SHDW_CTRL : \\\n+\t DLB2_V2_5LSP_CFG_SHDW_CTRL)\n #define DLB2_LSP_CFG_SHDW_CTRL_RST 0x0\n-union dlb2_lsp_cfg_shdw_ctrl {\n-\tstruct {\n-\t\tu32 transfer : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS(x) \\\n+\n+#define DLB2_LSP_CFG_SHDW_CTRL_TRANSFER\t0x00000001\n+#define DLB2_LSP_CFG_SHDW_CTRL_RSVD0\t\t0xFFFFFFFE\n+#define DLB2_LSP_CFG_SHDW_CTRL_TRANSFER_LOC\t0\n+#define DLB2_LSP_CFG_SHDW_CTRL_RSVD0_LOC\t1\n+\n+#define DLB2_V2LSP_CFG_SHDW_RANGE_COS(x) \\\n \t(0xa4000074 + (x) * 4)\n+#define DLB2_V2_5LSP_CFG_SHDW_RANGE_COS(x) \\\n+\t(0x94000074 + (x) * 4)\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS(ver, x) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_SHDW_RANGE_COS(x) : \\\n+\t DLB2_V2_5LSP_CFG_SHDW_RANGE_COS(x))\n #define DLB2_LSP_CFG_SHDW_RANGE_COS_RST 0x40\n-union dlb2_lsp_cfg_shdw_range_cos {\n-\tstruct {\n-\t\tu32 bw_range : 9;\n-\t\tu32 rsvz0 : 22;\n-\t\tu32 no_extra_credit : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0 0xac000000\n+\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE\t\t0x000001FF\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_RSVZ0\t\t0x7FFFFE00\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_NO_EXTRA_CREDIT\t0x80000000\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE_LOC\t\t0\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_RSVZ0_LOC\t\t9\n+#define DLB2_LSP_CFG_SHDW_RANGE_COS_NO_EXTRA_CREDIT_LOC\t31\n+\n+#define DLB2_V2LSP_CFG_CTRL_GENERAL_0 0xac000000\n+#define DLB2_V2_5LSP_CFG_CTRL_GENERAL_0 0x9c000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2LSP_CFG_CTRL_GENERAL_0 : \\\n+\t DLB2_V2_5LSP_CFG_CTRL_GENERAL_0)\n #define DLB2_LSP_CFG_CTRL_GENERAL_0_RST 0x0\n-union dlb2_lsp_cfg_ctrl_general_0 {\n-\tstruct {\n-\t\tu32 disab_atq_empty_arb : 1;\n-\t\tu32 inc_tok_unit_idle : 1;\n-\t\tu32 disab_rlist_pri : 1;\n-\t\tu32 inc_cmp_unit_idle : 1;\n-\t\tu32 rsvz0 : 2;\n-\t\tu32 dir_single_op : 1;\n-\t\tu32 dir_half_bw : 1;\n-\t\tu32 dir_single_out : 1;\n-\t\tu32 dir_disab_multi : 1;\n-\t\tu32 atq_single_op : 1;\n-\t\tu32 atq_half_bw : 1;\n-\t\tu32 atq_single_out : 1;\n-\t\tu32 atq_disab_multi : 1;\n-\t\tu32 dirrpl_single_op : 1;\n-\t\tu32 dirrpl_half_bw : 1;\n-\t\tu32 dirrpl_single_out : 1;\n-\t\tu32 lbrpl_single_op : 1;\n-\t\tu32 lbrpl_half_bw : 1;\n-\t\tu32 lbrpl_single_out : 1;\n-\t\tu32 ldb_single_op : 1;\n-\t\tu32 ldb_half_bw : 1;\n-\t\tu32 ldb_disab_multi : 1;\n-\t\tu32 atm_single_sch : 1;\n-\t\tu32 atm_single_cmp : 1;\n-\t\tu32 ldb_ce_tog_arb : 1;\n-\t\tu32 rsvz1 : 1;\n-\t\tu32 smon0_valid_sel : 2;\n-\t\tu32 smon0_value_sel : 1;\n-\t\tu32 smon0_compare_sel : 2;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CFG_MSTR_DIAG_RESET_STS 0xb4000000\n-#define DLB2_CFG_MSTR_DIAG_RESET_STS_RST 0x80000bff\n-union dlb2_cfg_mstr_diag_reset_sts {\n-\tstruct {\n-\t\tu32 chp_pf_reset_done : 1;\n-\t\tu32 rop_pf_reset_done : 1;\n-\t\tu32 lsp_pf_reset_done : 1;\n-\t\tu32 nalb_pf_reset_done : 1;\n-\t\tu32 ap_pf_reset_done : 1;\n-\t\tu32 dp_pf_reset_done : 1;\n-\t\tu32 qed_pf_reset_done : 1;\n-\t\tu32 dqed_pf_reset_done : 1;\n-\t\tu32 aqed_pf_reset_done : 1;\n-\t\tu32 sys_pf_reset_done : 1;\n-\t\tu32 pf_reset_active : 1;\n-\t\tu32 flrsm_state : 7;\n-\t\tu32 rsvd0 : 13;\n-\t\tu32 dlb_proc_reset_done : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004\n-#define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff\n-union dlb2_cfg_mstr_cfg_diagnostic_idle_status {\n-\tstruct {\n-\t\tu32 chp_pipeidle : 1;\n-\t\tu32 rop_pipeidle : 1;\n-\t\tu32 lsp_pipeidle : 1;\n-\t\tu32 nalb_pipeidle : 1;\n-\t\tu32 ap_pipeidle : 1;\n-\t\tu32 dp_pipeidle : 1;\n-\t\tu32 qed_pipeidle : 1;\n-\t\tu32 dqed_pipeidle : 1;\n-\t\tu32 aqed_pipeidle : 1;\n-\t\tu32 sys_pipeidle : 1;\n-\t\tu32 chp_unit_idle : 1;\n-\t\tu32 rop_unit_idle : 1;\n-\t\tu32 lsp_unit_idle : 1;\n-\t\tu32 nalb_unit_idle : 1;\n-\t\tu32 ap_unit_idle : 1;\n-\t\tu32 dp_unit_idle : 1;\n-\t\tu32 qed_unit_idle : 1;\n-\t\tu32 dqed_unit_idle : 1;\n-\t\tu32 aqed_unit_idle : 1;\n-\t\tu32 sys_unit_idle : 1;\n-\t\tu32 rsvd1 : 4;\n-\t\tu32 mstr_cfg_ring_idle : 1;\n-\t\tu32 mstr_cfg_mstr_idle : 1;\n-\t\tu32 mstr_flr_clkreq_b : 1;\n-\t\tu32 mstr_proc_idle : 1;\n-\t\tu32 mstr_proc_idle_masked : 1;\n-\t\tu32 rsvd0 : 2;\n-\t\tu32 dlb_func_idle : 1;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CFG_MSTR_CFG_PM_STATUS 0xb4000014\n-#define DLB2_CFG_MSTR_CFG_PM_STATUS_RST 0x100403e\n-union dlb2_cfg_mstr_cfg_pm_status {\n-\tstruct {\n-\t\tu32 prochot : 1;\n-\t\tu32 pgcb_dlb_idle : 1;\n-\t\tu32 pgcb_dlb_pg_rdy_ack_b : 1;\n-\t\tu32 pmsm_pgcb_req_b : 1;\n-\t\tu32 pgbc_pmc_pg_req_b : 1;\n-\t\tu32 pmc_pgcb_pg_ack_b : 1;\n-\t\tu32 pmc_pgcb_fet_en_b : 1;\n-\t\tu32 pgcb_fet_en_b : 1;\n-\t\tu32 rsvz0 : 1;\n-\t\tu32 rsvz1 : 1;\n-\t\tu32 fuse_force_on : 1;\n-\t\tu32 fuse_proc_disable : 1;\n-\t\tu32 rsvz2 : 1;\n-\t\tu32 rsvz3 : 1;\n-\t\tu32 pm_fsm_d0tod3_ok : 1;\n-\t\tu32 pm_fsm_d3tod0_ok : 1;\n-\t\tu32 dlb_in_d3 : 1;\n-\t\tu32 rsvz4 : 7;\n-\t\tu32 pmsm : 8;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE 0xb4000018\n-#define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE_RST 0x1\n-union dlb2_cfg_mstr_cfg_pm_pmcsr_disable {\n-\tstruct {\n-\t\tu32 disable : 1;\n-\t\tu32 rsvz0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_VF2PF_MAILBOX_BYTES 256\n-#define DLB2_FUNC_VF_VF2PF_MAILBOX(x) \\\n+\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2\t0x00000001\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2\t0x00000002\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2\t0x00000004\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2\t0x00000008\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2\t\t0x00000030\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2\t0x00000040\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2\t0x00000080\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2\t0x00000100\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2\t0x00000200\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2\t0x00000400\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2\t0x00000800\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2\t0x00001000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2\t0x00002000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2\t0x00004000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2\t0x00008000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2\t0x00010000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2\t0x00020000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2\t0x00040000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2\t0x00080000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2\t0x00100000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2\t0x00200000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2\t0x00400000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2\t0x00800000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2\t0x01000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2\t0x02000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2\t\t0x04000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2\t0x18000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2\t0x20000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2\t0xC0000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_LOC\t0\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_LOC\t\t1\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_LOC\t\t2\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_LOC\t\t3\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_LOC\t\t\t4\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_LOC\t\t6\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_LOC\t\t7\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_LOC\t\t8\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_LOC\t\t9\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_LOC\t\t10\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_LOC\t\t11\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_LOC\t\t12\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_LOC\t\t13\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_LOC\t\t14\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_LOC\t\t15\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_LOC\t\t16\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_LOC\t\t17\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_LOC\t\t18\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_LOC\t\t19\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_LOC\t\t20\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_LOC\t\t21\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_LOC\t\t22\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_LOC\t\t23\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_LOC\t\t24\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_LOC\t\t25\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_LOC\t\t\t26\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_LOC\t\t27\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_LOC\t\t29\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_LOC\t\t30\n+\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_5\t0x00000001\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_5\t0x00000002\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_5\t0x00000004\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_5\t0x00000008\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5\t0x00000010\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_5\t\t0x00000020\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_5\t0x00000040\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_5\t0x00000080\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_5\t0x00000100\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_5\t0x00000200\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_5\t0x00000400\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_5\t0x00000800\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_5\t0x00001000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_5\t0x00002000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_5\t0x00004000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_5\t0x00008000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_5\t0x00010000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_5\t0x00020000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_5\t0x00040000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_5\t0x00080000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_5\t0x00100000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_5\t0x00200000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_5\t0x00400000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_5\t0x00800000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_5\t0x01000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_5\t0x02000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_5\t\t0x04000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_5\t0x18000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_5\t0x20000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_5\t0xC0000000\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_5_LOC\t0\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_5_LOC\t1\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_5_LOC\t\t2\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_5_LOC\t3\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5_LOC\t\t4\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_5_LOC\t\t\t5\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_5_LOC\t\t6\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_5_LOC\t\t7\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_5_LOC\t\t8\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_5_LOC\t\t9\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_5_LOC\t\t10\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_5_LOC\t\t11\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_5_LOC\t\t12\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_5_LOC\t\t13\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_5_LOC\t14\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_5_LOC\t\t15\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_5_LOC\t16\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_5_LOC\t\t17\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_5_LOC\t\t18\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_5_LOC\t19\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_5_LOC\t\t20\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_5_LOC\t\t21\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_5_LOC\t\t22\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_5_LOC\t\t23\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_5_LOC\t\t24\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_5_LOC\t\t25\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_5_LOC\t\t\t26\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_5_LOC\t\t27\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_5_LOC\t\t29\n+#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_5_LOC\t30\n+\n+#define DLB2_LSP_SMON_COMPARE0 0xac000048\n+#define DLB2_LSP_SMON_COMPARE0_RST 0x0\n+\n+#define DLB2_LSP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_COMPARE0_COMPARE0_LOC\t0\n+\n+#define DLB2_LSP_SMON_COMPARE1 0xac00004c\n+#define DLB2_LSP_SMON_COMPARE1_RST 0x0\n+\n+#define DLB2_LSP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_COMPARE1_COMPARE1_LOC\t0\n+\n+#define DLB2_LSP_SMON_CFG0 0xac000050\n+#define DLB2_LSP_SMON_CFG0_RST 0x40000000\n+\n+#define DLB2_LSP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n+#define DLB2_LSP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n+#define DLB2_LSP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n+#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n+#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n+#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n+#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n+#define DLB2_LSP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n+#define DLB2_LSP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n+#define DLB2_LSP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n+#define DLB2_LSP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n+#define DLB2_LSP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n+#define DLB2_LSP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n+#define DLB2_LSP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n+#define DLB2_LSP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n+#define DLB2_LSP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n+#define DLB2_LSP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n+#define DLB2_LSP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n+#define DLB2_LSP_SMON_CFG0_VERSION\t\t\t0xC0000000\n+#define DLB2_LSP_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n+#define DLB2_LSP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n+#define DLB2_LSP_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n+#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n+#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n+#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n+#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n+#define DLB2_LSP_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n+#define DLB2_LSP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n+#define DLB2_LSP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n+#define DLB2_LSP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n+#define DLB2_LSP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n+#define DLB2_LSP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n+#define DLB2_LSP_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n+#define DLB2_LSP_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n+#define DLB2_LSP_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n+#define DLB2_LSP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n+#define DLB2_LSP_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n+#define DLB2_LSP_SMON_CFG0_VERSION_LOC\t\t\t30\n+\n+#define DLB2_LSP_SMON_CFG1 0xac000054\n+#define DLB2_LSP_SMON_CFG1_RST 0x0\n+\n+#define DLB2_LSP_SMON_CFG1_MODE0\t0x000000FF\n+#define DLB2_LSP_SMON_CFG1_MODE1\t0x0000FF00\n+#define DLB2_LSP_SMON_CFG1_RSVZ0\t0xFFFF0000\n+#define DLB2_LSP_SMON_CFG1_MODE0_LOC\t0\n+#define DLB2_LSP_SMON_CFG1_MODE1_LOC\t8\n+#define DLB2_LSP_SMON_CFG1_RSVZ0_LOC\t16\n+\n+#define DLB2_LSP_SMON_ACTIVITYCNTR0 0xac000058\n+#define DLB2_LSP_SMON_ACTIVITYCNTR0_RST 0x0\n+\n+#define DLB2_LSP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n+\n+#define DLB2_LSP_SMON_ACTIVITYCNTR1 0xac00005c\n+#define DLB2_LSP_SMON_ACTIVITYCNTR1_RST 0x0\n+\n+#define DLB2_LSP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n+\n+#define DLB2_LSP_SMON_MAX_TMR 0xac000060\n+#define DLB2_LSP_SMON_MAX_TMR_RST 0x0\n+\n+#define DLB2_LSP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n+\n+#define DLB2_LSP_SMON_TMR 0xac000064\n+#define DLB2_LSP_SMON_TMR_RST 0x0\n+\n+#define DLB2_LSP_SMON_TMR_TIMER\t0xFFFFFFFF\n+#define DLB2_LSP_SMON_TMR_TIMER_LOC\t0\n+\n+#define DLB2_V2CM_DIAG_RESET_STS 0xb4000000\n+#define DLB2_V2_5CM_DIAG_RESET_STS 0xa4000000\n+#define DLB2_CM_DIAG_RESET_STS(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t V2CM_DIAG_RESET_STS : \\\n+\t V2_5CM_DIAG_RESET_STS)\n+#define DLB2_CM_DIAG_RESET_STS_RST 0x80000bff\n+\n+#define DLB2_CM_DIAG_RESET_STS_CHP_PF_RESET_DONE\t0x00000001\n+#define DLB2_CM_DIAG_RESET_STS_ROP_PF_RESET_DONE\t0x00000002\n+#define DLB2_CM_DIAG_RESET_STS_LSP_PF_RESET_DONE\t0x00000004\n+#define DLB2_CM_DIAG_RESET_STS_NALB_PF_RESET_DONE\t0x00000008\n+#define DLB2_CM_DIAG_RESET_STS_AP_PF_RESET_DONE\t0x00000010\n+#define DLB2_CM_DIAG_RESET_STS_DP_PF_RESET_DONE\t0x00000020\n+#define DLB2_CM_DIAG_RESET_STS_QED_PF_RESET_DONE\t0x00000040\n+#define DLB2_CM_DIAG_RESET_STS_DQED_PF_RESET_DONE\t0x00000080\n+#define DLB2_CM_DIAG_RESET_STS_AQED_PF_RESET_DONE\t0x00000100\n+#define DLB2_CM_DIAG_RESET_STS_SYS_PF_RESET_DONE\t0x00000200\n+#define DLB2_CM_DIAG_RESET_STS_PF_RESET_ACTIVE\t0x00000400\n+#define DLB2_CM_DIAG_RESET_STS_FLRSM_STATE\t\t0x0003F800\n+#define DLB2_CM_DIAG_RESET_STS_RSVD0\t\t\t0x7FFC0000\n+#define DLB2_CM_DIAG_RESET_STS_DLB_PROC_RESET_DONE\t0x80000000\n+#define DLB2_CM_DIAG_RESET_STS_CHP_PF_RESET_DONE_LOC\t\t0\n+#define DLB2_CM_DIAG_RESET_STS_ROP_PF_RESET_DONE_LOC\t\t1\n+#define DLB2_CM_DIAG_RESET_STS_LSP_PF_RESET_DONE_LOC\t\t2\n+#define DLB2_CM_DIAG_RESET_STS_NALB_PF_RESET_DONE_LOC\t3\n+#define DLB2_CM_DIAG_RESET_STS_AP_PF_RESET_DONE_LOC\t\t4\n+#define DLB2_CM_DIAG_RESET_STS_DP_PF_RESET_DONE_LOC\t\t5\n+#define DLB2_CM_DIAG_RESET_STS_QED_PF_RESET_DONE_LOC\t\t6\n+#define DLB2_CM_DIAG_RESET_STS_DQED_PF_RESET_DONE_LOC\t7\n+#define DLB2_CM_DIAG_RESET_STS_AQED_PF_RESET_DONE_LOC\t8\n+#define DLB2_CM_DIAG_RESET_STS_SYS_PF_RESET_DONE_LOC\t\t9\n+#define DLB2_CM_DIAG_RESET_STS_PF_RESET_ACTIVE_LOC\t\t10\n+#define DLB2_CM_DIAG_RESET_STS_FLRSM_STATE_LOC\t\t11\n+#define DLB2_CM_DIAG_RESET_STS_RSVD0_LOC\t\t\t18\n+#define DLB2_CM_DIAG_RESET_STS_DLB_PROC_RESET_DONE_LOC\t31\n+\n+#define DLB2_V2CM_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004\n+#define DLB2_V2_5CM_CFG_DIAGNOSTIC_IDLE_STATUS 0xa4000004\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CM_CFG_DIAGNOSTIC_IDLE_STATUS : \\\n+\t DLB2_V2_5CM_CFG_DIAGNOSTIC_IDLE_STATUS)\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff\n+\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_PIPEIDLE\t\t0x00000001\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_PIPEIDLE\t\t0x00000002\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_PIPEIDLE\t\t0x00000004\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_PIPEIDLE\t0x00000008\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_PIPEIDLE\t\t0x00000010\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_PIPEIDLE\t\t0x00000020\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_PIPEIDLE\t\t0x00000040\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_PIPEIDLE\t0x00000080\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_PIPEIDLE\t0x00000100\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_PIPEIDLE\t\t0x00000200\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_UNIT_IDLE\t0x00000400\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_UNIT_IDLE\t0x00000800\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_UNIT_IDLE\t0x00001000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_UNIT_IDLE\t0x00002000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_UNIT_IDLE\t\t0x00004000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_UNIT_IDLE\t\t0x00008000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_UNIT_IDLE\t0x00010000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_UNIT_IDLE\t0x00020000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_UNIT_IDLE\t0x00040000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_UNIT_IDLE\t0x00080000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD1\t\t0x00F00000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_RING_IDLE\t0x01000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_MSTR_IDLE\t0x02000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_FLR_CLKREQ_B\t0x04000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE\t0x08000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_MASKED 0x10000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD0\t\t 0x60000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE\t 0x80000000\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_PIPEIDLE_LOC\t\t0\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_PIPEIDLE_LOC\t\t1\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_PIPEIDLE_LOC\t\t2\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_PIPEIDLE_LOC\t\t3\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_PIPEIDLE_LOC\t\t4\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_PIPEIDLE_LOC\t\t5\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_PIPEIDLE_LOC\t\t6\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_PIPEIDLE_LOC\t\t7\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_PIPEIDLE_LOC\t\t8\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_PIPEIDLE_LOC\t\t9\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_UNIT_IDLE_LOC\t\t10\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_UNIT_IDLE_LOC\t\t11\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_UNIT_IDLE_LOC\t\t12\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_UNIT_IDLE_LOC\t13\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_UNIT_IDLE_LOC\t\t14\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_UNIT_IDLE_LOC\t\t15\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_UNIT_IDLE_LOC\t\t16\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_UNIT_IDLE_LOC\t17\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_UNIT_IDLE_LOC\t18\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_UNIT_IDLE_LOC\t\t19\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD1_LOC\t\t\t20\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_RING_IDLE_LOC\t24\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_MSTR_IDLE_LOC\t25\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_FLR_CLKREQ_B_LOC\t26\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_LOC\t27\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_MASKED_LOC\t28\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD0_LOC\t\t\t29\n+#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE_LOC\t\t31\n+\n+#define DLB2_V2CM_CFG_PM_STATUS 0xb4000014\n+#define DLB2_V2_5CM_CFG_PM_STATUS 0xa4000014\n+#define DLB2_CM_CFG_PM_STATUS(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CM_CFG_PM_STATUS : \\\n+\t DLB2_V2_5CM_CFG_PM_STATUS)\n+#define DLB2_CM_CFG_PM_STATUS_RST 0x100403e\n+\n+#define DLB2_CM_CFG_PM_STATUS_PROCHOT\t\t0x00000001\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_IDLE\t\t0x00000002\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_PG_RDY_ACK_B\t0x00000004\n+#define DLB2_CM_CFG_PM_STATUS_PMSM_PGCB_REQ_B\t0x00000008\n+#define DLB2_CM_CFG_PM_STATUS_PGBC_PMC_PG_REQ_B\t0x00000010\n+#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_PG_ACK_B\t0x00000020\n+#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_FET_EN_B\t0x00000040\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_FET_EN_B\t\t0x00000080\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ0\t\t\t0x00000100\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ1\t\t\t0x00000200\n+#define DLB2_CM_CFG_PM_STATUS_FUSE_FORCE_ON\t\t0x00000400\n+#define DLB2_CM_CFG_PM_STATUS_FUSE_PROC_DISABLE\t0x00000800\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ2\t\t\t0x00001000\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ3\t\t\t0x00002000\n+#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D0TOD3_OK\t0x00004000\n+#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D3TOD0_OK\t0x00008000\n+#define DLB2_CM_CFG_PM_STATUS_DLB_IN_D3\t\t0x00010000\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ4\t\t\t0x00FE0000\n+#define DLB2_CM_CFG_PM_STATUS_PMSM\t\t\t0xFF000000\n+#define DLB2_CM_CFG_PM_STATUS_PROCHOT_LOC\t\t\t0\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_IDLE_LOC\t\t1\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_PG_RDY_ACK_B_LOC\t2\n+#define DLB2_CM_CFG_PM_STATUS_PMSM_PGCB_REQ_B_LOC\t\t3\n+#define DLB2_CM_CFG_PM_STATUS_PGBC_PMC_PG_REQ_B_LOC\t\t4\n+#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_PG_ACK_B_LOC\t\t5\n+#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_FET_EN_B_LOC\t\t6\n+#define DLB2_CM_CFG_PM_STATUS_PGCB_FET_EN_B_LOC\t\t7\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ0_LOC\t\t\t8\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ1_LOC\t\t\t9\n+#define DLB2_CM_CFG_PM_STATUS_FUSE_FORCE_ON_LOC\t\t10\n+#define DLB2_CM_CFG_PM_STATUS_FUSE_PROC_DISABLE_LOC\t\t11\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ2_LOC\t\t\t12\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ3_LOC\t\t\t13\n+#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D0TOD3_OK_LOC\t\t14\n+#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D3TOD0_OK_LOC\t\t15\n+#define DLB2_CM_CFG_PM_STATUS_DLB_IN_D3_LOC\t\t\t16\n+#define DLB2_CM_CFG_PM_STATUS_RSVZ4_LOC\t\t\t17\n+#define DLB2_CM_CFG_PM_STATUS_PMSM_LOC\t\t\t24\n+\n+#define DLB2_V2CM_CFG_PM_PMCSR_DISABLE 0xb4000018\n+#define DLB2_V2_5CM_CFG_PM_PMCSR_DISABLE 0xa4000018\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE(ver) \\\n+\t(ver == DLB2_HW_V2 ? \\\n+\t DLB2_V2CM_CFG_PM_PMCSR_DISABLE : \\\n+\t DLB2_V2_5CM_CFG_PM_PMCSR_DISABLE)\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RST 0x1\n+\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE_DISABLE\t0x00000001\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RSVZ0\t0xFFFFFFFE\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE_DISABLE_LOC\t0\n+#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RSVZ0_LOC\t1\n+\n+#define DLB2_VF_VF2PF_MAILBOX_BYTES 256\n+#define DLB2_VF_VF2PF_MAILBOX(x) \\\n \t(0x1000 + (x) * 0x4)\n-#define DLB2_FUNC_VF_VF2PF_MAILBOX_RST 0x0\n-union dlb2_func_vf_vf2pf_mailbox {\n-\tstruct {\n-\t\tu32 msg : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR 0x1f00\n-#define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR_RST 0x0\n-#define DLB2_FUNC_VF_SIOV_VF2PF_MAILBOX_ISR_TRIGGER 0x8000\n-union dlb2_func_vf_vf2pf_mailbox_isr {\n-\tstruct {\n-\t\tu32 isr : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_PF2VF_MAILBOX_BYTES 64\n-#define DLB2_FUNC_VF_PF2VF_MAILBOX(x) \\\n+#define DLB2_VF_VF2PF_MAILBOX_RST 0x0\n+\n+#define DLB2_VF_VF2PF_MAILBOX_MSG\t0xFFFFFFFF\n+#define DLB2_VF_VF2PF_MAILBOX_MSG_LOC\t0\n+\n+#define DLB2_VF_VF2PF_MAILBOX_ISR 0x1f00\n+#define DLB2_VF_VF2PF_MAILBOX_ISR_RST 0x0\n+#define DLB2_VF_SIOV_MBOX_ISR_TRIGGER 0x8000\n+\n+#define DLB2_VF_VF2PF_MAILBOX_ISR_ISR\t0x00000001\n+#define DLB2_VF_VF2PF_MAILBOX_ISR_RSVD0\t0xFFFFFFFE\n+#define DLB2_VF_VF2PF_MAILBOX_ISR_ISR_LOC\t0\n+#define DLB2_VF_VF2PF_MAILBOX_ISR_RSVD0_LOC\t1\n+\n+#define DLB2_VF_PF2VF_MAILBOX_BYTES 64\n+#define DLB2_VF_PF2VF_MAILBOX(x) \\\n \t(0x2000 + (x) * 0x4)\n-#define DLB2_FUNC_VF_PF2VF_MAILBOX_RST 0x0\n-union dlb2_func_vf_pf2vf_mailbox {\n-\tstruct {\n-\t\tu32 msg : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR 0x2f00\n-#define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR_RST 0x0\n-union dlb2_func_vf_pf2vf_mailbox_isr {\n-\tstruct {\n-\t\tu32 pf_isr : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_VF_MSI_ISR_PEND 0x2f10\n-#define DLB2_FUNC_VF_VF_MSI_ISR_PEND_RST 0x0\n-union dlb2_func_vf_vf_msi_isr_pend {\n-\tstruct {\n-\t\tu32 isr_pend : 32;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS 0x3000\n-#define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS_RST 0x1\n-union dlb2_func_vf_vf_reset_in_progress {\n-\tstruct {\n-\t\tu32 reset_in_progress : 1;\n-\t\tu32 rsvd0 : 31;\n-\t} field;\n-\tu32 val;\n-};\n-\n-#define DLB2_FUNC_VF_VF_MSI_ISR 0x4000\n-#define DLB2_FUNC_VF_VF_MSI_ISR_RST 0x0\n-union dlb2_func_vf_vf_msi_isr {\n-\tstruct {\n-\t\tu32 vf_msi_isr : 32;\n-\t} field;\n-\tu32 val;\n-};\n+#define DLB2_VF_PF2VF_MAILBOX_RST 0x0\n+\n+#define DLB2_VF_PF2VF_MAILBOX_MSG\t0xFFFFFFFF\n+#define DLB2_VF_PF2VF_MAILBOX_MSG_LOC\t0\n+\n+#define DLB2_VF_PF2VF_MAILBOX_ISR 0x2f00\n+#define DLB2_VF_PF2VF_MAILBOX_ISR_RST 0x0\n+\n+#define DLB2_VF_PF2VF_MAILBOX_ISR_PF_ISR\t0x00000001\n+#define DLB2_VF_PF2VF_MAILBOX_ISR_RSVD0\t0xFFFFFFFE\n+#define DLB2_VF_PF2VF_MAILBOX_ISR_PF_ISR_LOC\t0\n+#define DLB2_VF_PF2VF_MAILBOX_ISR_RSVD0_LOC\t1\n+\n+#define DLB2_VF_VF_MSI_ISR_PEND 0x2f10\n+#define DLB2_VF_VF_MSI_ISR_PEND_RST 0x0\n+\n+#define DLB2_VF_VF_MSI_ISR_PEND_ISR_PEND\t0xFFFFFFFF\n+#define DLB2_VF_VF_MSI_ISR_PEND_ISR_PEND_LOC\t0\n+\n+#define DLB2_VF_VF_RESET_IN_PROGRESS 0x3000\n+#define DLB2_VF_VF_RESET_IN_PROGRESS_RST 0x1\n+\n+#define DLB2_VF_VF_RESET_IN_PROGRESS_RESET_IN_PROGRESS\t0x00000001\n+#define DLB2_VF_VF_RESET_IN_PROGRESS_RSVD0\t\t\t0xFFFFFFFE\n+#define DLB2_VF_VF_RESET_IN_PROGRESS_RESET_IN_PROGRESS_LOC\t0\n+#define DLB2_VF_VF_RESET_IN_PROGRESS_RSVD0_LOC\t\t1\n+\n+#define DLB2_VF_VF_MSI_ISR 0x4000\n+#define DLB2_VF_VF_MSI_ISR_RST 0x0\n+\n+#define DLB2_VF_VF_MSI_ISR_VF_MSI_ISR\t0xFFFFFFFF\n+#define DLB2_VF_VF_MSI_ISR_VF_MSI_ISR_LOC\t0\n+\n+#define DLB2_SYS_TOTAL_CREDITS 0x10000100\n+#define DLB2_SYS_TOTAL_CREDITS_RST 0x4000\n+\n+#define DLB2_SYS_TOTAL_CREDITS_TOTAL_CREDITS\t0xFFFFFFFF\n+#define DLB2_SYS_TOTAL_CREDITS_TOTAL_CREDITS_LOC\t0\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_U(x) \\\n+\t(0x10000fa4 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_U_RST 0x0\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_U_CQ_AI_ADDR_U\t0xFFFFFFFF\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_U_CQ_AI_ADDR_U_LOC\t0\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L(x) \\\n+\t(0x10000fa0 + (x) * 0x1000)\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RST 0x0\n+\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RSVD0\t\t0x00000003\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L_CQ_AI_ADDR_L\t0xFFFFFFFC\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RSVD0_LOC\t\t0\n+#define DLB2_SYS_LDB_CQ_AI_ADDR_L_CQ_AI_ADDR_L_LOC\t2\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_U(x) \\\n+\t(0x10000fe4 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_U_RST 0x0\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_U_CQ_AI_ADDR_U\t0xFFFFFFFF\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_U_CQ_AI_ADDR_U_LOC\t0\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L(x) \\\n+\t(0x10000fe0 + (x) * 0x1000)\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RST 0x0\n+\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RSVD0\t\t0x00000003\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L_CQ_AI_ADDR_L\t0xFFFFFFFC\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RSVD0_LOC\t\t0\n+#define DLB2_SYS_DIR_CQ_AI_ADDR_L_CQ_AI_ADDR_L_LOC\t2\n+\n+#define DLB2_SYS_WB_DIR_CQ_STATE(x) \\\n+\t(0x11c00000 + (x) * 0x1000)\n+#define DLB2_SYS_WB_DIR_CQ_STATE_RST 0x0\n+\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB0_V\t0x00000001\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB1_V\t0x00000002\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB2_V\t0x00000004\n+#define DLB2_SYS_WB_DIR_CQ_STATE_DIR_OPT\t0x00000008\n+#define DLB2_SYS_WB_DIR_CQ_STATE_CQ_OPT_CLR\t0x00000010\n+#define DLB2_SYS_WB_DIR_CQ_STATE_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB0_V_LOC\t\t0\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB1_V_LOC\t\t1\n+#define DLB2_SYS_WB_DIR_CQ_STATE_WB2_V_LOC\t\t2\n+#define DLB2_SYS_WB_DIR_CQ_STATE_DIR_OPT_LOC\t\t3\n+#define DLB2_SYS_WB_DIR_CQ_STATE_CQ_OPT_CLR_LOC\t4\n+#define DLB2_SYS_WB_DIR_CQ_STATE_RSVD0_LOC\t\t5\n+\n+#define DLB2_SYS_WB_LDB_CQ_STATE(x) \\\n+\t(0x11d00000 + (x) * 0x1000)\n+#define DLB2_SYS_WB_LDB_CQ_STATE_RST 0x0\n+\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB0_V\t0x00000001\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB1_V\t0x00000002\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB2_V\t0x00000004\n+#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD1\t0x00000008\n+#define DLB2_SYS_WB_LDB_CQ_STATE_CQ_OPT_CLR\t0x00000010\n+#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD0\t0xFFFFFFE0\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB0_V_LOC\t\t0\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB1_V_LOC\t\t1\n+#define DLB2_SYS_WB_LDB_CQ_STATE_WB2_V_LOC\t\t2\n+#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD1_LOC\t\t3\n+#define DLB2_SYS_WB_LDB_CQ_STATE_CQ_OPT_CLR_LOC\t4\n+#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD0_LOC\t\t5\n+\n+#define DLB2_CHP_CFG_VAS_CRD(x) \\\n+\t(0x40000000 + (x) * 0x1000)\n+#define DLB2_CHP_CFG_VAS_CRD_RST 0x0\n+\n+#define DLB2_CHP_CFG_VAS_CRD_COUNT\t0x00007FFF\n+#define DLB2_CHP_CFG_VAS_CRD_RSVD0\t0xFFFF8000\n+#define DLB2_CHP_CFG_VAS_CRD_COUNT_LOC\t0\n+#define DLB2_CHP_CFG_VAS_CRD_RSVD0_LOC\t15\n+\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT(x) \\\n+\t(0x90b00000 + (x) * 0x1000)\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RST 0x0\n+\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_LIMIT\t0x00007FFF\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_V\t0x00008000\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RSVD0\t0xFFFF0000\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_LIMIT_LOC\t0\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_V_LOC\t\t15\n+#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RSVD0_LOC\t16\n \n #endif /* __DLB2_REGS_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_regs_new.h b/drivers/event/dlb2/pf/base/dlb2_regs_new.h\ndeleted file mode 100644\nindex 26c3e7f4a..000000000\n--- a/drivers/event/dlb2/pf/base/dlb2_regs_new.h\n+++ /dev/null\n@@ -1,4304 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2020 Intel Corporation\n- */\n-\n-#ifndef __DLB2_REGS_NEW_H\n-#define __DLB2_REGS_NEW_H\n-\n-#include \"dlb2_osdep_types.h\"\n-\n-#define DLB2_PF_VF2PF_MAILBOX_BYTES 256\n-#define DLB2_PF_VF2PF_MAILBOX(vf_id, x) \\\n-\t(0x1000 + 0x4 * (x) + (vf_id) * 0x10000)\n-#define DLB2_PF_VF2PF_MAILBOX_RST 0x0\n-\n-#define DLB2_PF_VF2PF_MAILBOX_MSG\t0xFFFFFFFF\n-#define DLB2_PF_VF2PF_MAILBOX_MSG_LOC\t0\n-\n-#define DLB2_PF_VF2PF_MAILBOX_ISR(vf_id) \\\n-\t(0x1f00 + (vf_id) * 0x10000)\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_RST 0x0\n-\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF0_ISR\t0x00000001\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF1_ISR\t0x00000002\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF2_ISR\t0x00000004\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF3_ISR\t0x00000008\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF4_ISR\t0x00000010\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF5_ISR\t0x00000020\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF6_ISR\t0x00000040\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF7_ISR\t0x00000080\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF8_ISR\t0x00000100\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF9_ISR\t0x00000200\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF10_ISR\t0x00000400\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF11_ISR\t0x00000800\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF12_ISR\t0x00001000\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF13_ISR\t0x00002000\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF14_ISR\t0x00004000\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF15_ISR\t0x00008000\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_RSVD0\t0xFFFF0000\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF0_ISR_LOC\t0\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF1_ISR_LOC\t1\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF2_ISR_LOC\t2\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF3_ISR_LOC\t3\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF4_ISR_LOC\t4\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF5_ISR_LOC\t5\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF6_ISR_LOC\t6\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF7_ISR_LOC\t7\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF8_ISR_LOC\t8\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF9_ISR_LOC\t9\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF10_ISR_LOC\t10\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF11_ISR_LOC\t11\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF12_ISR_LOC\t12\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF13_ISR_LOC\t13\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF14_ISR_LOC\t14\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_VF15_ISR_LOC\t15\n-#define DLB2_PF_VF2PF_MAILBOX_ISR_RSVD0_LOC\t\t16\n-\n-#define DLB2_PF_VF2PF_FLR_ISR(vf_id) \\\n-\t(0x1f04 + (vf_id) * 0x10000)\n-#define DLB2_PF_VF2PF_FLR_ISR_RST 0x0\n-\n-#define DLB2_PF_VF2PF_FLR_ISR_VF0_ISR\t0x00000001\n-#define DLB2_PF_VF2PF_FLR_ISR_VF1_ISR\t0x00000002\n-#define DLB2_PF_VF2PF_FLR_ISR_VF2_ISR\t0x00000004\n-#define DLB2_PF_VF2PF_FLR_ISR_VF3_ISR\t0x00000008\n-#define DLB2_PF_VF2PF_FLR_ISR_VF4_ISR\t0x00000010\n-#define DLB2_PF_VF2PF_FLR_ISR_VF5_ISR\t0x00000020\n-#define DLB2_PF_VF2PF_FLR_ISR_VF6_ISR\t0x00000040\n-#define DLB2_PF_VF2PF_FLR_ISR_VF7_ISR\t0x00000080\n-#define DLB2_PF_VF2PF_FLR_ISR_VF8_ISR\t0x00000100\n-#define DLB2_PF_VF2PF_FLR_ISR_VF9_ISR\t0x00000200\n-#define DLB2_PF_VF2PF_FLR_ISR_VF10_ISR\t0x00000400\n-#define DLB2_PF_VF2PF_FLR_ISR_VF11_ISR\t0x00000800\n-#define DLB2_PF_VF2PF_FLR_ISR_VF12_ISR\t0x00001000\n-#define DLB2_PF_VF2PF_FLR_ISR_VF13_ISR\t0x00002000\n-#define DLB2_PF_VF2PF_FLR_ISR_VF14_ISR\t0x00004000\n-#define DLB2_PF_VF2PF_FLR_ISR_VF15_ISR\t0x00008000\n-#define DLB2_PF_VF2PF_FLR_ISR_RSVD0\t\t0xFFFF0000\n-#define DLB2_PF_VF2PF_FLR_ISR_VF0_ISR_LOC\t0\n-#define DLB2_PF_VF2PF_FLR_ISR_VF1_ISR_LOC\t1\n-#define DLB2_PF_VF2PF_FLR_ISR_VF2_ISR_LOC\t2\n-#define DLB2_PF_VF2PF_FLR_ISR_VF3_ISR_LOC\t3\n-#define DLB2_PF_VF2PF_FLR_ISR_VF4_ISR_LOC\t4\n-#define DLB2_PF_VF2PF_FLR_ISR_VF5_ISR_LOC\t5\n-#define DLB2_PF_VF2PF_FLR_ISR_VF6_ISR_LOC\t6\n-#define DLB2_PF_VF2PF_FLR_ISR_VF7_ISR_LOC\t7\n-#define DLB2_PF_VF2PF_FLR_ISR_VF8_ISR_LOC\t8\n-#define DLB2_PF_VF2PF_FLR_ISR_VF9_ISR_LOC\t9\n-#define DLB2_PF_VF2PF_FLR_ISR_VF10_ISR_LOC\t10\n-#define DLB2_PF_VF2PF_FLR_ISR_VF11_ISR_LOC\t11\n-#define DLB2_PF_VF2PF_FLR_ISR_VF12_ISR_LOC\t12\n-#define DLB2_PF_VF2PF_FLR_ISR_VF13_ISR_LOC\t13\n-#define DLB2_PF_VF2PF_FLR_ISR_VF14_ISR_LOC\t14\n-#define DLB2_PF_VF2PF_FLR_ISR_VF15_ISR_LOC\t15\n-#define DLB2_PF_VF2PF_FLR_ISR_RSVD0_LOC\t16\n-\n-#define DLB2_PF_VF2PF_ISR_PEND(vf_id) \\\n-\t(0x1f10 + (vf_id) * 0x10000)\n-#define DLB2_PF_VF2PF_ISR_PEND_RST 0x0\n-\n-#define DLB2_PF_VF2PF_ISR_PEND_ISR_PEND\t0x00000001\n-#define DLB2_PF_VF2PF_ISR_PEND_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_PF_VF2PF_ISR_PEND_ISR_PEND_LOC\t0\n-#define DLB2_PF_VF2PF_ISR_PEND_RSVD0_LOC\t1\n-\n-#define DLB2_PF_PF2VF_MAILBOX_BYTES 64\n-#define DLB2_PF_PF2VF_MAILBOX(vf_id, x) \\\n-\t(0x2000 + 0x4 * (x) + (vf_id) * 0x10000)\n-#define DLB2_PF_PF2VF_MAILBOX_RST 0x0\n-\n-#define DLB2_PF_PF2VF_MAILBOX_MSG\t0xFFFFFFFF\n-#define DLB2_PF_PF2VF_MAILBOX_MSG_LOC\t0\n-\n-#define DLB2_PF_PF2VF_MAILBOX_ISR(vf_id) \\\n-\t(0x2f00 + (vf_id) * 0x10000)\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_RST 0x0\n-\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF0_ISR\t0x00000001\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF1_ISR\t0x00000002\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF2_ISR\t0x00000004\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF3_ISR\t0x00000008\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF4_ISR\t0x00000010\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF5_ISR\t0x00000020\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF6_ISR\t0x00000040\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF7_ISR\t0x00000080\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF8_ISR\t0x00000100\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF9_ISR\t0x00000200\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF10_ISR\t0x00000400\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF11_ISR\t0x00000800\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF12_ISR\t0x00001000\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF13_ISR\t0x00002000\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF14_ISR\t0x00004000\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF15_ISR\t0x00008000\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_RSVD0\t0xFFFF0000\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF0_ISR_LOC\t0\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF1_ISR_LOC\t1\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF2_ISR_LOC\t2\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF3_ISR_LOC\t3\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF4_ISR_LOC\t4\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF5_ISR_LOC\t5\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF6_ISR_LOC\t6\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF7_ISR_LOC\t7\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF8_ISR_LOC\t8\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF9_ISR_LOC\t9\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF10_ISR_LOC\t10\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF11_ISR_LOC\t11\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF12_ISR_LOC\t12\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF13_ISR_LOC\t13\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF14_ISR_LOC\t14\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_VF15_ISR_LOC\t15\n-#define DLB2_PF_PF2VF_MAILBOX_ISR_RSVD0_LOC\t\t16\n-\n-#define DLB2_PF_VF_RESET_IN_PROGRESS(vf_id) \\\n-\t(0x3000 + (vf_id) * 0x10000)\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_RST 0xffff\n-\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF0_RESET_IN_PROGRESS\t0x00000001\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF1_RESET_IN_PROGRESS\t0x00000002\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF2_RESET_IN_PROGRESS\t0x00000004\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF3_RESET_IN_PROGRESS\t0x00000008\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF4_RESET_IN_PROGRESS\t0x00000010\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF5_RESET_IN_PROGRESS\t0x00000020\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF6_RESET_IN_PROGRESS\t0x00000040\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF7_RESET_IN_PROGRESS\t0x00000080\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF8_RESET_IN_PROGRESS\t0x00000100\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF9_RESET_IN_PROGRESS\t0x00000200\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF10_RESET_IN_PROGRESS\t0x00000400\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF11_RESET_IN_PROGRESS\t0x00000800\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF12_RESET_IN_PROGRESS\t0x00001000\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF13_RESET_IN_PROGRESS\t0x00002000\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF14_RESET_IN_PROGRESS\t0x00004000\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF15_RESET_IN_PROGRESS\t0x00008000\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_RSVD0\t\t\t0xFFFF0000\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF0_RESET_IN_PROGRESS_LOC\t0\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF1_RESET_IN_PROGRESS_LOC\t1\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF2_RESET_IN_PROGRESS_LOC\t2\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF3_RESET_IN_PROGRESS_LOC\t3\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF4_RESET_IN_PROGRESS_LOC\t4\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF5_RESET_IN_PROGRESS_LOC\t5\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF6_RESET_IN_PROGRESS_LOC\t6\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF7_RESET_IN_PROGRESS_LOC\t7\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF8_RESET_IN_PROGRESS_LOC\t8\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF9_RESET_IN_PROGRESS_LOC\t9\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF10_RESET_IN_PROGRESS_LOC\t10\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF11_RESET_IN_PROGRESS_LOC\t11\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF12_RESET_IN_PROGRESS_LOC\t12\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF13_RESET_IN_PROGRESS_LOC\t13\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF14_RESET_IN_PROGRESS_LOC\t14\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_VF15_RESET_IN_PROGRESS_LOC\t15\n-#define DLB2_PF_VF_RESET_IN_PROGRESS_RSVD0_LOC\t\t\t16\n-\n-#define DLB2_MSIX_VECTOR_CTRL(x) \\\n-\t(0x100000c + (x) * 0x10)\n-#define DLB2_MSIX_VECTOR_CTRL_RST 0x1\n-\n-#define DLB2_MSIX_VECTOR_CTRL_VEC_MASK\t0x00000001\n-#define DLB2_MSIX_VECTOR_CTRL_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_MSIX_VECTOR_CTRL_VEC_MASK_LOC\t0\n-#define DLB2_MSIX_VECTOR_CTRL_RSVD0_LOC\t1\n-\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL(x) \\\n-\t(0x20 + (x) * 0x4)\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RST 0x0\n-\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_FUNC_VF_BAR_DIS\t0x00000001\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_FUNC_VF_BAR_DIS_LOC\t0\n-#define DLB2_IOSF_FUNC_VF_BAR_DSBL_RSVD0_LOC\t\t\t1\n-\n-#define DLB2_V2SYS_TOTAL_VAS 0x1000011c\n-#define DLB2_V2_5SYS_TOTAL_VAS 0x10000114\n-#define DLB2_SYS_TOTAL_VAS(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2SYS_TOTAL_VAS : \\\n-\t DLB2_V2_5SYS_TOTAL_VAS)\n-#define DLB2_SYS_TOTAL_VAS_RST 0x20\n-\n-#define DLB2_SYS_TOTAL_VAS_TOTAL_VAS\t0xFFFFFFFF\n-#define DLB2_SYS_TOTAL_VAS_TOTAL_VAS_LOC\t0\n-\n-#define DLB2_SYS_TOTAL_DIR_CRDS 0x10000108\n-#define DLB2_SYS_TOTAL_DIR_CRDS_RST 0x1000\n-\n-#define DLB2_SYS_TOTAL_DIR_CRDS_TOTAL_DIR_CREDITS\t0xFFFFFFFF\n-#define DLB2_SYS_TOTAL_DIR_CRDS_TOTAL_DIR_CREDITS_LOC\t0\n-\n-#define DLB2_SYS_TOTAL_LDB_CRDS 0x10000104\n-#define DLB2_SYS_TOTAL_LDB_CRDS_RST 0x2000\n-\n-#define DLB2_SYS_TOTAL_LDB_CRDS_TOTAL_LDB_CREDITS\t0xFFFFFFFF\n-#define DLB2_SYS_TOTAL_LDB_CRDS_TOTAL_LDB_CREDITS_LOC\t0\n-\n-#define DLB2_SYS_ALARM_PF_SYND2 0x10000508\n-#define DLB2_SYS_ALARM_PF_SYND2_RST 0x0\n-\n-#define DLB2_SYS_ALARM_PF_SYND2_LOCK_ID\t0x0000FFFF\n-#define DLB2_SYS_ALARM_PF_SYND2_MEAS\t\t0x00010000\n-#define DLB2_SYS_ALARM_PF_SYND2_DEBUG\t0x00FE0000\n-#define DLB2_SYS_ALARM_PF_SYND2_CQ_POP\t0x01000000\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_UHL\t0x02000000\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_ORSP\t0x04000000\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_VALID\t0x08000000\n-#define DLB2_SYS_ALARM_PF_SYND2_CQ_INT_REARM\t0x10000000\n-#define DLB2_SYS_ALARM_PF_SYND2_DSI_ERROR\t0x20000000\n-#define DLB2_SYS_ALARM_PF_SYND2_RSVD0\t0xC0000000\n-#define DLB2_SYS_ALARM_PF_SYND2_LOCK_ID_LOC\t\t0\n-#define DLB2_SYS_ALARM_PF_SYND2_MEAS_LOC\t\t16\n-#define DLB2_SYS_ALARM_PF_SYND2_DEBUG_LOC\t\t17\n-#define DLB2_SYS_ALARM_PF_SYND2_CQ_POP_LOC\t\t24\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_UHL_LOC\t\t25\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_ORSP_LOC\t\t26\n-#define DLB2_SYS_ALARM_PF_SYND2_QE_VALID_LOC\t\t27\n-#define DLB2_SYS_ALARM_PF_SYND2_CQ_INT_REARM_LOC\t28\n-#define DLB2_SYS_ALARM_PF_SYND2_DSI_ERROR_LOC\t29\n-#define DLB2_SYS_ALARM_PF_SYND2_RSVD0_LOC\t\t30\n-\n-#define DLB2_SYS_ALARM_PF_SYND1 0x10000504\n-#define DLB2_SYS_ALARM_PF_SYND1_RST 0x0\n-\n-#define DLB2_SYS_ALARM_PF_SYND1_DSI\t\t0x0000FFFF\n-#define DLB2_SYS_ALARM_PF_SYND1_QID\t\t0x00FF0000\n-#define DLB2_SYS_ALARM_PF_SYND1_QTYPE\t0x03000000\n-#define DLB2_SYS_ALARM_PF_SYND1_QPRI\t\t0x1C000000\n-#define DLB2_SYS_ALARM_PF_SYND1_MSG_TYPE\t0xE0000000\n-#define DLB2_SYS_ALARM_PF_SYND1_DSI_LOC\t0\n-#define DLB2_SYS_ALARM_PF_SYND1_QID_LOC\t16\n-#define DLB2_SYS_ALARM_PF_SYND1_QTYPE_LOC\t24\n-#define DLB2_SYS_ALARM_PF_SYND1_QPRI_LOC\t26\n-#define DLB2_SYS_ALARM_PF_SYND1_MSG_TYPE_LOC\t29\n-\n-#define DLB2_SYS_ALARM_PF_SYND0 0x10000500\n-#define DLB2_SYS_ALARM_PF_SYND0_RST 0x0\n-\n-#define DLB2_SYS_ALARM_PF_SYND0_SYNDROME\t0x000000FF\n-#define DLB2_SYS_ALARM_PF_SYND0_RTYPE\t0x00000300\n-#define DLB2_SYS_ALARM_PF_SYND0_RSVD0\t0x00001C00\n-#define DLB2_SYS_ALARM_PF_SYND0_IS_LDB\t0x00002000\n-#define DLB2_SYS_ALARM_PF_SYND0_CLS\t\t0x0000C000\n-#define DLB2_SYS_ALARM_PF_SYND0_AID\t\t0x003F0000\n-#define DLB2_SYS_ALARM_PF_SYND0_UNIT\t\t0x03C00000\n-#define DLB2_SYS_ALARM_PF_SYND0_SOURCE\t0x3C000000\n-#define DLB2_SYS_ALARM_PF_SYND0_MORE\t\t0x40000000\n-#define DLB2_SYS_ALARM_PF_SYND0_VALID\t0x80000000\n-#define DLB2_SYS_ALARM_PF_SYND0_SYNDROME_LOC\t0\n-#define DLB2_SYS_ALARM_PF_SYND0_RTYPE_LOC\t8\n-#define DLB2_SYS_ALARM_PF_SYND0_RSVD0_LOC\t10\n-#define DLB2_SYS_ALARM_PF_SYND0_IS_LDB_LOC\t13\n-#define DLB2_SYS_ALARM_PF_SYND0_CLS_LOC\t14\n-#define DLB2_SYS_ALARM_PF_SYND0_AID_LOC\t16\n-#define DLB2_SYS_ALARM_PF_SYND0_UNIT_LOC\t22\n-#define DLB2_SYS_ALARM_PF_SYND0_SOURCE_LOC\t26\n-#define DLB2_SYS_ALARM_PF_SYND0_MORE_LOC\t30\n-#define DLB2_SYS_ALARM_PF_SYND0_VALID_LOC\t31\n-\n-#define DLB2_SYS_VF_LDB_VPP_V(x) \\\n-\t(0x10000f00 + (x) * 0x1000)\n-#define DLB2_SYS_VF_LDB_VPP_V_RST 0x0\n-\n-#define DLB2_SYS_VF_LDB_VPP_V_VPP_V\t0x00000001\n-#define DLB2_SYS_VF_LDB_VPP_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_VF_LDB_VPP_V_VPP_V_LOC\t0\n-#define DLB2_SYS_VF_LDB_VPP_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_VF_LDB_VPP2PP(x) \\\n-\t(0x10000f04 + (x) * 0x1000)\n-#define DLB2_SYS_VF_LDB_VPP2PP_RST 0x0\n-\n-#define DLB2_SYS_VF_LDB_VPP2PP_PP\t0x0000003F\n-#define DLB2_SYS_VF_LDB_VPP2PP_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_VF_LDB_VPP2PP_PP_LOC\t0\n-#define DLB2_SYS_VF_LDB_VPP2PP_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_VF_DIR_VPP_V(x) \\\n-\t(0x10000f08 + (x) * 0x1000)\n-#define DLB2_SYS_VF_DIR_VPP_V_RST 0x0\n-\n-#define DLB2_SYS_VF_DIR_VPP_V_VPP_V\t0x00000001\n-#define DLB2_SYS_VF_DIR_VPP_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_VF_DIR_VPP_V_VPP_V_LOC\t0\n-#define DLB2_SYS_VF_DIR_VPP_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_VF_DIR_VPP2PP(x) \\\n-\t(0x10000f0c + (x) * 0x1000)\n-#define DLB2_SYS_VF_DIR_VPP2PP_RST 0x0\n-\n-#define DLB2_SYS_VF_DIR_VPP2PP_PP\t0x0000003F\n-#define DLB2_SYS_VF_DIR_VPP2PP_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_VF_DIR_VPP2PP_PP_LOC\t0\n-#define DLB2_SYS_VF_DIR_VPP2PP_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_VF_LDB_VQID_V(x) \\\n-\t(0x10000f10 + (x) * 0x1000)\n-#define DLB2_SYS_VF_LDB_VQID_V_RST 0x0\n-\n-#define DLB2_SYS_VF_LDB_VQID_V_VQID_V\t0x00000001\n-#define DLB2_SYS_VF_LDB_VQID_V_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_SYS_VF_LDB_VQID_V_VQID_V_LOC\t0\n-#define DLB2_SYS_VF_LDB_VQID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_VF_LDB_VQID2QID(x) \\\n-\t(0x10000f14 + (x) * 0x1000)\n-#define DLB2_SYS_VF_LDB_VQID2QID_RST 0x0\n-\n-#define DLB2_SYS_VF_LDB_VQID2QID_QID\t\t0x0000001F\n-#define DLB2_SYS_VF_LDB_VQID2QID_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_VF_LDB_VQID2QID_QID_LOC\t0\n-#define DLB2_SYS_VF_LDB_VQID2QID_RSVD0_LOC\t5\n-\n-#define DLB2_SYS_LDB_QID2VQID(x) \\\n-\t(0x10000f18 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_QID2VQID_RST 0x0\n-\n-#define DLB2_SYS_LDB_QID2VQID_VQID\t0x0000001F\n-#define DLB2_SYS_LDB_QID2VQID_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_LDB_QID2VQID_VQID_LOC\t0\n-#define DLB2_SYS_LDB_QID2VQID_RSVD0_LOC\t5\n-\n-#define DLB2_SYS_VF_DIR_VQID_V(x) \\\n-\t(0x10000f1c + (x) * 0x1000)\n-#define DLB2_SYS_VF_DIR_VQID_V_RST 0x0\n-\n-#define DLB2_SYS_VF_DIR_VQID_V_VQID_V\t0x00000001\n-#define DLB2_SYS_VF_DIR_VQID_V_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_SYS_VF_DIR_VQID_V_VQID_V_LOC\t0\n-#define DLB2_SYS_VF_DIR_VQID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_VF_DIR_VQID2QID(x) \\\n-\t(0x10000f20 + (x) * 0x1000)\n-#define DLB2_SYS_VF_DIR_VQID2QID_RST 0x0\n-\n-#define DLB2_SYS_VF_DIR_VQID2QID_QID\t\t0x0000003F\n-#define DLB2_SYS_VF_DIR_VQID2QID_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_VF_DIR_VQID2QID_QID_LOC\t0\n-#define DLB2_SYS_VF_DIR_VQID2QID_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_LDB_VASQID_V(x) \\\n-\t(0x10000f24 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_VASQID_V_RST 0x0\n-\n-#define DLB2_SYS_LDB_VASQID_V_VASQID_V\t0x00000001\n-#define DLB2_SYS_LDB_VASQID_V_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_SYS_LDB_VASQID_V_VASQID_V_LOC\t0\n-#define DLB2_SYS_LDB_VASQID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_DIR_VASQID_V(x) \\\n-\t(0x10000f28 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_VASQID_V_RST 0x0\n-\n-#define DLB2_SYS_DIR_VASQID_V_VASQID_V\t0x00000001\n-#define DLB2_SYS_DIR_VASQID_V_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_SYS_DIR_VASQID_V_VASQID_V_LOC\t0\n-#define DLB2_SYS_DIR_VASQID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_ALARM_VF_SYND2(x) \\\n-\t(0x10000f48 + (x) * 0x1000)\n-#define DLB2_SYS_ALARM_VF_SYND2_RST 0x0\n-\n-#define DLB2_SYS_ALARM_VF_SYND2_LOCK_ID\t0x0000FFFF\n-#define DLB2_SYS_ALARM_VF_SYND2_DEBUG\t0x00FF0000\n-#define DLB2_SYS_ALARM_VF_SYND2_CQ_POP\t0x01000000\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_UHL\t0x02000000\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_ORSP\t0x04000000\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_VALID\t0x08000000\n-#define DLB2_SYS_ALARM_VF_SYND2_ISZ\t\t0x10000000\n-#define DLB2_SYS_ALARM_VF_SYND2_DSI_ERROR\t0x20000000\n-#define DLB2_SYS_ALARM_VF_SYND2_DLBRSVD\t0xC0000000\n-#define DLB2_SYS_ALARM_VF_SYND2_LOCK_ID_LOC\t\t0\n-#define DLB2_SYS_ALARM_VF_SYND2_DEBUG_LOC\t\t16\n-#define DLB2_SYS_ALARM_VF_SYND2_CQ_POP_LOC\t\t24\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_UHL_LOC\t\t25\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_ORSP_LOC\t\t26\n-#define DLB2_SYS_ALARM_VF_SYND2_QE_VALID_LOC\t\t27\n-#define DLB2_SYS_ALARM_VF_SYND2_ISZ_LOC\t\t28\n-#define DLB2_SYS_ALARM_VF_SYND2_DSI_ERROR_LOC\t29\n-#define DLB2_SYS_ALARM_VF_SYND2_DLBRSVD_LOC\t\t30\n-\n-#define DLB2_SYS_ALARM_VF_SYND1(x) \\\n-\t(0x10000f44 + (x) * 0x1000)\n-#define DLB2_SYS_ALARM_VF_SYND1_RST 0x0\n-\n-#define DLB2_SYS_ALARM_VF_SYND1_DSI\t\t0x0000FFFF\n-#define DLB2_SYS_ALARM_VF_SYND1_QID\t\t0x00FF0000\n-#define DLB2_SYS_ALARM_VF_SYND1_QTYPE\t0x03000000\n-#define DLB2_SYS_ALARM_VF_SYND1_QPRI\t\t0x1C000000\n-#define DLB2_SYS_ALARM_VF_SYND1_MSG_TYPE\t0xE0000000\n-#define DLB2_SYS_ALARM_VF_SYND1_DSI_LOC\t0\n-#define DLB2_SYS_ALARM_VF_SYND1_QID_LOC\t16\n-#define DLB2_SYS_ALARM_VF_SYND1_QTYPE_LOC\t24\n-#define DLB2_SYS_ALARM_VF_SYND1_QPRI_LOC\t26\n-#define DLB2_SYS_ALARM_VF_SYND1_MSG_TYPE_LOC\t29\n-\n-#define DLB2_SYS_ALARM_VF_SYND0(x) \\\n-\t(0x10000f40 + (x) * 0x1000)\n-#define DLB2_SYS_ALARM_VF_SYND0_RST 0x0\n-\n-#define DLB2_SYS_ALARM_VF_SYND0_SYNDROME\t\t0x000000FF\n-#define DLB2_SYS_ALARM_VF_SYND0_RTYPE\t\t0x00000300\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND0_PARITY\t0x00000400\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND1_PARITY\t0x00000800\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND2_PARITY\t0x00001000\n-#define DLB2_SYS_ALARM_VF_SYND0_IS_LDB\t\t0x00002000\n-#define DLB2_SYS_ALARM_VF_SYND0_CLS\t\t\t0x0000C000\n-#define DLB2_SYS_ALARM_VF_SYND0_AID\t\t\t0x003F0000\n-#define DLB2_SYS_ALARM_VF_SYND0_UNIT\t\t\t0x03C00000\n-#define DLB2_SYS_ALARM_VF_SYND0_SOURCE\t\t0x3C000000\n-#define DLB2_SYS_ALARM_VF_SYND0_MORE\t\t\t0x40000000\n-#define DLB2_SYS_ALARM_VF_SYND0_VALID\t\t0x80000000\n-#define DLB2_SYS_ALARM_VF_SYND0_SYNDROME_LOC\t\t0\n-#define DLB2_SYS_ALARM_VF_SYND0_RTYPE_LOC\t\t8\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND0_PARITY_LOC\t10\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND1_PARITY_LOC\t11\n-#define DLB2_SYS_ALARM_VF_SYND0_VF_SYND2_PARITY_LOC\t12\n-#define DLB2_SYS_ALARM_VF_SYND0_IS_LDB_LOC\t\t13\n-#define DLB2_SYS_ALARM_VF_SYND0_CLS_LOC\t\t14\n-#define DLB2_SYS_ALARM_VF_SYND0_AID_LOC\t\t16\n-#define DLB2_SYS_ALARM_VF_SYND0_UNIT_LOC\t\t22\n-#define DLB2_SYS_ALARM_VF_SYND0_SOURCE_LOC\t\t26\n-#define DLB2_SYS_ALARM_VF_SYND0_MORE_LOC\t\t30\n-#define DLB2_SYS_ALARM_VF_SYND0_VALID_LOC\t\t31\n-\n-#define DLB2_SYS_LDB_QID_CFG_V(x) \\\n-\t(0x10000f58 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_QID_CFG_V_RST 0x0\n-\n-#define DLB2_SYS_LDB_QID_CFG_V_SN_CFG_V\t0x00000001\n-#define DLB2_SYS_LDB_QID_CFG_V_FID_CFG_V\t0x00000002\n-#define DLB2_SYS_LDB_QID_CFG_V_RSVD0\t\t0xFFFFFFFC\n-#define DLB2_SYS_LDB_QID_CFG_V_SN_CFG_V_LOC\t0\n-#define DLB2_SYS_LDB_QID_CFG_V_FID_CFG_V_LOC\t1\n-#define DLB2_SYS_LDB_QID_CFG_V_RSVD0_LOC\t2\n-\n-#define DLB2_SYS_LDB_QID_ITS(x) \\\n-\t(0x10000f54 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_QID_ITS_RST 0x0\n-\n-#define DLB2_SYS_LDB_QID_ITS_QID_ITS\t0x00000001\n-#define DLB2_SYS_LDB_QID_ITS_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_LDB_QID_ITS_QID_ITS_LOC\t0\n-#define DLB2_SYS_LDB_QID_ITS_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_LDB_QID_V(x) \\\n-\t(0x10000f50 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_QID_V_RST 0x0\n-\n-#define DLB2_SYS_LDB_QID_V_QID_V\t0x00000001\n-#define DLB2_SYS_LDB_QID_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_LDB_QID_V_QID_V_LOC\t0\n-#define DLB2_SYS_LDB_QID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_DIR_QID_ITS(x) \\\n-\t(0x10000f64 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_QID_ITS_RST 0x0\n-\n-#define DLB2_SYS_DIR_QID_ITS_QID_ITS\t0x00000001\n-#define DLB2_SYS_DIR_QID_ITS_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_DIR_QID_ITS_QID_ITS_LOC\t0\n-#define DLB2_SYS_DIR_QID_ITS_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_DIR_QID_V(x) \\\n-\t(0x10000f60 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_QID_V_RST 0x0\n-\n-#define DLB2_SYS_DIR_QID_V_QID_V\t0x00000001\n-#define DLB2_SYS_DIR_QID_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_DIR_QID_V_QID_V_LOC\t0\n-#define DLB2_SYS_DIR_QID_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_LDB_CQ_AI_DATA(x) \\\n-\t(0x10000fa8 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_AI_DATA_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_AI_DATA_CQ_AI_DATA\t0xFFFFFFFF\n-#define DLB2_SYS_LDB_CQ_AI_DATA_CQ_AI_DATA_LOC\t0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR(x) \\\n-\t(0x10000fa4 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD1\t0x00000003\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_CQ_AI_ADDR\t0x000FFFFC\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD0\t0xFFF00000\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD1_LOC\t\t0\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_CQ_AI_ADDR_LOC\t2\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_RSVD0_LOC\t\t20\n-\n-#define DLB2_V2SYS_LDB_CQ_PASID(x) \\\n-\t(0x10000fa0 + (x) * 0x1000)\n-#define DLB2_V2_5SYS_LDB_CQ_PASID(x) \\\n-\t(0x10000f9c + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_PASID(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2SYS_LDB_CQ_PASID(x) : \\\n-\t DLB2_V2_5SYS_LDB_CQ_PASID(x))\n-#define DLB2_SYS_LDB_CQ_PASID_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_PASID_PASID\t\t0x000FFFFF\n-#define DLB2_SYS_LDB_CQ_PASID_EXE_REQ\t0x00100000\n-#define DLB2_SYS_LDB_CQ_PASID_PRIV_REQ\t0x00200000\n-#define DLB2_SYS_LDB_CQ_PASID_FMT2\t\t0x00400000\n-#define DLB2_SYS_LDB_CQ_PASID_RSVD0\t\t0xFF800000\n-#define DLB2_SYS_LDB_CQ_PASID_PASID_LOC\t0\n-#define DLB2_SYS_LDB_CQ_PASID_EXE_REQ_LOC\t20\n-#define DLB2_SYS_LDB_CQ_PASID_PRIV_REQ_LOC\t21\n-#define DLB2_SYS_LDB_CQ_PASID_FMT2_LOC\t22\n-#define DLB2_SYS_LDB_CQ_PASID_RSVD0_LOC\t23\n-\n-#define DLB2_SYS_LDB_CQ_AT(x) \\\n-\t(0x10000f9c + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_AT_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_AT_CQ_AT\t0x00000003\n-#define DLB2_SYS_LDB_CQ_AT_RSVD0\t0xFFFFFFFC\n-#define DLB2_SYS_LDB_CQ_AT_CQ_AT_LOC\t0\n-#define DLB2_SYS_LDB_CQ_AT_RSVD0_LOC\t2\n-\n-#define DLB2_SYS_LDB_CQ_ISR(x) \\\n-\t(0x10000f98 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_ISR_RST 0x0\n-/* CQ Interrupt Modes */\n-#define DLB2_CQ_ISR_MODE_DIS  0\n-#define DLB2_CQ_ISR_MODE_MSI  1\n-#define DLB2_CQ_ISR_MODE_MSIX 2\n-#define DLB2_CQ_ISR_MODE_ADI  3\n-\n-#define DLB2_SYS_LDB_CQ_ISR_VECTOR\t0x0000003F\n-#define DLB2_SYS_LDB_CQ_ISR_VF\t0x000003C0\n-#define DLB2_SYS_LDB_CQ_ISR_EN_CODE\t0x00000C00\n-#define DLB2_SYS_LDB_CQ_ISR_RSVD0\t0xFFFFF000\n-#define DLB2_SYS_LDB_CQ_ISR_VECTOR_LOC\t0\n-#define DLB2_SYS_LDB_CQ_ISR_VF_LOC\t\t6\n-#define DLB2_SYS_LDB_CQ_ISR_EN_CODE_LOC\t10\n-#define DLB2_SYS_LDB_CQ_ISR_RSVD0_LOC\t12\n-\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO(x) \\\n-\t(0x10000f94 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_VF\t\t0x0000000F\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_IS_PF\t0x00000010\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RO\t\t0x00000020\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_VF_LOC\t0\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_IS_PF_LOC\t4\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RO_LOC\t5\n-#define DLB2_SYS_LDB_CQ2VF_PF_RO_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_LDB_PP_V(x) \\\n-\t(0x10000f90 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_PP_V_RST 0x0\n-\n-#define DLB2_SYS_LDB_PP_V_PP_V\t0x00000001\n-#define DLB2_SYS_LDB_PP_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_LDB_PP_V_PP_V_LOC\t0\n-#define DLB2_SYS_LDB_PP_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_LDB_PP2VDEV(x) \\\n-\t(0x10000f8c + (x) * 0x1000)\n-#define DLB2_SYS_LDB_PP2VDEV_RST 0x0\n-\n-#define DLB2_SYS_LDB_PP2VDEV_VDEV\t0x0000000F\n-#define DLB2_SYS_LDB_PP2VDEV_RSVD0\t0xFFFFFFF0\n-#define DLB2_SYS_LDB_PP2VDEV_VDEV_LOC\t0\n-#define DLB2_SYS_LDB_PP2VDEV_RSVD0_LOC\t4\n-\n-#define DLB2_SYS_LDB_PP2VAS(x) \\\n-\t(0x10000f88 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_PP2VAS_RST 0x0\n-\n-#define DLB2_SYS_LDB_PP2VAS_VAS\t0x0000001F\n-#define DLB2_SYS_LDB_PP2VAS_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_LDB_PP2VAS_VAS_LOC\t\t0\n-#define DLB2_SYS_LDB_PP2VAS_RSVD0_LOC\t5\n-\n-#define DLB2_SYS_LDB_CQ_ADDR_U(x) \\\n-\t(0x10000f84 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_ADDR_U_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_ADDR_U_ADDR_U\t0xFFFFFFFF\n-#define DLB2_SYS_LDB_CQ_ADDR_U_ADDR_U_LOC\t0\n-\n-#define DLB2_SYS_LDB_CQ_ADDR_L(x) \\\n-\t(0x10000f80 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_ADDR_L_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_ADDR_L_RSVD0\t\t0x0000003F\n-#define DLB2_SYS_LDB_CQ_ADDR_L_ADDR_L\t0xFFFFFFC0\n-#define DLB2_SYS_LDB_CQ_ADDR_L_RSVD0_LOC\t0\n-#define DLB2_SYS_LDB_CQ_ADDR_L_ADDR_L_LOC\t6\n-\n-#define DLB2_SYS_DIR_CQ_FMT(x) \\\n-\t(0x10000fec + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_FMT_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_FMT_KEEP_PF_PPID\t0x00000001\n-#define DLB2_SYS_DIR_CQ_FMT_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_SYS_DIR_CQ_FMT_KEEP_PF_PPID_LOC\t0\n-#define DLB2_SYS_DIR_CQ_FMT_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_DIR_CQ_AI_DATA(x) \\\n-\t(0x10000fe8 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_AI_DATA_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_AI_DATA_CQ_AI_DATA\t0xFFFFFFFF\n-#define DLB2_SYS_DIR_CQ_AI_DATA_CQ_AI_DATA_LOC\t0\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR(x) \\\n-\t(0x10000fe4 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD1\t0x00000003\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_CQ_AI_ADDR\t0x000FFFFC\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD0\t0xFFF00000\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD1_LOC\t\t0\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_CQ_AI_ADDR_LOC\t2\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_RSVD0_LOC\t\t20\n-\n-#define DLB2_V2SYS_DIR_CQ_PASID(x) \\\n-\t(0x10000fe0 + (x) * 0x1000)\n-#define DLB2_V2_5SYS_DIR_CQ_PASID(x) \\\n-\t(0x10000fdc + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_PASID(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2SYS_DIR_CQ_PASID(x) : \\\n-\t DLB2_V2_5SYS_DIR_CQ_PASID(x))\n-#define DLB2_SYS_DIR_CQ_PASID_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_PASID_PASID\t\t0x000FFFFF\n-#define DLB2_SYS_DIR_CQ_PASID_EXE_REQ\t0x00100000\n-#define DLB2_SYS_DIR_CQ_PASID_PRIV_REQ\t0x00200000\n-#define DLB2_SYS_DIR_CQ_PASID_FMT2\t\t0x00400000\n-#define DLB2_SYS_DIR_CQ_PASID_RSVD0\t\t0xFF800000\n-#define DLB2_SYS_DIR_CQ_PASID_PASID_LOC\t0\n-#define DLB2_SYS_DIR_CQ_PASID_EXE_REQ_LOC\t20\n-#define DLB2_SYS_DIR_CQ_PASID_PRIV_REQ_LOC\t21\n-#define DLB2_SYS_DIR_CQ_PASID_FMT2_LOC\t22\n-#define DLB2_SYS_DIR_CQ_PASID_RSVD0_LOC\t23\n-\n-#define DLB2_SYS_DIR_CQ_AT(x) \\\n-\t(0x10000fdc + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_AT_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_AT_CQ_AT\t0x00000003\n-#define DLB2_SYS_DIR_CQ_AT_RSVD0\t0xFFFFFFFC\n-#define DLB2_SYS_DIR_CQ_AT_CQ_AT_LOC\t0\n-#define DLB2_SYS_DIR_CQ_AT_RSVD0_LOC\t2\n-\n-#define DLB2_SYS_DIR_CQ_ISR(x) \\\n-\t(0x10000fd8 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_ISR_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_ISR_VECTOR\t0x0000003F\n-#define DLB2_SYS_DIR_CQ_ISR_VF\t0x000003C0\n-#define DLB2_SYS_DIR_CQ_ISR_EN_CODE\t0x00000C00\n-#define DLB2_SYS_DIR_CQ_ISR_RSVD0\t0xFFFFF000\n-#define DLB2_SYS_DIR_CQ_ISR_VECTOR_LOC\t0\n-#define DLB2_SYS_DIR_CQ_ISR_VF_LOC\t\t6\n-#define DLB2_SYS_DIR_CQ_ISR_EN_CODE_LOC\t10\n-#define DLB2_SYS_DIR_CQ_ISR_RSVD0_LOC\t12\n-\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO(x) \\\n-\t(0x10000fd4 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_VF\t\t0x0000000F\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_IS_PF\t0x00000010\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RO\t\t0x00000020\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_VF_LOC\t0\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_IS_PF_LOC\t4\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RO_LOC\t5\n-#define DLB2_SYS_DIR_CQ2VF_PF_RO_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_DIR_PP_V(x) \\\n-\t(0x10000fd0 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_PP_V_RST 0x0\n-\n-#define DLB2_SYS_DIR_PP_V_PP_V\t0x00000001\n-#define DLB2_SYS_DIR_PP_V_RSVD0\t0xFFFFFFFE\n-#define DLB2_SYS_DIR_PP_V_PP_V_LOC\t0\n-#define DLB2_SYS_DIR_PP_V_RSVD0_LOC\t1\n-\n-#define DLB2_SYS_DIR_PP2VDEV(x) \\\n-\t(0x10000fcc + (x) * 0x1000)\n-#define DLB2_SYS_DIR_PP2VDEV_RST 0x0\n-\n-#define DLB2_SYS_DIR_PP2VDEV_VDEV\t0x0000000F\n-#define DLB2_SYS_DIR_PP2VDEV_RSVD0\t0xFFFFFFF0\n-#define DLB2_SYS_DIR_PP2VDEV_VDEV_LOC\t0\n-#define DLB2_SYS_DIR_PP2VDEV_RSVD0_LOC\t4\n-\n-#define DLB2_SYS_DIR_PP2VAS(x) \\\n-\t(0x10000fc8 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_PP2VAS_RST 0x0\n-\n-#define DLB2_SYS_DIR_PP2VAS_VAS\t0x0000001F\n-#define DLB2_SYS_DIR_PP2VAS_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_DIR_PP2VAS_VAS_LOC\t\t0\n-#define DLB2_SYS_DIR_PP2VAS_RSVD0_LOC\t5\n-\n-#define DLB2_SYS_DIR_CQ_ADDR_U(x) \\\n-\t(0x10000fc4 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_ADDR_U_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_ADDR_U_ADDR_U\t0xFFFFFFFF\n-#define DLB2_SYS_DIR_CQ_ADDR_U_ADDR_U_LOC\t0\n-\n-#define DLB2_SYS_DIR_CQ_ADDR_L(x) \\\n-\t(0x10000fc0 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_ADDR_L_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_ADDR_L_RSVD0\t\t0x0000003F\n-#define DLB2_SYS_DIR_CQ_ADDR_L_ADDR_L\t0xFFFFFFC0\n-#define DLB2_SYS_DIR_CQ_ADDR_L_RSVD0_LOC\t0\n-#define DLB2_SYS_DIR_CQ_ADDR_L_ADDR_L_LOC\t6\n-\n-#define DLB2_SYS_PM_SMON_COMP_MASK1 0x10003024\n-#define DLB2_SYS_PM_SMON_COMP_MASK1_RST 0xffffffff\n-\n-#define DLB2_SYS_PM_SMON_COMP_MASK1_COMP_MASK1\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_COMP_MASK1_COMP_MASK1_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_COMP_MASK0 0x10003020\n-#define DLB2_SYS_PM_SMON_COMP_MASK0_RST 0xffffffff\n-\n-#define DLB2_SYS_PM_SMON_COMP_MASK0_COMP_MASK0\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_COMP_MASK0_COMP_MASK0_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_MAX_TMR 0x1000301c\n-#define DLB2_SYS_PM_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_TMR 0x10003018\n-#define DLB2_SYS_PM_SMON_TMR_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_TMR_TIMER_VAL\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_TMR_TIMER_VAL_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1 0x10003014\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0 0x10003010\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_COMPARE1 0x1000300c\n-#define DLB2_SYS_PM_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_COMPARE0 0x10003008\n-#define DLB2_SYS_PM_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_SYS_PM_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_SYS_PM_SMON_CFG1 0x10003004\n-#define DLB2_SYS_PM_SMON_CFG1_RST 0x0\n-\n-#define DLB2_SYS_PM_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_SYS_PM_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_SYS_PM_SMON_CFG1_RSVD\t0xFFFF0000\n-#define DLB2_SYS_PM_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_SYS_PM_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_SYS_PM_SMON_CFG1_RSVD_LOC\t16\n-\n-#define DLB2_SYS_PM_SMON_CFG0 0x10003000\n-#define DLB2_SYS_PM_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_SYS_PM_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD2\t\t\t0x0000000E\n-#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_SYS_PM_SMON_CFG0_SMON_MODE\t\t0x0000F000\n-#define DLB2_SYS_PM_SMON_CFG0_STOPCOUNTEROVFL\t0x00010000\n-#define DLB2_SYS_PM_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER0OVFL\t0x00040000\n-#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER1OVFL\t0x00080000\n-#define DLB2_SYS_PM_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_SYS_PM_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_SYS_PM_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD1\t\t\t0x00800000\n-#define DLB2_SYS_PM_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD0\t\t\t0x20000000\n-#define DLB2_SYS_PM_SMON_CFG0_VERSION\t\t0xC0000000\n-#define DLB2_SYS_PM_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD2_LOC\t\t\t1\n-#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_SYS_PM_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_SYS_PM_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_SYS_PM_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_SYS_PM_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_SYS_PM_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_SYS_PM_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_SYS_PM_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_SYS_PM_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n-#define DLB2_SYS_PM_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD1_LOC\t\t\t23\n-#define DLB2_SYS_PM_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_SYS_PM_SMON_CFG0_RSVD0_LOC\t\t\t29\n-#define DLB2_SYS_PM_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_SYS_SMON_COMP_MASK1(x) \\\n-\t(0x18002024 + (x) * 0x40)\n-#define DLB2_SYS_SMON_COMP_MASK1_RST 0xffffffff\n-\n-#define DLB2_SYS_SMON_COMP_MASK1_COMP_MASK1\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_COMP_MASK1_COMP_MASK1_LOC\t0\n-\n-#define DLB2_SYS_SMON_COMP_MASK0(x) \\\n-\t(0x18002020 + (x) * 0x40)\n-#define DLB2_SYS_SMON_COMP_MASK0_RST 0xffffffff\n-\n-#define DLB2_SYS_SMON_COMP_MASK0_COMP_MASK0\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_COMP_MASK0_COMP_MASK0_LOC\t0\n-\n-#define DLB2_SYS_SMON_MAX_TMR(x) \\\n-\t(0x1800201c + (x) * 0x40)\n-#define DLB2_SYS_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_SYS_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_SYS_SMON_TMR(x) \\\n-\t(0x18002018 + (x) * 0x40)\n-#define DLB2_SYS_SMON_TMR_RST 0x0\n-\n-#define DLB2_SYS_SMON_TMR_TIMER_VAL\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_TMR_TIMER_VAL_LOC\t0\n-\n-#define DLB2_SYS_SMON_ACTIVITYCNTR1(x) \\\n-\t(0x18002014 + (x) * 0x40)\n-#define DLB2_SYS_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_SYS_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_SYS_SMON_ACTIVITYCNTR0(x) \\\n-\t(0x18002010 + (x) * 0x40)\n-#define DLB2_SYS_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_SYS_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_SYS_SMON_COMPARE1(x) \\\n-\t(0x1800200c + (x) * 0x40)\n-#define DLB2_SYS_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_SYS_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_SYS_SMON_COMPARE0(x) \\\n-\t(0x18002008 + (x) * 0x40)\n-#define DLB2_SYS_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_SYS_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_SYS_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_SYS_SMON_CFG1(x) \\\n-\t(0x18002004 + (x) * 0x40)\n-#define DLB2_SYS_SMON_CFG1_RST 0x0\n-\n-#define DLB2_SYS_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_SYS_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_SYS_SMON_CFG1_RSVD\t0xFFFF0000\n-#define DLB2_SYS_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_SYS_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_SYS_SMON_CFG1_RSVD_LOC\t16\n-\n-#define DLB2_SYS_SMON_CFG0(x) \\\n-\t(0x18002000 + (x) * 0x40)\n-#define DLB2_SYS_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_SYS_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_SYS_SMON_CFG0_RSVD2\t\t\t0x0000000E\n-#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_SYS_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_SYS_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_SYS_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_SYS_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_SYS_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_SYS_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_SYS_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_SYS_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_SYS_SMON_CFG0_RSVD1\t\t\t0x00800000\n-#define DLB2_SYS_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_SYS_SMON_CFG0_RSVD0\t\t\t0x20000000\n-#define DLB2_SYS_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_SYS_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_SYS_SMON_CFG0_RSVD2_LOC\t\t\t\t1\n-#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_SYS_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_SYS_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_SYS_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_SYS_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_SYS_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_SYS_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_SYS_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_SYS_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n-#define DLB2_SYS_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_SYS_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n-#define DLB2_SYS_SMON_CFG0_RSVD1_LOC\t\t\t\t23\n-#define DLB2_SYS_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_SYS_SMON_CFG0_RSVD0_LOC\t\t\t\t29\n-#define DLB2_SYS_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_SYS_INGRESS_ALARM_ENBL 0x10000300\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_RST 0x0\n-\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_HCW\t\t0x00000001\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PP\t\t0x00000002\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PASID\t\t0x00000004\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_QID\t\t0x00000008\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_DISABLED_QID\t\t0x00000010\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_LDB_QID_CFG\t0x00000020\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_RSVD0\t\t\t0xFFFFFFC0\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_HCW_LOC\t\t0\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PP_LOC\t\t1\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_PASID_LOC\t2\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_QID_LOC\t\t3\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_DISABLED_QID_LOC\t\t4\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_ILLEGAL_LDB_QID_CFG_LOC\t5\n-#define DLB2_SYS_INGRESS_ALARM_ENBL_RSVD0_LOC\t\t6\n-\n-#define DLB2_SYS_MSIX_ACK 0x10000400\n-#define DLB2_SYS_MSIX_ACK_RST 0x0\n-\n-#define DLB2_SYS_MSIX_ACK_MSIX_0_ACK\t0x00000001\n-#define DLB2_SYS_MSIX_ACK_MSIX_1_ACK\t0x00000002\n-#define DLB2_SYS_MSIX_ACK_RSVD0\t0xFFFFFFFC\n-#define DLB2_SYS_MSIX_ACK_MSIX_0_ACK_LOC\t0\n-#define DLB2_SYS_MSIX_ACK_MSIX_1_ACK_LOC\t1\n-#define DLB2_SYS_MSIX_ACK_RSVD0_LOC\t\t2\n-\n-#define DLB2_SYS_MSIX_PASSTHRU 0x10000404\n-#define DLB2_SYS_MSIX_PASSTHRU_RST 0x0\n-\n-#define DLB2_SYS_MSIX_PASSTHRU_MSIX_0_PASSTHRU\t0x00000001\n-#define DLB2_SYS_MSIX_PASSTHRU_MSIX_1_PASSTHRU\t0x00000002\n-#define DLB2_SYS_MSIX_PASSTHRU_RSVD0\t\t\t0xFFFFFFFC\n-#define DLB2_SYS_MSIX_PASSTHRU_MSIX_0_PASSTHRU_LOC\t0\n-#define DLB2_SYS_MSIX_PASSTHRU_MSIX_1_PASSTHRU_LOC\t1\n-#define DLB2_SYS_MSIX_PASSTHRU_RSVD0_LOC\t\t2\n-\n-#define DLB2_SYS_MSIX_MODE 0x10000408\n-#define DLB2_SYS_MSIX_MODE_RST 0x0\n-/* MSI-X Modes */\n-#define DLB2_MSIX_MODE_PACKED     0\n-#define DLB2_MSIX_MODE_COMPRESSED 1\n-\n-#define DLB2_SYS_MSIX_MODE_MODE_V2\t0x00000001\n-#define DLB2_SYS_MSIX_MODE_POLL_MODE_V2\t0x00000002\n-#define DLB2_SYS_MSIX_MODE_POLL_MASK_V2\t0x00000004\n-#define DLB2_SYS_MSIX_MODE_POLL_LOCK_V2\t0x00000008\n-#define DLB2_SYS_MSIX_MODE_RSVD0_V2\t0xFFFFFFF0\n-#define DLB2_SYS_MSIX_MODE_MODE_V2_LOC\t0\n-#define DLB2_SYS_MSIX_MODE_POLL_MODE_V2_LOC\t1\n-#define DLB2_SYS_MSIX_MODE_POLL_MASK_V2_LOC\t2\n-#define DLB2_SYS_MSIX_MODE_POLL_LOCK_V2_LOC\t3\n-#define DLB2_SYS_MSIX_MODE_RSVD0_V2_LOC\t4\n-\n-#define DLB2_SYS_MSIX_MODE_MODE_V2_5\t0x00000001\n-#define DLB2_SYS_MSIX_MODE_IMS_POLLING_V2_5\t0x00000002\n-#define DLB2_SYS_MSIX_MODE_RSVD0_V2_5\t0xFFFFFFFC\n-#define DLB2_SYS_MSIX_MODE_MODE_V2_5_LOC\t\t0\n-#define DLB2_SYS_MSIX_MODE_IMS_POLLING_V2_5_LOC\t1\n-#define DLB2_SYS_MSIX_MODE_RSVD0_V2_5_LOC\t\t2\n-\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS 0x10000440\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT\t0x00000001\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT\t0x00000002\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT\t0x00000004\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT\t0x00000008\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT\t0x00000010\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT\t0x00000020\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT\t0x00000040\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT\t0x00000080\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT\t0x00000100\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT\t0x00000200\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT\t0x00000400\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT\t0x00000800\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT\t0x00001000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT\t0x00002000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT\t0x00004000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT\t0x00008000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT\t0x00010000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT\t0x00020000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT\t0x00040000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT\t0x00080000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT\t0x00100000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT\t0x00200000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT\t0x00400000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT\t0x00800000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT\t0x01000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT\t0x02000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT\t0x04000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT\t0x08000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT\t0x10000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT\t0x20000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT\t0x40000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT\t0x80000000\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT_LOC\t0\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT_LOC\t1\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT_LOC\t2\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT_LOC\t3\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT_LOC\t4\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT_LOC\t5\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT_LOC\t6\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT_LOC\t7\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT_LOC\t8\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT_LOC\t9\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT_LOC\t10\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT_LOC\t11\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT_LOC\t12\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT_LOC\t13\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT_LOC\t14\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT_LOC\t15\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT_LOC\t16\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT_LOC\t17\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT_LOC\t18\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT_LOC\t19\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT_LOC\t20\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT_LOC\t21\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT_LOC\t22\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT_LOC\t23\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT_LOC\t24\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT_LOC\t25\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT_LOC\t26\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT_LOC\t27\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT_LOC\t28\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT_LOC\t29\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT_LOC\t30\n-#define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT_LOC\t31\n-\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS 0x10000444\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT\t0x00000001\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT\t0x00000002\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT\t0x00000004\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT\t0x00000008\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT\t0x00000010\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT\t0x00000020\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT\t0x00000040\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT\t0x00000080\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT\t0x00000100\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT\t0x00000200\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT\t0x00000400\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT\t0x00000800\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT\t0x00001000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT\t0x00002000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT\t0x00004000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT\t0x00008000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT\t0x00010000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT\t0x00020000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT\t0x00040000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT\t0x00080000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT\t0x00100000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT\t0x00200000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT\t0x00400000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT\t0x00800000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT\t0x01000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT\t0x02000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT\t0x04000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT\t0x08000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT\t0x10000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT\t0x20000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT\t0x40000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT\t0x80000000\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT_LOC\t0\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT_LOC\t1\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT_LOC\t2\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT_LOC\t3\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT_LOC\t4\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT_LOC\t5\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT_LOC\t6\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT_LOC\t7\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT_LOC\t8\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT_LOC\t9\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT_LOC\t10\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT_LOC\t11\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT_LOC\t12\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT_LOC\t13\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT_LOC\t14\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT_LOC\t15\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT_LOC\t16\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT_LOC\t17\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT_LOC\t18\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT_LOC\t19\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT_LOC\t20\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT_LOC\t21\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT_LOC\t22\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT_LOC\t23\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT_LOC\t24\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT_LOC\t25\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT_LOC\t26\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT_LOC\t27\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT_LOC\t28\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT_LOC\t29\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT_LOC\t30\n-#define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT_LOC\t31\n-\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS 0x10000460\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT\t0x00000001\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT\t0x00000002\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT\t0x00000004\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT\t0x00000008\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT\t0x00000010\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT\t0x00000020\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT\t0x00000040\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT\t0x00000080\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT\t0x00000100\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT\t0x00000200\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT\t0x00000400\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT\t0x00000800\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT\t0x00001000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT\t0x00002000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT\t0x00004000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT\t0x00008000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT\t0x00010000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT\t0x00020000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT\t0x00040000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT\t0x00080000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT\t0x00100000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT\t0x00200000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT\t0x00400000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT\t0x00800000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT\t0x01000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT\t0x02000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT\t0x04000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT\t0x08000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT\t0x10000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT\t0x20000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT\t0x40000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT\t0x80000000\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_0_OCC_INT_LOC\t0\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_1_OCC_INT_LOC\t1\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_2_OCC_INT_LOC\t2\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_3_OCC_INT_LOC\t3\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_4_OCC_INT_LOC\t4\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_5_OCC_INT_LOC\t5\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_6_OCC_INT_LOC\t6\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_7_OCC_INT_LOC\t7\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_8_OCC_INT_LOC\t8\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_9_OCC_INT_LOC\t9\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_10_OCC_INT_LOC\t10\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_11_OCC_INT_LOC\t11\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_12_OCC_INT_LOC\t12\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_13_OCC_INT_LOC\t13\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_14_OCC_INT_LOC\t14\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_15_OCC_INT_LOC\t15\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_16_OCC_INT_LOC\t16\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_17_OCC_INT_LOC\t17\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_18_OCC_INT_LOC\t18\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_19_OCC_INT_LOC\t19\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_20_OCC_INT_LOC\t20\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_21_OCC_INT_LOC\t21\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_22_OCC_INT_LOC\t22\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_23_OCC_INT_LOC\t23\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_24_OCC_INT_LOC\t24\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_25_OCC_INT_LOC\t25\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_26_OCC_INT_LOC\t26\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_27_OCC_INT_LOC\t27\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_28_OCC_INT_LOC\t28\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_29_OCC_INT_LOC\t29\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_30_OCC_INT_LOC\t30\n-#define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_CQ_31_OCC_INT_LOC\t31\n-\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS 0x10000464\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT\t0x00000001\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT\t0x00000002\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT\t0x00000004\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT\t0x00000008\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT\t0x00000010\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT\t0x00000020\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT\t0x00000040\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT\t0x00000080\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT\t0x00000100\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT\t0x00000200\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT\t0x00000400\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT\t0x00000800\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT\t0x00001000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT\t0x00002000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT\t0x00004000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT\t0x00008000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT\t0x00010000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT\t0x00020000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT\t0x00040000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT\t0x00080000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT\t0x00100000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT\t0x00200000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT\t0x00400000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT\t0x00800000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT\t0x01000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT\t0x02000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT\t0x04000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT\t0x08000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT\t0x10000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT\t0x20000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT\t0x40000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT\t0x80000000\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_32_OCC_INT_LOC\t0\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_33_OCC_INT_LOC\t1\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_34_OCC_INT_LOC\t2\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_35_OCC_INT_LOC\t3\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_36_OCC_INT_LOC\t4\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_37_OCC_INT_LOC\t5\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_38_OCC_INT_LOC\t6\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_39_OCC_INT_LOC\t7\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_40_OCC_INT_LOC\t8\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_41_OCC_INT_LOC\t9\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_42_OCC_INT_LOC\t10\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_43_OCC_INT_LOC\t11\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_44_OCC_INT_LOC\t12\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_45_OCC_INT_LOC\t13\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_46_OCC_INT_LOC\t14\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_47_OCC_INT_LOC\t15\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_48_OCC_INT_LOC\t16\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_49_OCC_INT_LOC\t17\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_50_OCC_INT_LOC\t18\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_51_OCC_INT_LOC\t19\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_52_OCC_INT_LOC\t20\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_53_OCC_INT_LOC\t21\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_54_OCC_INT_LOC\t22\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_55_OCC_INT_LOC\t23\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_56_OCC_INT_LOC\t24\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_57_OCC_INT_LOC\t25\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_58_OCC_INT_LOC\t26\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_59_OCC_INT_LOC\t27\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_60_OCC_INT_LOC\t28\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_61_OCC_INT_LOC\t29\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_62_OCC_INT_LOC\t30\n-#define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_CQ_63_OCC_INT_LOC\t31\n-\n-#define DLB2_SYS_DIR_CQ_OPT_CLR 0x100004c0\n-#define DLB2_SYS_DIR_CQ_OPT_CLR_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_OPT_CLR_CQ\t\t0x0000003F\n-#define DLB2_SYS_DIR_CQ_OPT_CLR_RSVD0\t0xFFFFFFC0\n-#define DLB2_SYS_DIR_CQ_OPT_CLR_CQ_LOC\t0\n-#define DLB2_SYS_DIR_CQ_OPT_CLR_RSVD0_LOC\t6\n-\n-#define DLB2_SYS_ALARM_HW_SYND 0x1000050c\n-#define DLB2_SYS_ALARM_HW_SYND_RST 0x0\n-\n-#define DLB2_SYS_ALARM_HW_SYND_SYNDROME\t0x000000FF\n-#define DLB2_SYS_ALARM_HW_SYND_RTYPE\t\t0x00000300\n-#define DLB2_SYS_ALARM_HW_SYND_ALARM\t\t0x00000400\n-#define DLB2_SYS_ALARM_HW_SYND_CWD\t\t0x00000800\n-#define DLB2_SYS_ALARM_HW_SYND_VF_PF_MB\t0x00001000\n-#define DLB2_SYS_ALARM_HW_SYND_RSVD0\t\t0x00002000\n-#define DLB2_SYS_ALARM_HW_SYND_CLS\t\t0x0000C000\n-#define DLB2_SYS_ALARM_HW_SYND_AID\t\t0x003F0000\n-#define DLB2_SYS_ALARM_HW_SYND_UNIT\t\t0x03C00000\n-#define DLB2_SYS_ALARM_HW_SYND_SOURCE\t0x3C000000\n-#define DLB2_SYS_ALARM_HW_SYND_MORE\t\t0x40000000\n-#define DLB2_SYS_ALARM_HW_SYND_VALID\t\t0x80000000\n-#define DLB2_SYS_ALARM_HW_SYND_SYNDROME_LOC\t0\n-#define DLB2_SYS_ALARM_HW_SYND_RTYPE_LOC\t8\n-#define DLB2_SYS_ALARM_HW_SYND_ALARM_LOC\t10\n-#define DLB2_SYS_ALARM_HW_SYND_CWD_LOC\t11\n-#define DLB2_SYS_ALARM_HW_SYND_VF_PF_MB_LOC\t12\n-#define DLB2_SYS_ALARM_HW_SYND_RSVD0_LOC\t13\n-#define DLB2_SYS_ALARM_HW_SYND_CLS_LOC\t14\n-#define DLB2_SYS_ALARM_HW_SYND_AID_LOC\t16\n-#define DLB2_SYS_ALARM_HW_SYND_UNIT_LOC\t22\n-#define DLB2_SYS_ALARM_HW_SYND_SOURCE_LOC\t26\n-#define DLB2_SYS_ALARM_HW_SYND_MORE_LOC\t30\n-#define DLB2_SYS_ALARM_HW_SYND_VALID_LOC\t31\n-\n-#define DLB2_AQED_QID_FID_LIM(x) \\\n-\t(0x20000000 + (x) * 0x1000)\n-#define DLB2_AQED_QID_FID_LIM_RST 0x7ff\n-\n-#define DLB2_AQED_QID_FID_LIM_QID_FID_LIMIT\t0x00001FFF\n-#define DLB2_AQED_QID_FID_LIM_RSVD0\t\t0xFFFFE000\n-#define DLB2_AQED_QID_FID_LIM_QID_FID_LIMIT_LOC\t0\n-#define DLB2_AQED_QID_FID_LIM_RSVD0_LOC\t\t13\n-\n-#define DLB2_AQED_QID_HID_WIDTH(x) \\\n-\t(0x20080000 + (x) * 0x1000)\n-#define DLB2_AQED_QID_HID_WIDTH_RST 0x0\n-\n-#define DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE\t0x00000007\n-#define DLB2_AQED_QID_HID_WIDTH_RSVD0\t\t0xFFFFFFF8\n-#define DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE_LOC\t0\n-#define DLB2_AQED_QID_HID_WIDTH_RSVD0_LOC\t\t3\n-\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8\n-\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI0\t0x000000FF\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI1\t0x0000FF00\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI2\t0x00FF0000\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI3\t0xFF000000\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI0_LOC\t0\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI1_LOC\t8\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI2_LOC\t16\n-#define DLB2_AQED_CFG_ARB_WEIGHTS_TQPRI_ATM_0_PRI3_LOC\t24\n-\n-#define DLB2_AQED_SMON_ACTIVITYCNTR0 0x2c00004c\n-#define DLB2_AQED_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_AQED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_AQED_SMON_ACTIVITYCNTR1 0x2c000050\n-#define DLB2_AQED_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_AQED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_AQED_SMON_COMPARE0 0x2c000054\n-#define DLB2_AQED_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_AQED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_AQED_SMON_COMPARE1 0x2c000058\n-#define DLB2_AQED_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_AQED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_AQED_SMON_CFG0 0x2c00005c\n-#define DLB2_AQED_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_AQED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_AQED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_AQED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_AQED_SMON_CFG0_SMON_MODE\t\t0x0000F000\n-#define DLB2_AQED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_AQED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_AQED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_AQED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_AQED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_AQED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_AQED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_AQED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_AQED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_AQED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_AQED_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_AQED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_AQED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_AQED_SMON_CFG0_RSVZ0_LOC\t\t\t2\n-#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_AQED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_AQED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_AQED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_AQED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_AQED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_AQED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_AQED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_AQED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_AQED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_AQED_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_AQED_SMON_CFG0_RSVZ1_LOC\t\t\t23\n-#define DLB2_AQED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_AQED_SMON_CFG0_RSVZ2_LOC\t\t\t29\n-#define DLB2_AQED_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_AQED_SMON_CFG1 0x2c000060\n-#define DLB2_AQED_SMON_CFG1_RST 0x0\n-\n-#define DLB2_AQED_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_AQED_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_AQED_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_AQED_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_AQED_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_AQED_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_AQED_SMON_MAX_TMR 0x2c000064\n-#define DLB2_AQED_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_AQED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_AQED_SMON_TMR 0x2c000068\n-#define DLB2_AQED_SMON_TMR_RST 0x0\n-\n-#define DLB2_AQED_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_AQED_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_ATM_QID2CQIDIX_00(x) \\\n-\t(0x30080000 + (x) * 0x1000)\n-#define DLB2_ATM_QID2CQIDIX_00_RST 0x0\n-#define DLB2_ATM_QID2CQIDIX(x, y) \\\n-\t(DLB2_ATM_QID2CQIDIX_00(x) + 0x80000 * (y))\n-#define DLB2_ATM_QID2CQIDIX_NUM 16\n-\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P0\t0x000000FF\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P1\t0x0000FF00\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P2\t0x00FF0000\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P3\t0xFF000000\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P0_LOC\t0\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P1_LOC\t8\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P2_LOC\t16\n-#define DLB2_ATM_QID2CQIDIX_00_CQ_P3_LOC\t24\n-\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN 0x34000004\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc\n-\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN0\t0x000000FF\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN1\t0x0000FF00\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN2\t0x00FF0000\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN3\t0xFF000000\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN0_LOC\t0\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN1_LOC\t8\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN2_LOC\t16\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_BIN3_LOC\t24\n-\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN 0x34000008\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc\n-\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN0\t0x000000FF\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN1\t0x0000FF00\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN2\t0x00FF0000\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN3\t0xFF000000\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN0_LOC\t0\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN1_LOC\t8\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN2_LOC\t16\n-#define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_BIN3_LOC\t24\n-\n-#define DLB2_ATM_SMON_ACTIVITYCNTR0 0x3c000050\n-#define DLB2_ATM_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_ATM_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_ATM_SMON_ACTIVITYCNTR1 0x3c000054\n-#define DLB2_ATM_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_ATM_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_ATM_SMON_COMPARE0 0x3c000058\n-#define DLB2_ATM_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_ATM_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_ATM_SMON_COMPARE1 0x3c00005c\n-#define DLB2_ATM_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_ATM_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_ATM_SMON_CFG0 0x3c000060\n-#define DLB2_ATM_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_ATM_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_ATM_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_ATM_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_ATM_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_ATM_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_ATM_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_ATM_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_ATM_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_ATM_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_ATM_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_ATM_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_ATM_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_ATM_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_ATM_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_ATM_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_ATM_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_ATM_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_ATM_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n-#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_ATM_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_ATM_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_ATM_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_ATM_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_ATM_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_ATM_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_ATM_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_ATM_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n-#define DLB2_ATM_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_ATM_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n-#define DLB2_ATM_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n-#define DLB2_ATM_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_ATM_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n-#define DLB2_ATM_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_ATM_SMON_CFG1 0x3c000064\n-#define DLB2_ATM_SMON_CFG1_RST 0x0\n-\n-#define DLB2_ATM_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_ATM_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_ATM_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_ATM_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_ATM_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_ATM_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_ATM_SMON_MAX_TMR 0x3c000068\n-#define DLB2_ATM_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_ATM_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_ATM_SMON_TMR 0x3c00006c\n-#define DLB2_ATM_SMON_TMR_RST 0x0\n-\n-#define DLB2_ATM_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_ATM_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_CHP_CFG_DIR_VAS_CRD(x) \\\n-\t(0x40000000 + (x) * 0x1000)\n-#define DLB2_CHP_CFG_DIR_VAS_CRD_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_VAS_CRD_COUNT\t0x00003FFF\n-#define DLB2_CHP_CFG_DIR_VAS_CRD_RSVD0\t0xFFFFC000\n-#define DLB2_CHP_CFG_DIR_VAS_CRD_COUNT_LOC\t0\n-#define DLB2_CHP_CFG_DIR_VAS_CRD_RSVD0_LOC\t14\n-\n-#define DLB2_CHP_CFG_LDB_VAS_CRD(x) \\\n-\t(0x40080000 + (x) * 0x1000)\n-#define DLB2_CHP_CFG_LDB_VAS_CRD_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_VAS_CRD_COUNT\t0x00007FFF\n-#define DLB2_CHP_CFG_LDB_VAS_CRD_RSVD0\t0xFFFF8000\n-#define DLB2_CHP_CFG_LDB_VAS_CRD_COUNT_LOC\t0\n-#define DLB2_CHP_CFG_LDB_VAS_CRD_RSVD0_LOC\t15\n-\n-#define DLB2_V2CHP_ORD_QID_SN(x) \\\n-\t(0x40100000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_ORD_QID_SN(x) \\\n-\t(0x40080000 + (x) * 0x1000)\n-#define DLB2_CHP_ORD_QID_SN(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_ORD_QID_SN(x) : \\\n-\t DLB2_V2_5CHP_ORD_QID_SN(x))\n-#define DLB2_CHP_ORD_QID_SN_RST 0x0\n-\n-#define DLB2_CHP_ORD_QID_SN_SN\t0x000003FF\n-#define DLB2_CHP_ORD_QID_SN_RSVD0\t0xFFFFFC00\n-#define DLB2_CHP_ORD_QID_SN_SN_LOC\t\t0\n-#define DLB2_CHP_ORD_QID_SN_RSVD0_LOC\t10\n-\n-#define DLB2_V2CHP_ORD_QID_SN_MAP(x) \\\n-\t(0x40180000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_ORD_QID_SN_MAP(x) \\\n-\t(0x40100000 + (x) * 0x1000)\n-#define DLB2_CHP_ORD_QID_SN_MAP(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_ORD_QID_SN_MAP(x) : \\\n-\t DLB2_V2_5CHP_ORD_QID_SN_MAP(x))\n-#define DLB2_CHP_ORD_QID_SN_MAP_RST 0x0\n-\n-#define DLB2_CHP_ORD_QID_SN_MAP_MODE\t\t0x00000007\n-#define DLB2_CHP_ORD_QID_SN_MAP_SLOT\t\t0x00000078\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ0\t0x00000080\n-#define DLB2_CHP_ORD_QID_SN_MAP_GRP\t\t0x00000100\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ1\t0x00000200\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVD0\t0xFFFFFC00\n-#define DLB2_CHP_ORD_QID_SN_MAP_MODE_LOC\t0\n-#define DLB2_CHP_ORD_QID_SN_MAP_SLOT_LOC\t3\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ0_LOC\t7\n-#define DLB2_CHP_ORD_QID_SN_MAP_GRP_LOC\t8\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVZ1_LOC\t9\n-#define DLB2_CHP_ORD_QID_SN_MAP_RSVD0_LOC\t10\n-\n-#define DLB2_V2CHP_SN_CHK_ENBL(x) \\\n-\t(0x40200000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_SN_CHK_ENBL(x) \\\n-\t(0x40180000 + (x) * 0x1000)\n-#define DLB2_CHP_SN_CHK_ENBL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_SN_CHK_ENBL(x) : \\\n-\t DLB2_V2_5CHP_SN_CHK_ENBL(x))\n-#define DLB2_CHP_SN_CHK_ENBL_RST 0x0\n-\n-#define DLB2_CHP_SN_CHK_ENBL_EN\t0x00000001\n-#define DLB2_CHP_SN_CHK_ENBL_RSVD0\t0xFFFFFFFE\n-#define DLB2_CHP_SN_CHK_ENBL_EN_LOC\t\t0\n-#define DLB2_CHP_SN_CHK_ENBL_RSVD0_LOC\t1\n-\n-#define DLB2_V2CHP_DIR_CQ_DEPTH(x) \\\n-\t(0x40280000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_DEPTH(x) \\\n-\t(0x40300000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_DEPTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_DEPTH(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_DEPTH(x))\n-#define DLB2_CHP_DIR_CQ_DEPTH_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_DEPTH_DEPTH\t0x00001FFF\n-#define DLB2_CHP_DIR_CQ_DEPTH_RSVD0\t0xFFFFE000\n-#define DLB2_CHP_DIR_CQ_DEPTH_DEPTH_LOC\t0\n-#define DLB2_CHP_DIR_CQ_DEPTH_RSVD0_LOC\t13\n-\n-#define DLB2_V2CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n-\t(0x40300000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_INT_DEPTH_THRSH(x) \\\n-\t(0x40380000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_INT_DEPTH_THRSH(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_INT_DEPTH_THRSH(x))\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD\t0x00001FFF\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RSVD0\t\t0xFFFFE000\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD_LOC\t0\n-#define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RSVD0_LOC\t\t13\n-\n-#define DLB2_V2CHP_DIR_CQ_INT_ENB(x) \\\n-\t(0x40380000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_INT_ENB(x) \\\n-\t(0x40400000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_INT_ENB(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_INT_ENB(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_INT_ENB(x))\n-#define DLB2_CHP_DIR_CQ_INT_ENB_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_INT_ENB_EN_TIM\t0x00000001\n-#define DLB2_CHP_DIR_CQ_INT_ENB_EN_DEPTH\t0x00000002\n-#define DLB2_CHP_DIR_CQ_INT_ENB_RSVD0\t0xFFFFFFFC\n-#define DLB2_CHP_DIR_CQ_INT_ENB_EN_TIM_LOC\t0\n-#define DLB2_CHP_DIR_CQ_INT_ENB_EN_DEPTH_LOC\t1\n-#define DLB2_CHP_DIR_CQ_INT_ENB_RSVD0_LOC\t2\n-\n-#define DLB2_V2CHP_DIR_CQ_TMR_THRSH(x) \\\n-\t(0x40480000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_TMR_THRSH(x) \\\n-\t(0x40500000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_TMR_THRSH(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_TMR_THRSH(x))\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_RST 0x1\n-\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_0\t0x00000001\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_13_1\t0x00003FFE\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_RSVD0\t0xFFFFC000\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_0_LOC\t0\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_THRSH_13_1_LOC\t1\n-#define DLB2_CHP_DIR_CQ_TMR_THRSH_RSVD0_LOC\t\t14\n-\n-#define DLB2_V2CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n-\t(0x40500000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_TKN_DEPTH_SEL(x) \\\n-\t(0x40580000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_TKN_DEPTH_SEL(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_TKN_DEPTH_SEL(x))\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT\t0x0000000F\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RSVD0\t\t\t0xFFFFFFF0\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_LOC\t0\n-#define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RSVD0_LOC\t\t4\n-\n-#define DLB2_V2CHP_DIR_CQ_WD_ENB(x) \\\n-\t(0x40580000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_WD_ENB(x) \\\n-\t(0x40600000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_WD_ENB(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_WD_ENB(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_WD_ENB(x))\n-#define DLB2_CHP_DIR_CQ_WD_ENB_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_WD_ENB_WD_ENABLE\t0x00000001\n-#define DLB2_CHP_DIR_CQ_WD_ENB_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_CHP_DIR_CQ_WD_ENB_WD_ENABLE_LOC\t0\n-#define DLB2_CHP_DIR_CQ_WD_ENB_RSVD0_LOC\t1\n-\n-#define DLB2_V2CHP_DIR_CQ_WPTR(x) \\\n-\t(0x40600000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ_WPTR(x) \\\n-\t(0x40680000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ_WPTR(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_WPTR(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ_WPTR(x))\n-#define DLB2_CHP_DIR_CQ_WPTR_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_WPTR_WRITE_POINTER\t0x00001FFF\n-#define DLB2_CHP_DIR_CQ_WPTR_RSVD0\t\t0xFFFFE000\n-#define DLB2_CHP_DIR_CQ_WPTR_WRITE_POINTER_LOC\t0\n-#define DLB2_CHP_DIR_CQ_WPTR_RSVD0_LOC\t\t13\n-\n-#define DLB2_V2CHP_DIR_CQ2VAS(x) \\\n-\t(0x40680000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_DIR_CQ2VAS(x) \\\n-\t(0x40700000 + (x) * 0x1000)\n-#define DLB2_CHP_DIR_CQ2VAS(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ2VAS(x) : \\\n-\t DLB2_V2_5CHP_DIR_CQ2VAS(x))\n-#define DLB2_CHP_DIR_CQ2VAS_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ2VAS_CQ2VAS\t0x0000001F\n-#define DLB2_CHP_DIR_CQ2VAS_RSVD0\t0xFFFFFFE0\n-#define DLB2_CHP_DIR_CQ2VAS_CQ2VAS_LOC\t0\n-#define DLB2_CHP_DIR_CQ2VAS_RSVD0_LOC\t5\n-\n-#define DLB2_V2CHP_HIST_LIST_BASE(x) \\\n-\t(0x40700000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_HIST_LIST_BASE(x) \\\n-\t(0x40780000 + (x) * 0x1000)\n-#define DLB2_CHP_HIST_LIST_BASE(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_HIST_LIST_BASE(x) : \\\n-\t DLB2_V2_5CHP_HIST_LIST_BASE(x))\n-#define DLB2_CHP_HIST_LIST_BASE_RST 0x0\n-\n-#define DLB2_CHP_HIST_LIST_BASE_BASE\t\t0x00001FFF\n-#define DLB2_CHP_HIST_LIST_BASE_RSVD0\t0xFFFFE000\n-#define DLB2_CHP_HIST_LIST_BASE_BASE_LOC\t0\n-#define DLB2_CHP_HIST_LIST_BASE_RSVD0_LOC\t13\n-\n-#define DLB2_V2CHP_HIST_LIST_LIM(x) \\\n-\t(0x40780000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_HIST_LIST_LIM(x) \\\n-\t(0x40800000 + (x) * 0x1000)\n-#define DLB2_CHP_HIST_LIST_LIM(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_HIST_LIST_LIM(x) : \\\n-\t DLB2_V2_5CHP_HIST_LIST_LIM(x))\n-#define DLB2_CHP_HIST_LIST_LIM_RST 0x0\n-\n-#define DLB2_CHP_HIST_LIST_LIM_LIMIT\t0x00001FFF\n-#define DLB2_CHP_HIST_LIST_LIM_RSVD0\t0xFFFFE000\n-#define DLB2_CHP_HIST_LIST_LIM_LIMIT_LOC\t0\n-#define DLB2_CHP_HIST_LIST_LIM_RSVD0_LOC\t13\n-\n-#define DLB2_V2CHP_HIST_LIST_POP_PTR(x) \\\n-\t(0x40800000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_HIST_LIST_POP_PTR(x) \\\n-\t(0x40880000 + (x) * 0x1000)\n-#define DLB2_CHP_HIST_LIST_POP_PTR(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_HIST_LIST_POP_PTR(x) : \\\n-\t DLB2_V2_5CHP_HIST_LIST_POP_PTR(x))\n-#define DLB2_CHP_HIST_LIST_POP_PTR_RST 0x0\n-\n-#define DLB2_CHP_HIST_LIST_POP_PTR_POP_PTR\t\t0x00001FFF\n-#define DLB2_CHP_HIST_LIST_POP_PTR_GENERATION\t0x00002000\n-#define DLB2_CHP_HIST_LIST_POP_PTR_RSVD0\t\t0xFFFFC000\n-#define DLB2_CHP_HIST_LIST_POP_PTR_POP_PTR_LOC\t0\n-#define DLB2_CHP_HIST_LIST_POP_PTR_GENERATION_LOC\t13\n-#define DLB2_CHP_HIST_LIST_POP_PTR_RSVD0_LOC\t\t14\n-\n-#define DLB2_V2CHP_HIST_LIST_PUSH_PTR(x) \\\n-\t(0x40880000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_HIST_LIST_PUSH_PTR(x) \\\n-\t(0x40900000 + (x) * 0x1000)\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_HIST_LIST_PUSH_PTR(x) : \\\n-\t DLB2_V2_5CHP_HIST_LIST_PUSH_PTR(x))\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_RST 0x0\n-\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_PUSH_PTR\t\t0x00001FFF\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_GENERATION\t0x00002000\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_RSVD0\t\t0xFFFFC000\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_PUSH_PTR_LOC\t0\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_GENERATION_LOC\t13\n-#define DLB2_CHP_HIST_LIST_PUSH_PTR_RSVD0_LOC\t14\n-\n-#define DLB2_V2CHP_LDB_CQ_DEPTH(x) \\\n-\t(0x40900000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_DEPTH(x) \\\n-\t(0x40a80000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_DEPTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_DEPTH(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_DEPTH(x))\n-#define DLB2_CHP_LDB_CQ_DEPTH_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_DEPTH_DEPTH\t0x000007FF\n-#define DLB2_CHP_LDB_CQ_DEPTH_RSVD0\t0xFFFFF800\n-#define DLB2_CHP_LDB_CQ_DEPTH_DEPTH_LOC\t0\n-#define DLB2_CHP_LDB_CQ_DEPTH_RSVD0_LOC\t11\n-\n-#define DLB2_V2CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n-\t(0x40980000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_INT_DEPTH_THRSH(x) \\\n-\t(0x40b00000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_INT_DEPTH_THRSH(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_INT_DEPTH_THRSH(x))\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD\t0x000007FF\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RSVD0\t\t0xFFFFF800\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_DEPTH_THRESHOLD_LOC\t0\n-#define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RSVD0_LOC\t\t11\n-\n-#define DLB2_V2CHP_LDB_CQ_INT_ENB(x) \\\n-\t(0x40a00000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_INT_ENB(x) \\\n-\t(0x40b80000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_INT_ENB(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_INT_ENB(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_INT_ENB(x))\n-#define DLB2_CHP_LDB_CQ_INT_ENB_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_INT_ENB_EN_TIM\t0x00000001\n-#define DLB2_CHP_LDB_CQ_INT_ENB_EN_DEPTH\t0x00000002\n-#define DLB2_CHP_LDB_CQ_INT_ENB_RSVD0\t0xFFFFFFFC\n-#define DLB2_CHP_LDB_CQ_INT_ENB_EN_TIM_LOC\t0\n-#define DLB2_CHP_LDB_CQ_INT_ENB_EN_DEPTH_LOC\t1\n-#define DLB2_CHP_LDB_CQ_INT_ENB_RSVD0_LOC\t2\n-\n-#define DLB2_V2CHP_LDB_CQ_TMR_THRSH(x) \\\n-\t(0x40b00000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_TMR_THRSH(x) \\\n-\t(0x40c80000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_TMR_THRSH(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_TMR_THRSH(x))\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_RST 0x1\n-\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_0\t0x00000001\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_13_1\t0x00003FFE\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_RSVD0\t0xFFFFC000\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_0_LOC\t0\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_THRSH_13_1_LOC\t1\n-#define DLB2_CHP_LDB_CQ_TMR_THRSH_RSVD0_LOC\t\t14\n-\n-#define DLB2_V2CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n-\t(0x40b80000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_TKN_DEPTH_SEL(x) \\\n-\t(0x40d00000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_TKN_DEPTH_SEL(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_TKN_DEPTH_SEL(x))\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT\t0x0000000F\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RSVD0\t\t\t0xFFFFFFF0\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_LOC\t0\n-#define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RSVD0_LOC\t\t4\n-\n-#define DLB2_V2CHP_LDB_CQ_WD_ENB(x) \\\n-\t(0x40c00000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_WD_ENB(x) \\\n-\t(0x40d80000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_WD_ENB(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_WD_ENB(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_WD_ENB(x))\n-#define DLB2_CHP_LDB_CQ_WD_ENB_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_WD_ENB_WD_ENABLE\t0x00000001\n-#define DLB2_CHP_LDB_CQ_WD_ENB_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_CHP_LDB_CQ_WD_ENB_WD_ENABLE_LOC\t0\n-#define DLB2_CHP_LDB_CQ_WD_ENB_RSVD0_LOC\t1\n-\n-#define DLB2_V2CHP_LDB_CQ_WPTR(x) \\\n-\t(0x40c80000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ_WPTR(x) \\\n-\t(0x40e00000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ_WPTR(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_WPTR(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ_WPTR(x))\n-#define DLB2_CHP_LDB_CQ_WPTR_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_WPTR_WRITE_POINTER\t0x000007FF\n-#define DLB2_CHP_LDB_CQ_WPTR_RSVD0\t\t0xFFFFF800\n-#define DLB2_CHP_LDB_CQ_WPTR_WRITE_POINTER_LOC\t0\n-#define DLB2_CHP_LDB_CQ_WPTR_RSVD0_LOC\t\t11\n-\n-#define DLB2_V2CHP_LDB_CQ2VAS(x) \\\n-\t(0x40d00000 + (x) * 0x1000)\n-#define DLB2_V2_5CHP_LDB_CQ2VAS(x) \\\n-\t(0x40e80000 + (x) * 0x1000)\n-#define DLB2_CHP_LDB_CQ2VAS(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ2VAS(x) : \\\n-\t DLB2_V2_5CHP_LDB_CQ2VAS(x))\n-#define DLB2_CHP_LDB_CQ2VAS_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ2VAS_CQ2VAS\t0x0000001F\n-#define DLB2_CHP_LDB_CQ2VAS_RSVD0\t0xFFFFFFE0\n-#define DLB2_CHP_LDB_CQ2VAS_CQ2VAS_LOC\t0\n-#define DLB2_CHP_LDB_CQ2VAS_RSVD0_LOC\t5\n-\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_RST 0x180002\n-\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_ALARM_DIS\t\t0x00000001\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_SYND_DIS\t\t0x00000002\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNCR_ALARM_DIS\t\t0x00000004\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNC_SYND_DIS\t\t0x00000008\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_ALARM_DIS\t\t0x00000010\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_SYND_DIS\t\t0x00000020\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_ALARM_DIS\t\t0x00000040\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_SYND_DIS\t\t0x00000080\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_ALARM_DIS\t\t0x00000100\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_SYND_DIS\t\t0x00000200\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_ALARM_DIS\t\t0x00000400\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_SYND_DIS\t\t0x00000800\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_ALARM_DIS\t\t0x00001000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_SYND_DIS\t\t0x00002000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_ALARM_DIS\t\t0x00004000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_SYND_DIS\t\t0x00008000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_DLB_COR_ALARM_ENABLE\t0x00010000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE\t0x00020000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE\t0x00040000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_LDB\t\t0x00080000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_DIR\t\t0x00100000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_LDB\t0x00200000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_DIR\t0x00400000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_RSVZ0\t\t\t0xFF800000\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_ALARM_DIS_LOC\t\t0\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_COR_SYND_DIS_LOC\t\t1\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNCR_ALARM_DIS_LOC\t\t2\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_UNC_SYND_DIS_LOC\t\t3\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_ALARM_DIS_LOC\t\t4\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF0_SYND_DIS_LOC\t\t5\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_ALARM_DIS_LOC\t\t6\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF1_SYND_DIS_LOC\t\t7\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_ALARM_DIS_LOC\t\t8\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF2_SYND_DIS_LOC\t\t9\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_ALARM_DIS_LOC\t\t10\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF3_SYND_DIS_LOC\t\t11\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_ALARM_DIS_LOC\t\t12\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF4_SYND_DIS_LOC\t\t13\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_ALARM_DIS_LOC\t\t14\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_INT_INF5_SYND_DIS_LOC\t\t15\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_DLB_COR_ALARM_ENABLE_LOC\t\t16\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE_LOC\t17\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE_LOC\t18\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_LDB_LOC\t\t\t19\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_WRITE_DIR_LOC\t\t\t20\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_LDB_LOC\t\t21\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_PAD_FIRST_WRITE_DIR_LOC\t\t22\n-#define DLB2_CHP_CFG_CHP_CSR_CTRL_RSVZ0_LOC\t\t\t\t23\n-\n-#define DLB2_V2CHP_DIR_CQ_INTR_ARMED0 0x4400005c\n-#define DLB2_V2_5CHP_DIR_CQ_INTR_ARMED0 0x4400004c\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_INTR_ARMED0 : \\\n-\t DLB2_V2_5CHP_DIR_CQ_INTR_ARMED0)\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED0_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED0_ARMED\t0xFFFFFFFF\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED0_ARMED_LOC\t0\n-\n-#define DLB2_V2CHP_DIR_CQ_INTR_ARMED1 0x44000060\n-#define DLB2_V2_5CHP_DIR_CQ_INTR_ARMED1 0x44000050\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_DIR_CQ_INTR_ARMED1 : \\\n-\t DLB2_V2_5CHP_DIR_CQ_INTR_ARMED1)\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED1_RST 0x0\n-\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED1_ARMED\t0xFFFFFFFF\n-#define DLB2_CHP_DIR_CQ_INTR_ARMED1_ARMED_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084\n-#define DLB2_V2_5CHP_CFG_DIR_CQ_TIMER_CTL 0x44000088\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_CQ_TIMER_CTL : \\\n-\t DLB2_V2_5CHP_CFG_DIR_CQ_TIMER_CTL)\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_SAMPLE_INTERVAL\t0x000000FF\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_ENB\t\t\t0x00000100\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RSVZ0\t\t\t0xFFFFFE00\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_SAMPLE_INTERVAL_LOC\t0\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_ENB_LOC\t\t8\n-#define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RSVZ0_LOC\t\t9\n-\n-#define DLB2_V2CHP_CFG_DIR_WDTO_0 0x44000088\n-#define DLB2_V2_5CHP_CFG_DIR_WDTO_0 0x4400008c\n-#define DLB2_CHP_CFG_DIR_WDTO_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WDTO_0 : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WDTO_0)\n-#define DLB2_CHP_CFG_DIR_WDTO_0_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_WDTO_0_WDTO\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_DIR_WDTO_0_WDTO_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_DIR_WDTO_1 0x4400008c\n-#define DLB2_V2_5CHP_CFG_DIR_WDTO_1 0x44000090\n-#define DLB2_CHP_CFG_DIR_WDTO_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WDTO_1 : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WDTO_1)\n-#define DLB2_CHP_CFG_DIR_WDTO_1_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_WDTO_1_WDTO\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_DIR_WDTO_1_WDTO_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_DIR_WD_DISABLE0 0x44000098\n-#define DLB2_V2_5CHP_CFG_DIR_WD_DISABLE0 0x440000a4\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WD_DISABLE0 : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WD_DISABLE0)\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE0_RST 0xffffffff\n-\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE0_WD_DISABLE\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE0_WD_DISABLE_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_DIR_WD_DISABLE1 0x4400009c\n-#define DLB2_V2_5CHP_CFG_DIR_WD_DISABLE1 0x440000a8\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WD_DISABLE1 : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WD_DISABLE1)\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE1_RST 0xffffffff\n-\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE1_WD_DISABLE\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_DIR_WD_DISABLE1_WD_DISABLE_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0\n-#define DLB2_V2_5CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000b0\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WD_ENB_INTERVAL : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WD_ENB_INTERVAL)\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_SAMPLE_INTERVAL\t0x0FFFFFFF\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_ENB\t\t\t0x10000000\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RSVZ0\t\t0xE0000000\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_SAMPLE_INTERVAL_LOC\t0\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_ENB_LOC\t\t28\n-#define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RSVZ0_LOC\t\t29\n-\n-#define DLB2_V2CHP_CFG_DIR_WD_THRESHOLD 0x440000ac\n-#define DLB2_V2_5CHP_CFG_DIR_WD_THRESHOLD 0x440000c0\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_DIR_WD_THRESHOLD : \\\n-\t DLB2_V2_5CHP_CFG_DIR_WD_THRESHOLD)\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RST 0x0\n-\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_WD_THRESHOLD\t0x000000FF\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RSVZ0\t\t0xFFFFFF00\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_WD_THRESHOLD_LOC\t0\n-#define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RSVZ0_LOC\t\t8\n-\n-#define DLB2_V2CHP_LDB_CQ_INTR_ARMED0 0x440000b0\n-#define DLB2_V2_5CHP_LDB_CQ_INTR_ARMED0 0x440000c4\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_INTR_ARMED0 : \\\n-\t DLB2_V2_5CHP_LDB_CQ_INTR_ARMED0)\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED0_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED0_ARMED\t0xFFFFFFFF\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED0_ARMED_LOC\t0\n-\n-#define DLB2_V2CHP_LDB_CQ_INTR_ARMED1 0x440000b4\n-#define DLB2_V2_5CHP_LDB_CQ_INTR_ARMED1 0x440000c8\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_LDB_CQ_INTR_ARMED1 : \\\n-\t DLB2_V2_5CHP_LDB_CQ_INTR_ARMED1)\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED1_RST 0x0\n-\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED1_ARMED\t0xFFFFFFFF\n-#define DLB2_CHP_LDB_CQ_INTR_ARMED1_ARMED_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8\n-#define DLB2_V2_5CHP_CFG_LDB_CQ_TIMER_CTL 0x440000ec\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_CQ_TIMER_CTL : \\\n-\t DLB2_V2_5CHP_CFG_LDB_CQ_TIMER_CTL)\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_SAMPLE_INTERVAL\t0x000000FF\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_ENB\t\t\t0x00000100\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RSVZ0\t\t\t0xFFFFFE00\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_SAMPLE_INTERVAL_LOC\t0\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_ENB_LOC\t\t8\n-#define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RSVZ0_LOC\t\t9\n-\n-#define DLB2_V2CHP_CFG_LDB_WDTO_0 0x440000dc\n-#define DLB2_V2_5CHP_CFG_LDB_WDTO_0 0x440000f0\n-#define DLB2_CHP_CFG_LDB_WDTO_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WDTO_0 : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WDTO_0)\n-#define DLB2_CHP_CFG_LDB_WDTO_0_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_WDTO_0_WDTO\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_LDB_WDTO_0_WDTO_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_LDB_WDTO_1 0x440000e0\n-#define DLB2_V2_5CHP_CFG_LDB_WDTO_1 0x440000f4\n-#define DLB2_CHP_CFG_LDB_WDTO_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WDTO_1 : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WDTO_1)\n-#define DLB2_CHP_CFG_LDB_WDTO_1_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_WDTO_1_WDTO\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_LDB_WDTO_1_WDTO_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_LDB_WD_DISABLE0 0x440000ec\n-#define DLB2_V2_5CHP_CFG_LDB_WD_DISABLE0 0x44000100\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WD_DISABLE0 : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WD_DISABLE0)\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE0_RST 0xffffffff\n-\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE0_WD_DISABLE\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE0_WD_DISABLE_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_LDB_WD_DISABLE1 0x440000f0\n-#define DLB2_V2_5CHP_CFG_LDB_WD_DISABLE1 0x44000104\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WD_DISABLE1 : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WD_DISABLE1)\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE1_RST 0xffffffff\n-\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE1_WD_DISABLE\t0xFFFFFFFF\n-#define DLB2_CHP_CFG_LDB_WD_DISABLE1_WD_DISABLE_LOC\t0\n-\n-#define DLB2_V2CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4\n-#define DLB2_V2_5CHP_CFG_LDB_WD_ENB_INTERVAL 0x44000108\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WD_ENB_INTERVAL : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WD_ENB_INTERVAL)\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_SAMPLE_INTERVAL\t0x0FFFFFFF\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_ENB\t\t\t0x10000000\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RSVZ0\t\t0xE0000000\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_SAMPLE_INTERVAL_LOC\t0\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_ENB_LOC\t\t28\n-#define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RSVZ0_LOC\t\t29\n-\n-#define DLB2_V2CHP_CFG_LDB_WD_THRESHOLD 0x44000100\n-#define DLB2_V2_5CHP_CFG_LDB_WD_THRESHOLD 0x44000114\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CHP_CFG_LDB_WD_THRESHOLD : \\\n-\t DLB2_V2_5CHP_CFG_LDB_WD_THRESHOLD)\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RST 0x0\n-\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_WD_THRESHOLD\t0x000000FF\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RSVZ0\t\t0xFFFFFF00\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_WD_THRESHOLD_LOC\t0\n-#define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RSVZ0_LOC\t\t8\n-\n-#define DLB2_CHP_SMON_COMPARE0 0x4c000000\n-#define DLB2_CHP_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_CHP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_CHP_SMON_COMPARE1 0x4c000004\n-#define DLB2_CHP_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_CHP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_CHP_SMON_CFG0 0x4c000008\n-#define DLB2_CHP_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_CHP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_CHP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_CHP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_CHP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_CHP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_CHP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_CHP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_CHP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_CHP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_CHP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_CHP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_CHP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_CHP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_CHP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_CHP_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_CHP_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_CHP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_CHP_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n-#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_CHP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_CHP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_CHP_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_CHP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_CHP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_CHP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_CHP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_CHP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n-#define DLB2_CHP_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_CHP_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n-#define DLB2_CHP_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n-#define DLB2_CHP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_CHP_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n-#define DLB2_CHP_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_CHP_SMON_CFG1 0x4c00000c\n-#define DLB2_CHP_SMON_CFG1_RST 0x0\n-\n-#define DLB2_CHP_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_CHP_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_CHP_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_CHP_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_CHP_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_CHP_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_CHP_SMON_ACTIVITYCNTR0 0x4c000010\n-#define DLB2_CHP_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_CHP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_CHP_SMON_ACTIVITYCNTR1 0x4c000014\n-#define DLB2_CHP_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_CHP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_CHP_SMON_MAX_TMR 0x4c000018\n-#define DLB2_CHP_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_CHP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_CHP_SMON_TMR 0x4c00001c\n-#define DLB2_CHP_SMON_TMR_RST 0x0\n-\n-#define DLB2_CHP_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_CHP_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_CHP_CTRL_DIAG_02 0x4c000028\n-#define DLB2_CHP_CTRL_DIAG_02_RST 0x1555\n-\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2\t0x00000001\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2\t0x00000002\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2 0x04\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2 0x08\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2 0x0010\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2 0x0020\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2    0x0040\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2    0x0080\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2\t 0x0100\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2\t 0x0200\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2\t0x0400\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2\t0x0800\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2    0x1000\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2    0x2000\n-#define DLB2_CHP_CTRL_DIAG_02_RSVD0_V2\t\t\t\t    0xFFFFC000\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_LOC\t    0\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_LOC\t    1\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_LOC 2\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_LOC 3\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_LOC 4\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_LOC 5\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_LOC    6\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_LOC    7\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_LOC\t  8\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_LOC\t  9\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_LOC\t  10\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_LOC\t  11\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_LOC 12\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_LOC 13\n-#define DLB2_CHP_CTRL_DIAG_02_RSVD0_V2_LOC\t\t\t\t  14\n-\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_5\t     0x00000001\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_5\t     0x00000002\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_5  4\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_5  8\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x10\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_5 0x20\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_5\t0x0040\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_5\t0x0080\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x00000100\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_5 0x00000200\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_5 0x0400\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_5 0x0800\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_5 0x1000\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_5 0x2000\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOKEN_QB_STATUS_SIZE_V2_5\t    0x0001C000\n-#define DLB2_CHP_CTRL_DIAG_02_FREELIST_SIZE_V2_5\t\t    0xFFFE0000\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_EMPTY_V2_5_LOC 0\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_CREDIT_STATUS_AFULL_V2_5_LOC 1\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC 2\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_OUT_HCW_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 3\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC 4\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_AP_CMP_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 5\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC    6\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOK_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC 7\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC\t    8\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_ROP_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC\t    9\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_EMPTY_V2_5_LOC   10\n-#define DLB2_CHP_CTRL_DIAG_02_QED_TO_CQ_PIPE_CREDIT_STATUS_AFULL_V2_5_LOC   11\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_EMPTY_V2_5_LOC 12\n-#define DLB2_CHP_CTRL_DIAG_02_EGRESS_LSP_TOKEN_CREDIT_STATUS_AFULL_V2_5_LOC 13\n-#define DLB2_CHP_CTRL_DIAG_02_CHP_LSP_TOKEN_QB_STATUS_SIZE_V2_5_LOC\t    14\n-#define DLB2_CHP_CTRL_DIAG_02_FREELIST_SIZE_V2_5_LOC\t\t\t    17\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0 0x54000000\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfefcfaf8\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI0\t0x000000FF\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI1\t0x0000FF00\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI2\t0x00FF0000\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI3\t0xFF000000\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI0_LOC\t0\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI1_LOC\t8\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI2_LOC\t16\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_PRI3_LOC\t24\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1 0x54000004\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RST 0x0\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RSVZ0\t0xFFFFFFFF\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RSVZ0_LOC\t0\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x54000008\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0\t0x000000FF\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1\t0x0000FF00\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2\t0x00FF0000\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3\t0xFF000000\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0_LOC\t0\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1_LOC\t8\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2_LOC\t16\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3_LOC\t24\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x5400000c\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n-\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0\t0xFFFFFFFF\n-#define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0_LOC\t0\n-\n-#define DLB2_DP_DIR_CSR_CTRL 0x54000010\n-#define DLB2_DP_DIR_CSR_CTRL_RST 0x0\n-\n-#define DLB2_DP_DIR_CSR_CTRL_INT_COR_ALARM_DIS\t0x00000001\n-#define DLB2_DP_DIR_CSR_CTRL_INT_COR_SYND_DIS\t0x00000002\n-#define DLB2_DP_DIR_CSR_CTRL_INT_UNCR_ALARM_DIS\t0x00000004\n-#define DLB2_DP_DIR_CSR_CTRL_INT_UNC_SYND_DIS\t0x00000008\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_ALARM_DIS\t0x00000010\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_SYND_DIS\t0x00000020\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_ALARM_DIS\t0x00000040\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_SYND_DIS\t0x00000080\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_ALARM_DIS\t0x00000100\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_SYND_DIS\t0x00000200\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_ALARM_DIS\t0x00000400\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_SYND_DIS\t0x00000800\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_ALARM_DIS\t0x00001000\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_SYND_DIS\t0x00002000\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_ALARM_DIS\t0x00004000\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_SYND_DIS\t0x00008000\n-#define DLB2_DP_DIR_CSR_CTRL_RSVZ0\t\t\t0xFFFF0000\n-#define DLB2_DP_DIR_CSR_CTRL_INT_COR_ALARM_DIS_LOC\t0\n-#define DLB2_DP_DIR_CSR_CTRL_INT_COR_SYND_DIS_LOC\t1\n-#define DLB2_DP_DIR_CSR_CTRL_INT_UNCR_ALARM_DIS_LOC\t2\n-#define DLB2_DP_DIR_CSR_CTRL_INT_UNC_SYND_DIS_LOC\t3\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_ALARM_DIS_LOC\t4\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF0_SYND_DIS_LOC\t5\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_ALARM_DIS_LOC\t6\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF1_SYND_DIS_LOC\t7\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_ALARM_DIS_LOC\t8\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF2_SYND_DIS_LOC\t9\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_ALARM_DIS_LOC\t10\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF3_SYND_DIS_LOC\t11\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_ALARM_DIS_LOC\t12\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF4_SYND_DIS_LOC\t13\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_ALARM_DIS_LOC\t14\n-#define DLB2_DP_DIR_CSR_CTRL_INT_INF5_SYND_DIS_LOC\t15\n-#define DLB2_DP_DIR_CSR_CTRL_RSVZ0_LOC\t\t16\n-\n-#define DLB2_DP_SMON_ACTIVITYCNTR0 0x5c000058\n-#define DLB2_DP_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_DP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_DP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_DP_SMON_ACTIVITYCNTR1 0x5c00005c\n-#define DLB2_DP_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_DP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_DP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_DP_SMON_COMPARE0 0x5c000060\n-#define DLB2_DP_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_DP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_DP_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_DP_SMON_COMPARE1 0x5c000064\n-#define DLB2_DP_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_DP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_DP_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_DP_SMON_CFG0 0x5c000068\n-#define DLB2_DP_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_DP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_DP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_DP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_DP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_DP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_DP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_DP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_DP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_DP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_DP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_DP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_DP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_DP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_DP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_DP_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_DP_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n-#define DLB2_DP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t1\n-#define DLB2_DP_SMON_CFG0_RSVZ0_LOC\t\t\t2\n-#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_DP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_DP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_DP_SMON_CFG0_SMON_MODE_LOC\t\t12\n-#define DLB2_DP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t16\n-#define DLB2_DP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_DP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t18\n-#define DLB2_DP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t19\n-#define DLB2_DP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_DP_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n-#define DLB2_DP_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_DP_SMON_CFG0_RSVZ1_LOC\t\t\t23\n-#define DLB2_DP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_DP_SMON_CFG0_RSVZ2_LOC\t\t\t29\n-#define DLB2_DP_SMON_CFG0_VERSION_LOC\t\t30\n-\n-#define DLB2_DP_SMON_CFG1 0x5c00006c\n-#define DLB2_DP_SMON_CFG1_RST 0x0\n-\n-#define DLB2_DP_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_DP_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_DP_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_DP_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_DP_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_DP_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_DP_SMON_MAX_TMR 0x5c000070\n-#define DLB2_DP_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_DP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_DP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_DP_SMON_TMR 0x5c000074\n-#define DLB2_DP_SMON_TMR_RST 0x0\n-\n-#define DLB2_DP_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_DP_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_DQED_SMON_ACTIVITYCNTR0 0x6c000024\n-#define DLB2_DQED_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_DQED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_DQED_SMON_ACTIVITYCNTR1 0x6c000028\n-#define DLB2_DQED_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_DQED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_DQED_SMON_COMPARE0 0x6c00002c\n-#define DLB2_DQED_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_DQED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_DQED_SMON_COMPARE1 0x6c000030\n-#define DLB2_DQED_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_DQED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_DQED_SMON_CFG0 0x6c000034\n-#define DLB2_DQED_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_DQED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_DQED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_DQED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_DQED_SMON_CFG0_SMON_MODE\t\t0x0000F000\n-#define DLB2_DQED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_DQED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_DQED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_DQED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_DQED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_DQED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_DQED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_DQED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_DQED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_DQED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_DQED_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_DQED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_DQED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_DQED_SMON_CFG0_RSVZ0_LOC\t\t\t2\n-#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_DQED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_DQED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_DQED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_DQED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_DQED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_DQED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_DQED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_DQED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_DQED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_DQED_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_DQED_SMON_CFG0_RSVZ1_LOC\t\t\t23\n-#define DLB2_DQED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_DQED_SMON_CFG0_RSVZ2_LOC\t\t\t29\n-#define DLB2_DQED_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_DQED_SMON_CFG1 0x6c000038\n-#define DLB2_DQED_SMON_CFG1_RST 0x0\n-\n-#define DLB2_DQED_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_DQED_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_DQED_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_DQED_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_DQED_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_DQED_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_DQED_SMON_MAX_TMR 0x6c00003c\n-#define DLB2_DQED_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_DQED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_DQED_SMON_TMR 0x6c000040\n-#define DLB2_DQED_SMON_TMR_RST 0x0\n-\n-#define DLB2_DQED_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_DQED_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_QED_SMON_ACTIVITYCNTR0 0x7c000024\n-#define DLB2_QED_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_QED_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_QED_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_QED_SMON_ACTIVITYCNTR1 0x7c000028\n-#define DLB2_QED_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_QED_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_QED_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_QED_SMON_COMPARE0 0x7c00002c\n-#define DLB2_QED_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_QED_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_QED_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_QED_SMON_COMPARE1 0x7c000030\n-#define DLB2_QED_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_QED_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_QED_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_QED_SMON_CFG0 0x7c000034\n-#define DLB2_QED_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_QED_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_QED_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_QED_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_QED_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_QED_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_QED_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_QED_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_QED_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_QED_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_QED_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_QED_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_QED_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_QED_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_QED_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_QED_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_QED_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_QED_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_QED_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n-#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_QED_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_QED_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_QED_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_QED_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_QED_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_QED_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_QED_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_QED_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n-#define DLB2_QED_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_QED_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n-#define DLB2_QED_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n-#define DLB2_QED_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_QED_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n-#define DLB2_QED_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_QED_SMON_CFG1 0x7c000038\n-#define DLB2_QED_SMON_CFG1_RST 0x0\n-\n-#define DLB2_QED_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_QED_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_QED_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_QED_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_QED_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_QED_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_QED_SMON_MAX_TMR 0x7c00003c\n-#define DLB2_QED_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_QED_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_QED_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_QED_SMON_TMR 0x7c000040\n-#define DLB2_QED_SMON_TMR_RST 0x0\n-\n-#define DLB2_QED_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_QED_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x74000000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI0\t0x000000FF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI1\t0x0000FF00\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI2\t0x00FF0000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI3\t0xFF000000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI0_LOC\t0\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI1_LOC\t8\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI2_LOC\t16\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_PRI3_LOC\t24\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x74000004\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RSVZ0\t0xFFFFFFFF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RSVZ0_LOC\t0\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x74000008\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI0\t0x000000FF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI1\t0x0000FF00\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI2\t0x00FF0000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI3\t0xFF000000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI0_LOC\t0\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI1_LOC\t8\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI2_LOC\t16\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_0_PRI3_LOC\t24\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x7400000c\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RSVZ0\t0xFFFFFFFF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RSVZ0_LOC\t0\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x74000010\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0\t0x000000FF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1\t0x0000FF00\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2\t0x00FF0000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3\t0xFF000000\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI0_LOC\t0\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI1_LOC\t8\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI2_LOC\t16\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_PRI3_LOC\t24\n-\n-#define DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014\n-#define DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x74000014\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 : \\\n-\t DLB2_V2_5NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1)\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0\n-\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0\t0xFFFFFFFF\n-#define DLB2_NALB_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RSVZ0_LOC\t0\n-\n-#define DLB2_NALB_SMON_ACTIVITYCNTR0 0x8c000064\n-#define DLB2_NALB_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_NALB_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_NALB_SMON_ACTIVITYCNTR1 0x8c000068\n-#define DLB2_NALB_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_NALB_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_NALB_SMON_COMPARE0 0x8c00006c\n-#define DLB2_NALB_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_NALB_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_NALB_SMON_COMPARE1 0x8c000070\n-#define DLB2_NALB_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_NALB_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_NALB_SMON_CFG0 0x8c000074\n-#define DLB2_NALB_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_NALB_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_NALB_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_NALB_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_NALB_SMON_CFG0_SMON_MODE\t\t0x0000F000\n-#define DLB2_NALB_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_NALB_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_NALB_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_NALB_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_NALB_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_NALB_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_NALB_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_NALB_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_NALB_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_NALB_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_NALB_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_NALB_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_NALB_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_NALB_SMON_CFG0_RSVZ0_LOC\t\t\t2\n-#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_NALB_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_NALB_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_NALB_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_NALB_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_NALB_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_NALB_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_NALB_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_NALB_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_NALB_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_NALB_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_NALB_SMON_CFG0_RSVZ1_LOC\t\t\t23\n-#define DLB2_NALB_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_NALB_SMON_CFG0_RSVZ2_LOC\t\t\t29\n-#define DLB2_NALB_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_NALB_SMON_CFG1 0x8c000078\n-#define DLB2_NALB_SMON_CFG1_RST 0x0\n-\n-#define DLB2_NALB_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_NALB_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_NALB_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_NALB_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_NALB_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_NALB_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_NALB_SMON_MAX_TMR 0x8c00007c\n-#define DLB2_NALB_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_NALB_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_NALB_SMON_TMR 0x8c000080\n-#define DLB2_NALB_SMON_TMR_RST 0x0\n-\n-#define DLB2_NALB_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_NALB_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_V2RO_GRP_0_SLT_SHFT(x) \\\n-\t(0x96000000 + (x) * 0x4)\n-#define DLB2_V2_5RO_GRP_0_SLT_SHFT(x) \\\n-\t(0x86000000 + (x) * 0x4)\n-#define DLB2_RO_GRP_0_SLT_SHFT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2RO_GRP_0_SLT_SHFT(x) : \\\n-\t DLB2_V2_5RO_GRP_0_SLT_SHFT(x))\n-#define DLB2_RO_GRP_0_SLT_SHFT_RST 0x0\n-\n-#define DLB2_RO_GRP_0_SLT_SHFT_CHANGE\t0x000003FF\n-#define DLB2_RO_GRP_0_SLT_SHFT_RSVD0\t\t0xFFFFFC00\n-#define DLB2_RO_GRP_0_SLT_SHFT_CHANGE_LOC\t0\n-#define DLB2_RO_GRP_0_SLT_SHFT_RSVD0_LOC\t10\n-\n-#define DLB2_V2RO_GRP_1_SLT_SHFT(x) \\\n-\t(0x96010000 + (x) * 0x4)\n-#define DLB2_V2_5RO_GRP_1_SLT_SHFT(x) \\\n-\t(0x86010000 + (x) * 0x4)\n-#define DLB2_RO_GRP_1_SLT_SHFT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2RO_GRP_1_SLT_SHFT(x) : \\\n-\t DLB2_V2_5RO_GRP_1_SLT_SHFT(x))\n-#define DLB2_RO_GRP_1_SLT_SHFT_RST 0x0\n-\n-#define DLB2_RO_GRP_1_SLT_SHFT_CHANGE\t0x000003FF\n-#define DLB2_RO_GRP_1_SLT_SHFT_RSVD0\t\t0xFFFFFC00\n-#define DLB2_RO_GRP_1_SLT_SHFT_CHANGE_LOC\t0\n-#define DLB2_RO_GRP_1_SLT_SHFT_RSVD0_LOC\t10\n-\n-#define DLB2_V2RO_GRP_SN_MODE 0x94000000\n-#define DLB2_V2_5RO_GRP_SN_MODE 0x84000000\n-#define DLB2_RO_GRP_SN_MODE(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2RO_GRP_SN_MODE : \\\n-\t DLB2_V2_5RO_GRP_SN_MODE)\n-#define DLB2_RO_GRP_SN_MODE_RST 0x0\n-\n-#define DLB2_RO_GRP_SN_MODE_SN_MODE_0\t0x00000007\n-#define DLB2_RO_GRP_SN_MODE_RSZV0\t\t0x000000F8\n-#define DLB2_RO_GRP_SN_MODE_SN_MODE_1\t0x00000700\n-#define DLB2_RO_GRP_SN_MODE_RSZV1\t\t0xFFFFF800\n-#define DLB2_RO_GRP_SN_MODE_SN_MODE_0_LOC\t0\n-#define DLB2_RO_GRP_SN_MODE_RSZV0_LOC\t3\n-#define DLB2_RO_GRP_SN_MODE_SN_MODE_1_LOC\t8\n-#define DLB2_RO_GRP_SN_MODE_RSZV1_LOC\t11\n-\n-#define DLB2_V2RO_CFG_CTRL_GENERAL_0 0x9c000000\n-#define DLB2_V2_5RO_CFG_CTRL_GENERAL_0 0x8c000000\n-#define DLB2_RO_CFG_CTRL_GENERAL_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2RO_CFG_CTRL_GENERAL_0 : \\\n-\t DLB2_V2_5RO_CFG_CTRL_GENERAL_0)\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_RST 0x0\n-\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_UNIT_SINGLE_STEP_MODE\t0x00000001\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_RR_EN\t\t\t0x00000002\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_RSZV0\t\t\t0xFFFFFFFC\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_UNIT_SINGLE_STEP_MODE_LOC\t0\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_RR_EN_LOC\t\t\t1\n-#define DLB2_RO_CFG_CTRL_GENERAL_0_RSZV0_LOC\t\t\t2\n-\n-#define DLB2_RO_SMON_ACTIVITYCNTR0 0x9c000030\n-#define DLB2_RO_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_RO_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_RO_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_RO_SMON_ACTIVITYCNTR1 0x9c000034\n-#define DLB2_RO_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_RO_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_RO_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_RO_SMON_COMPARE0 0x9c000038\n-#define DLB2_RO_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_RO_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_RO_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_RO_SMON_COMPARE1 0x9c00003c\n-#define DLB2_RO_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_RO_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_RO_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_RO_SMON_CFG0 0x9c000040\n-#define DLB2_RO_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_RO_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_RO_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_RO_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_RO_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_RO_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_RO_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_RO_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_RO_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_RO_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_RO_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_RO_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_RO_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_RO_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_RO_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_RO_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_RO_SMON_CFG0_SMON_ENABLE_LOC\t\t0\n-#define DLB2_RO_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t1\n-#define DLB2_RO_SMON_CFG0_RSVZ0_LOC\t\t\t2\n-#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_RO_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_RO_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_RO_SMON_CFG0_SMON_MODE_LOC\t\t12\n-#define DLB2_RO_SMON_CFG0_STOPCOUNTEROVFL_LOC\t16\n-#define DLB2_RO_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_RO_SMON_CFG0_STATCOUNTER0OVFL_LOC\t18\n-#define DLB2_RO_SMON_CFG0_STATCOUNTER1OVFL_LOC\t19\n-#define DLB2_RO_SMON_CFG0_STOPTIMEROVFL_LOC\t\t20\n-#define DLB2_RO_SMON_CFG0_INTTIMEROVFL_LOC\t\t21\n-#define DLB2_RO_SMON_CFG0_STATTIMEROVFL_LOC\t\t22\n-#define DLB2_RO_SMON_CFG0_RSVZ1_LOC\t\t\t23\n-#define DLB2_RO_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_RO_SMON_CFG0_RSVZ2_LOC\t\t\t29\n-#define DLB2_RO_SMON_CFG0_VERSION_LOC\t\t30\n-\n-#define DLB2_RO_SMON_CFG1 0x9c000044\n-#define DLB2_RO_SMON_CFG1_RST 0x0\n-\n-#define DLB2_RO_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_RO_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_RO_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_RO_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_RO_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_RO_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_RO_SMON_MAX_TMR 0x9c000048\n-#define DLB2_RO_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_RO_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_RO_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_RO_SMON_TMR 0x9c00004c\n-#define DLB2_RO_SMON_TMR_RST 0x0\n-\n-#define DLB2_RO_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_RO_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_V2LSP_CQ2PRIOV(x) \\\n-\t(0xa0000000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ2PRIOV(x) \\\n-\t(0x90000000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ2PRIOV(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ2PRIOV(x) : \\\n-\t DLB2_V2_5LSP_CQ2PRIOV(x))\n-#define DLB2_LSP_CQ2PRIOV_RST 0x0\n-\n-#define DLB2_LSP_CQ2PRIOV_PRIO\t0x00FFFFFF\n-#define DLB2_LSP_CQ2PRIOV_V\t\t0xFF000000\n-#define DLB2_LSP_CQ2PRIOV_PRIO_LOC\t0\n-#define DLB2_LSP_CQ2PRIOV_V_LOC\t24\n-\n-#define DLB2_V2LSP_CQ2QID0(x) \\\n-\t(0xa0080000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ2QID0(x) \\\n-\t(0x90080000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ2QID0(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ2QID0(x) : \\\n-\t DLB2_V2_5LSP_CQ2QID0(x))\n-#define DLB2_LSP_CQ2QID0_RST 0x0\n-\n-#define DLB2_LSP_CQ2QID0_QID_P0\t0x0000007F\n-#define DLB2_LSP_CQ2QID0_RSVD3\t0x00000080\n-#define DLB2_LSP_CQ2QID0_QID_P1\t0x00007F00\n-#define DLB2_LSP_CQ2QID0_RSVD2\t0x00008000\n-#define DLB2_LSP_CQ2QID0_QID_P2\t0x007F0000\n-#define DLB2_LSP_CQ2QID0_RSVD1\t0x00800000\n-#define DLB2_LSP_CQ2QID0_QID_P3\t0x7F000000\n-#define DLB2_LSP_CQ2QID0_RSVD0\t0x80000000\n-#define DLB2_LSP_CQ2QID0_QID_P0_LOC\t0\n-#define DLB2_LSP_CQ2QID0_RSVD3_LOC\t7\n-#define DLB2_LSP_CQ2QID0_QID_P1_LOC\t8\n-#define DLB2_LSP_CQ2QID0_RSVD2_LOC\t15\n-#define DLB2_LSP_CQ2QID0_QID_P2_LOC\t16\n-#define DLB2_LSP_CQ2QID0_RSVD1_LOC\t23\n-#define DLB2_LSP_CQ2QID0_QID_P3_LOC\t24\n-#define DLB2_LSP_CQ2QID0_RSVD0_LOC\t31\n-\n-#define DLB2_V2LSP_CQ2QID1(x) \\\n-\t(0xa0100000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ2QID1(x) \\\n-\t(0x90100000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ2QID1(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ2QID1(x) : \\\n-\t DLB2_V2_5LSP_CQ2QID1(x))\n-#define DLB2_LSP_CQ2QID1_RST 0x0\n-\n-#define DLB2_LSP_CQ2QID1_QID_P4\t0x0000007F\n-#define DLB2_LSP_CQ2QID1_RSVD3\t0x00000080\n-#define DLB2_LSP_CQ2QID1_QID_P5\t0x00007F00\n-#define DLB2_LSP_CQ2QID1_RSVD2\t0x00008000\n-#define DLB2_LSP_CQ2QID1_QID_P6\t0x007F0000\n-#define DLB2_LSP_CQ2QID1_RSVD1\t0x00800000\n-#define DLB2_LSP_CQ2QID1_QID_P7\t0x7F000000\n-#define DLB2_LSP_CQ2QID1_RSVD0\t0x80000000\n-#define DLB2_LSP_CQ2QID1_QID_P4_LOC\t0\n-#define DLB2_LSP_CQ2QID1_RSVD3_LOC\t7\n-#define DLB2_LSP_CQ2QID1_QID_P5_LOC\t8\n-#define DLB2_LSP_CQ2QID1_RSVD2_LOC\t15\n-#define DLB2_LSP_CQ2QID1_QID_P6_LOC\t16\n-#define DLB2_LSP_CQ2QID1_RSVD1_LOC\t23\n-#define DLB2_LSP_CQ2QID1_QID_P7_LOC\t24\n-#define DLB2_LSP_CQ2QID1_RSVD0_LOC\t31\n-\n-#define DLB2_V2LSP_CQ_DIR_DSBL(x) \\\n-\t(0xa0180000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_DIR_DSBL(x) \\\n-\t(0x90180000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_DIR_DSBL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_DIR_DSBL(x) : \\\n-\t DLB2_V2_5LSP_CQ_DIR_DSBL(x))\n-#define DLB2_LSP_CQ_DIR_DSBL_RST 0x1\n-\n-#define DLB2_LSP_CQ_DIR_DSBL_DISABLED\t0x00000001\n-#define DLB2_LSP_CQ_DIR_DSBL_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_LSP_CQ_DIR_DSBL_DISABLED_LOC\t0\n-#define DLB2_LSP_CQ_DIR_DSBL_RSVD0_LOC\t1\n-\n-#define DLB2_V2LSP_CQ_DIR_TKN_CNT(x) \\\n-\t(0xa0200000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_DIR_TKN_CNT(x) \\\n-\t(0x90200000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_DIR_TKN_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_DIR_TKN_CNT(x) : \\\n-\t DLB2_V2_5LSP_CQ_DIR_TKN_CNT(x))\n-#define DLB2_LSP_CQ_DIR_TKN_CNT_RST 0x0\n-\n-#define DLB2_LSP_CQ_DIR_TKN_CNT_COUNT\t0x00001FFF\n-#define DLB2_LSP_CQ_DIR_TKN_CNT_RSVD0\t0xFFFFE000\n-#define DLB2_LSP_CQ_DIR_TKN_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_CQ_DIR_TKN_CNT_RSVD0_LOC\t13\n-\n-#define DLB2_V2LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n-\t(0xa0280000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \\\n-\t(0x90280000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) : \\\n-\t DLB2_V2_5LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x))\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0\n-\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2\t0x0000000F\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2\t0x00000010\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_IGNORE_DEPTH_V2\t0x00000020\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2\t\t0xFFFFFFC0\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_LOC\t0\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_LOC\t4\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_IGNORE_DEPTH_V2_LOC\t5\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_LOC\t\t6\n-\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_5 0x0000000F\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_5\t0x00000010\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_5\t\t0xFFFFFFE0\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2_5_LOC\t0\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_DISABLE_WB_OPT_V2_5_LOC\t4\n-#define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RSVD0_V2_5_LOC\t\t5\n-\n-#define DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n-\t(0xa0300000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTL(x) \\\n-\t(0x90300000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTL(x) : \\\n-\t DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTL(x))\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0\n-\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n-\t(0xa0380000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTH(x) \\\n-\t(0x90380000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_DIR_TOT_SCH_CNTH(x) : \\\n-\t DLB2_V2_5LSP_CQ_DIR_TOT_SCH_CNTH(x))\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0\n-\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_CQ_LDB_DSBL(x) \\\n-\t(0xa0400000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_DSBL(x) \\\n-\t(0x90400000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_DSBL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_DSBL(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_DSBL(x))\n-#define DLB2_LSP_CQ_LDB_DSBL_RST 0x1\n-\n-#define DLB2_LSP_CQ_LDB_DSBL_DISABLED\t0x00000001\n-#define DLB2_LSP_CQ_LDB_DSBL_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_LSP_CQ_LDB_DSBL_DISABLED_LOC\t0\n-#define DLB2_LSP_CQ_LDB_DSBL_RSVD0_LOC\t1\n-\n-#define DLB2_V2LSP_CQ_LDB_INFL_CNT(x) \\\n-\t(0xa0480000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_INFL_CNT(x) \\\n-\t(0x90480000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_INFL_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_INFL_CNT(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_INFL_CNT(x))\n-#define DLB2_LSP_CQ_LDB_INFL_CNT_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_INFL_CNT_COUNT\t0x00000FFF\n-#define DLB2_LSP_CQ_LDB_INFL_CNT_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_CQ_LDB_INFL_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_CQ_LDB_INFL_CNT_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_CQ_LDB_INFL_LIM(x) \\\n-\t(0xa0500000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_INFL_LIM(x) \\\n-\t(0x90500000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_INFL_LIM(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_INFL_LIM(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_INFL_LIM(x))\n-#define DLB2_LSP_CQ_LDB_INFL_LIM_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT\t0x00000FFF\n-#define DLB2_LSP_CQ_LDB_INFL_LIM_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT_LOC\t0\n-#define DLB2_LSP_CQ_LDB_INFL_LIM_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_CQ_LDB_TKN_CNT(x) \\\n-\t(0xa0580000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_TKN_CNT(x) \\\n-\t(0x90600000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_TKN_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_TKN_CNT(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_TKN_CNT(x))\n-#define DLB2_LSP_CQ_LDB_TKN_CNT_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_TKN_CNT_TOKEN_COUNT\t0x000007FF\n-#define DLB2_LSP_CQ_LDB_TKN_CNT_RSVD0\t0xFFFFF800\n-#define DLB2_LSP_CQ_LDB_TKN_CNT_TOKEN_COUNT_LOC\t0\n-#define DLB2_LSP_CQ_LDB_TKN_CNT_RSVD0_LOC\t\t11\n-\n-#define DLB2_V2LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n-\t(0xa0600000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_TKN_DEPTH_SEL(x) \\\n-\t(0x90680000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_TKN_DEPTH_SEL(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_TKN_DEPTH_SEL(x))\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2\t0x0000000F\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_IGNORE_DEPTH_V2\t0x00000010\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2\t\t0xFFFFFFE0\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_LOC\t0\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_IGNORE_DEPTH_V2_LOC\t\t4\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_LOC\t\t\t5\n-\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_5\t0x0000000F\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_5\t\t0xFFFFFFF0\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2_5_LOC\t0\n-#define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RSVD0_V2_5_LOC\t\t\t4\n-\n-#define DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n-\t(0xa0680000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTL(x) \\\n-\t(0x90700000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTL(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTL(x))\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n-\t(0xa0700000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTH(x) \\\n-\t(0x90780000 + (x) * 0x1000)\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CQ_LDB_TOT_SCH_CNTH(x) : \\\n-\t DLB2_V2_5LSP_CQ_LDB_TOT_SCH_CNTH(x))\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0\n-\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_DIR_MAX_DEPTH(x) \\\n-\t(0xa0780000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_DIR_MAX_DEPTH(x) \\\n-\t(0x90800000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_DIR_MAX_DEPTH(x) : \\\n-\t DLB2_V2_5LSP_QID_DIR_MAX_DEPTH(x))\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH_RST 0x0\n-\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH_DEPTH\t0x00001FFF\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH_RSVD0\t0xFFFFE000\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH_DEPTH_LOC\t0\n-#define DLB2_LSP_QID_DIR_MAX_DEPTH_RSVD0_LOC\t13\n-\n-#define DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n-\t(0xa0800000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTL(x) \\\n-\t(0x90880000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTL(x) : \\\n-\t DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTL(x))\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST 0x0\n-\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n-\t(0xa0880000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTH(x) \\\n-\t(0x90900000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_DIR_TOT_ENQ_CNTH(x) : \\\n-\t DLB2_V2_5LSP_QID_DIR_TOT_ENQ_CNTH(x))\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST 0x0\n-\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_DIR_ENQUEUE_CNT(x) \\\n-\t(0xa0900000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_DIR_ENQUEUE_CNT(x) \\\n-\t(0x90980000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_DIR_ENQUEUE_CNT(x) : \\\n-\t DLB2_V2_5LSP_QID_DIR_ENQUEUE_CNT(x))\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0\n-\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_COUNT\t0x00001FFF\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RSVD0\t0xFFFFE000\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RSVD0_LOC\t13\n-\n-#define DLB2_V2LSP_QID_DIR_DEPTH_THRSH(x) \\\n-\t(0xa0980000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_DIR_DEPTH_THRSH(x) \\\n-\t(0x90a00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_DIR_DEPTH_THRSH(x) : \\\n-\t DLB2_V2_5LSP_QID_DIR_DEPTH_THRSH(x))\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RST 0x0\n-\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_THRESH\t0x00001FFF\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RSVD0\t0xFFFFE000\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_THRESH_LOC\t0\n-#define DLB2_LSP_QID_DIR_DEPTH_THRSH_RSVD0_LOC\t13\n-\n-#define DLB2_V2LSP_QID_AQED_ACTIVE_CNT(x) \\\n-\t(0xa0a00000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_AQED_ACTIVE_CNT(x) \\\n-\t(0x90b80000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_AQED_ACTIVE_CNT(x) : \\\n-\t DLB2_V2_5LSP_QID_AQED_ACTIVE_CNT(x))\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RST 0x0\n-\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_COUNT\t0x00000FFF\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_QID_AQED_ACTIVE_CNT_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_QID_AQED_ACTIVE_LIM(x) \\\n-\t(0xa0a80000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_AQED_ACTIVE_LIM(x) \\\n-\t(0x90c00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_AQED_ACTIVE_LIM(x) : \\\n-\t DLB2_V2_5LSP_QID_AQED_ACTIVE_LIM(x))\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RST 0x0\n-\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_LIMIT\t0x00000FFF\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_LIMIT_LOC\t0\n-#define DLB2_LSP_QID_AQED_ACTIVE_LIM_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n-\t(0xa0b00000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTL(x) \\\n-\t(0x90c80000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTL(x) : \\\n-\t DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTL(x))\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST 0x0\n-\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n-\t(0xa0b80000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTH(x) \\\n-\t(0x90d00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_ATM_TOT_ENQ_CNTH(x) : \\\n-\t DLB2_V2_5LSP_QID_ATM_TOT_ENQ_CNTH(x))\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST 0x0\n-\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_LDB_ENQUEUE_CNT(x) \\\n-\t(0xa0c80000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_LDB_ENQUEUE_CNT(x) \\\n-\t(0x90e00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_LDB_ENQUEUE_CNT(x) : \\\n-\t DLB2_V2_5LSP_QID_LDB_ENQUEUE_CNT(x))\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0\n-\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_COUNT\t0x00003FFF\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RSVD0\t0xFFFFC000\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RSVD0_LOC\t14\n-\n-#define DLB2_V2LSP_QID_LDB_INFL_CNT(x) \\\n-\t(0xa0d00000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_LDB_INFL_CNT(x) \\\n-\t(0x90e80000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_LDB_INFL_CNT(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_LDB_INFL_CNT(x) : \\\n-\t DLB2_V2_5LSP_QID_LDB_INFL_CNT(x))\n-#define DLB2_LSP_QID_LDB_INFL_CNT_RST 0x0\n-\n-#define DLB2_LSP_QID_LDB_INFL_CNT_COUNT\t0x00000FFF\n-#define DLB2_LSP_QID_LDB_INFL_CNT_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_QID_LDB_INFL_CNT_COUNT_LOC\t0\n-#define DLB2_LSP_QID_LDB_INFL_CNT_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_QID_LDB_INFL_LIM(x) \\\n-\t(0xa0d80000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_LDB_INFL_LIM(x) \\\n-\t(0x90f00000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_LDB_INFL_LIM(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_LDB_INFL_LIM(x) : \\\n-\t DLB2_V2_5LSP_QID_LDB_INFL_LIM(x))\n-#define DLB2_LSP_QID_LDB_INFL_LIM_RST 0x0\n-\n-#define DLB2_LSP_QID_LDB_INFL_LIM_LIMIT\t0x00000FFF\n-#define DLB2_LSP_QID_LDB_INFL_LIM_RSVD0\t0xFFFFF000\n-#define DLB2_LSP_QID_LDB_INFL_LIM_LIMIT_LOC\t0\n-#define DLB2_LSP_QID_LDB_INFL_LIM_RSVD0_LOC\t12\n-\n-#define DLB2_V2LSP_QID2CQIDIX_00(x) \\\n-\t(0xa0e00000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID2CQIDIX_00(x) \\\n-\t(0x90f80000 + (x) * 0x1000)\n-#define DLB2_LSP_QID2CQIDIX_00(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID2CQIDIX_00(x) : \\\n-\t DLB2_V2_5LSP_QID2CQIDIX_00(x))\n-#define DLB2_LSP_QID2CQIDIX_00_RST 0x0\n-#define DLB2_LSP_QID2CQIDIX(ver, x, y) \\\n-\t(DLB2_LSP_QID2CQIDIX_00(ver, x) + 0x80000 * (y))\n-#define DLB2_LSP_QID2CQIDIX_NUM 16\n-\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P0\t0x000000FF\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P1\t0x0000FF00\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P2\t0x00FF0000\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P3\t0xFF000000\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P0_LOC\t0\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P1_LOC\t8\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P2_LOC\t16\n-#define DLB2_LSP_QID2CQIDIX_00_CQ_P3_LOC\t24\n-\n-#define DLB2_V2LSP_QID2CQIDIX2_00(x) \\\n-\t(0xa1600000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID2CQIDIX2_00(x) \\\n-\t(0x91780000 + (x) * 0x1000)\n-#define DLB2_LSP_QID2CQIDIX2_00(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID2CQIDIX2_00(x) : \\\n-\t DLB2_V2_5LSP_QID2CQIDIX2_00(x))\n-#define DLB2_LSP_QID2CQIDIX2_00_RST 0x0\n-#define DLB2_LSP_QID2CQIDIX2(ver, x, y) \\\n-\t(DLB2_LSP_QID2CQIDIX2_00(ver, x) + 0x80000 * (y))\n-#define DLB2_LSP_QID2CQIDIX2_NUM 16\n-\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P0\t0x000000FF\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P1\t0x0000FF00\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P2\t0x00FF0000\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P3\t0xFF000000\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P0_LOC\t0\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P1_LOC\t8\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P2_LOC\t16\n-#define DLB2_LSP_QID2CQIDIX2_00_CQ_P3_LOC\t24\n-\n-#define DLB2_V2LSP_QID_NALDB_MAX_DEPTH(x) \\\n-\t(0xa1f00000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_NALDB_MAX_DEPTH(x) \\\n-\t(0x92080000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_NALDB_MAX_DEPTH(x) : \\\n-\t DLB2_V2_5LSP_QID_NALDB_MAX_DEPTH(x))\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RST 0x0\n-\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_DEPTH\t0x00003FFF\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RSVD0\t0xFFFFC000\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_DEPTH_LOC\t0\n-#define DLB2_LSP_QID_NALDB_MAX_DEPTH_RSVD0_LOC\t14\n-\n-#define DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n-\t(0xa1f80000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTL(x) \\\n-\t(0x92100000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTL(x) : \\\n-\t DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTL(x))\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST 0x0\n-\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n-\t(0xa2000000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTH(x) \\\n-\t(0x92180000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_NALDB_TOT_ENQ_CNTH(x) : \\\n-\t DLB2_V2_5LSP_QID_NALDB_TOT_ENQ_CNTH(x))\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST 0x0\n-\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_QID_ATM_DEPTH_THRSH(x) \\\n-\t(0xa2080000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_ATM_DEPTH_THRSH(x) \\\n-\t(0x92200000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_ATM_DEPTH_THRSH(x) : \\\n-\t DLB2_V2_5LSP_QID_ATM_DEPTH_THRSH(x))\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RST 0x0\n-\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_THRESH\t0x00003FFF\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RSVD0\t0xFFFFC000\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_THRESH_LOC\t0\n-#define DLB2_LSP_QID_ATM_DEPTH_THRSH_RSVD0_LOC\t14\n-\n-#define DLB2_V2LSP_QID_NALDB_DEPTH_THRSH(x) \\\n-\t(0xa2100000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_NALDB_DEPTH_THRSH(x) \\\n-\t(0x92280000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_NALDB_DEPTH_THRSH(x) : \\\n-\t DLB2_V2_5LSP_QID_NALDB_DEPTH_THRSH(x))\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST 0x0\n-\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_THRESH\t0x00003FFF\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RSVD0\t\t0xFFFFC000\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_THRESH_LOC\t0\n-#define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RSVD0_LOC\t14\n-\n-#define DLB2_V2LSP_QID_ATM_ACTIVE(x) \\\n-\t(0xa2180000 + (x) * 0x1000)\n-#define DLB2_V2_5LSP_QID_ATM_ACTIVE(x) \\\n-\t(0x92300000 + (x) * 0x1000)\n-#define DLB2_LSP_QID_ATM_ACTIVE(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_QID_ATM_ACTIVE(x) : \\\n-\t DLB2_V2_5LSP_QID_ATM_ACTIVE(x))\n-#define DLB2_LSP_QID_ATM_ACTIVE_RST 0x0\n-\n-#define DLB2_LSP_QID_ATM_ACTIVE_COUNT\t0x00003FFF\n-#define DLB2_LSP_QID_ATM_ACTIVE_RSVD0\t0xFFFFC000\n-#define DLB2_LSP_QID_ATM_ACTIVE_COUNT_LOC\t0\n-#define DLB2_LSP_QID_ATM_ACTIVE_RSVD0_LOC\t14\n-\n-#define DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008\n-#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0x94000008\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 : \\\n-\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0)\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI0_WEIGHT\t0x000000FF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI1_WEIGHT\t0x0000FF00\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI2_WEIGHT\t0x00FF0000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI3_WEIGHT\t0xFF000000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI0_WEIGHT_LOC\t0\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI1_WEIGHT_LOC\t8\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI2_WEIGHT_LOC\t16\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_PRI3_WEIGHT_LOC\t24\n-\n-#define DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c\n-#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0x9400000c\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 : \\\n-\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1)\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RSVZ0_V2\t0xFFFFFFFF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RSVZ0_V2_LOC\t0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI4_WEIGHT_V2_5\t0x000000FF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI5_WEIGHT_V2_5\t0x0000FF00\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI6_WEIGHT_V2_5\t0x00FF0000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI7_WEIGHT_V2_5\t0xFF000000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI4_WEIGHT_V2_5_LOC\t0\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI5_WEIGHT_V2_5_LOC\t8\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI6_WEIGHT_V2_5_LOC\t16\n-#define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_PRI7_WEIGHT_V2_5_LOC\t24\n-\n-#define DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014\n-#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_0 0x94000014\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_0 : \\\n-\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_0)\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI0_WEIGHT\t0x000000FF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI1_WEIGHT\t0x0000FF00\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI2_WEIGHT\t0x00FF0000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI3_WEIGHT\t0xFF000000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI0_WEIGHT_LOC\t0\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI1_WEIGHT_LOC\t8\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI2_WEIGHT_LOC\t16\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_PRI3_WEIGHT_LOC\t24\n-\n-#define DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018\n-#define DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_1 0x94000018\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_ARB_WEIGHT_LDB_QID_1 : \\\n-\t DLB2_V2_5LSP_CFG_ARB_WEIGHT_LDB_QID_1)\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RSVZ0_V2\t0xFFFFFFFF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RSVZ0_V2_LOC\t0\n-\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI4_WEIGHT_V2_5\t0x000000FF\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI5_WEIGHT_V2_5\t0x0000FF00\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI6_WEIGHT_V2_5\t0x00FF0000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI7_WEIGHT_V2_5\t0xFF000000\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI4_WEIGHT_V2_5_LOC\t0\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI5_WEIGHT_V2_5_LOC\t8\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI6_WEIGHT_V2_5_LOC\t16\n-#define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_PRI7_WEIGHT_V2_5_LOC\t24\n-\n-#define DLB2_V2LSP_LDB_SCHED_CTRL 0xa400002c\n-#define DLB2_V2_5LSP_LDB_SCHED_CTRL 0x9400002c\n-#define DLB2_LSP_LDB_SCHED_CTRL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_LDB_SCHED_CTRL : \\\n-\t DLB2_V2_5LSP_LDB_SCHED_CTRL)\n-#define DLB2_LSP_LDB_SCHED_CTRL_RST 0x0\n-\n-#define DLB2_LSP_LDB_SCHED_CTRL_CQ\t\t\t0x000000FF\n-#define DLB2_LSP_LDB_SCHED_CTRL_QIDIX\t\t0x00000700\n-#define DLB2_LSP_LDB_SCHED_CTRL_VALUE\t\t0x00000800\n-#define DLB2_LSP_LDB_SCHED_CTRL_NALB_HASWORK_V\t0x00001000\n-#define DLB2_LSP_LDB_SCHED_CTRL_RLIST_HASWORK_V\t0x00002000\n-#define DLB2_LSP_LDB_SCHED_CTRL_SLIST_HASWORK_V\t0x00004000\n-#define DLB2_LSP_LDB_SCHED_CTRL_INFLIGHT_OK_V\t0x00008000\n-#define DLB2_LSP_LDB_SCHED_CTRL_AQED_NFULL_V\t\t0x00010000\n-#define DLB2_LSP_LDB_SCHED_CTRL_RSVZ0\t\t0xFFFE0000\n-#define DLB2_LSP_LDB_SCHED_CTRL_CQ_LOC\t\t0\n-#define DLB2_LSP_LDB_SCHED_CTRL_QIDIX_LOC\t\t8\n-#define DLB2_LSP_LDB_SCHED_CTRL_VALUE_LOC\t\t11\n-#define DLB2_LSP_LDB_SCHED_CTRL_NALB_HASWORK_V_LOC\t12\n-#define DLB2_LSP_LDB_SCHED_CTRL_RLIST_HASWORK_V_LOC\t13\n-#define DLB2_LSP_LDB_SCHED_CTRL_SLIST_HASWORK_V_LOC\t14\n-#define DLB2_LSP_LDB_SCHED_CTRL_INFLIGHT_OK_V_LOC\t15\n-#define DLB2_LSP_LDB_SCHED_CTRL_AQED_NFULL_V_LOC\t16\n-#define DLB2_LSP_LDB_SCHED_CTRL_RSVZ0_LOC\t\t17\n-\n-#define DLB2_V2LSP_DIR_SCH_CNT_L 0xa4000034\n-#define DLB2_V2_5LSP_DIR_SCH_CNT_L 0x94000034\n-#define DLB2_LSP_DIR_SCH_CNT_L(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_DIR_SCH_CNT_L : \\\n-\t DLB2_V2_5LSP_DIR_SCH_CNT_L)\n-#define DLB2_LSP_DIR_SCH_CNT_L_RST 0x0\n-\n-#define DLB2_LSP_DIR_SCH_CNT_L_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_DIR_SCH_CNT_L_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_DIR_SCH_CNT_H 0xa4000038\n-#define DLB2_V2_5LSP_DIR_SCH_CNT_H 0x94000038\n-#define DLB2_LSP_DIR_SCH_CNT_H(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_DIR_SCH_CNT_H : \\\n-\t DLB2_V2_5LSP_DIR_SCH_CNT_H)\n-#define DLB2_LSP_DIR_SCH_CNT_H_RST 0x0\n-\n-#define DLB2_LSP_DIR_SCH_CNT_H_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_DIR_SCH_CNT_H_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_LDB_SCH_CNT_L 0xa400003c\n-#define DLB2_V2_5LSP_LDB_SCH_CNT_L 0x9400003c\n-#define DLB2_LSP_LDB_SCH_CNT_L(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_LDB_SCH_CNT_L : \\\n-\t DLB2_V2_5LSP_LDB_SCH_CNT_L)\n-#define DLB2_LSP_LDB_SCH_CNT_L_RST 0x0\n-\n-#define DLB2_LSP_LDB_SCH_CNT_L_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_LDB_SCH_CNT_L_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_LDB_SCH_CNT_H 0xa4000040\n-#define DLB2_V2_5LSP_LDB_SCH_CNT_H 0x94000040\n-#define DLB2_LSP_LDB_SCH_CNT_H(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_LDB_SCH_CNT_H : \\\n-\t DLB2_V2_5LSP_LDB_SCH_CNT_H)\n-#define DLB2_LSP_LDB_SCH_CNT_H_RST 0x0\n-\n-#define DLB2_LSP_LDB_SCH_CNT_H_COUNT\t0xFFFFFFFF\n-#define DLB2_LSP_LDB_SCH_CNT_H_COUNT_LOC\t0\n-\n-#define DLB2_V2LSP_CFG_SHDW_CTRL 0xa4000070\n-#define DLB2_V2_5LSP_CFG_SHDW_CTRL 0x94000070\n-#define DLB2_LSP_CFG_SHDW_CTRL(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_SHDW_CTRL : \\\n-\t DLB2_V2_5LSP_CFG_SHDW_CTRL)\n-#define DLB2_LSP_CFG_SHDW_CTRL_RST 0x0\n-\n-#define DLB2_LSP_CFG_SHDW_CTRL_TRANSFER\t0x00000001\n-#define DLB2_LSP_CFG_SHDW_CTRL_RSVD0\t\t0xFFFFFFFE\n-#define DLB2_LSP_CFG_SHDW_CTRL_TRANSFER_LOC\t0\n-#define DLB2_LSP_CFG_SHDW_CTRL_RSVD0_LOC\t1\n-\n-#define DLB2_V2LSP_CFG_SHDW_RANGE_COS(x) \\\n-\t(0xa4000074 + (x) * 4)\n-#define DLB2_V2_5LSP_CFG_SHDW_RANGE_COS(x) \\\n-\t(0x94000074 + (x) * 4)\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS(ver, x) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_SHDW_RANGE_COS(x) : \\\n-\t DLB2_V2_5LSP_CFG_SHDW_RANGE_COS(x))\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_RST 0x40\n-\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE\t\t0x000001FF\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_RSVZ0\t\t0x7FFFFE00\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_NO_EXTRA_CREDIT\t0x80000000\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE_LOC\t\t0\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_RSVZ0_LOC\t\t9\n-#define DLB2_LSP_CFG_SHDW_RANGE_COS_NO_EXTRA_CREDIT_LOC\t31\n-\n-#define DLB2_V2LSP_CFG_CTRL_GENERAL_0 0xac000000\n-#define DLB2_V2_5LSP_CFG_CTRL_GENERAL_0 0x9c000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2LSP_CFG_CTRL_GENERAL_0 : \\\n-\t DLB2_V2_5LSP_CFG_CTRL_GENERAL_0)\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RST 0x0\n-\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2\t0x00000001\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2\t0x00000002\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2\t0x00000004\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2\t0x00000008\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2\t\t0x00000030\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2\t0x00000040\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2\t0x00000080\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2\t0x00000100\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2\t0x00000200\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2\t0x00000400\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2\t0x00000800\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2\t0x00001000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2\t0x00002000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2\t0x00004000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2\t0x00008000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2\t0x00010000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2\t0x00020000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2\t0x00040000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2\t0x00080000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2\t0x00100000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2\t0x00200000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2\t0x00400000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2\t0x00800000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2\t0x01000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2\t0x02000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2\t\t0x04000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2\t0x18000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2\t0x20000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2\t0xC0000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_LOC\t0\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_LOC\t\t1\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_LOC\t\t2\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_LOC\t\t3\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_LOC\t\t\t4\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_LOC\t\t6\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_LOC\t\t7\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_LOC\t\t8\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_LOC\t\t9\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_LOC\t\t10\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_LOC\t\t11\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_LOC\t\t12\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_LOC\t\t13\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_LOC\t\t14\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_LOC\t\t15\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_LOC\t\t16\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_LOC\t\t17\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_LOC\t\t18\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_LOC\t\t19\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_LOC\t\t20\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_LOC\t\t21\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_LOC\t\t22\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_LOC\t\t23\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_LOC\t\t24\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_LOC\t\t25\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_LOC\t\t\t26\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_LOC\t\t27\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_LOC\t\t29\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_LOC\t\t30\n-\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_5\t0x00000001\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_5\t0x00000002\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_5\t0x00000004\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_5\t0x00000008\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5\t0x00000010\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_5\t\t0x00000020\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_5\t0x00000040\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_5\t0x00000080\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_5\t0x00000100\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_5\t0x00000200\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_5\t0x00000400\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_5\t0x00000800\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_5\t0x00001000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_5\t0x00002000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_5\t0x00004000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_5\t0x00008000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_5\t0x00010000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_5\t0x00020000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_5\t0x00040000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_5\t0x00080000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_5\t0x00100000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_5\t0x00200000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_5\t0x00400000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_5\t0x00800000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_5\t0x01000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_5\t0x02000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_5\t\t0x04000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_5\t0x18000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_5\t0x20000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_5\t0xC0000000\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_ATQ_EMPTY_ARB_V2_5_LOC\t0\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_TOK_UNIT_IDLE_V2_5_LOC\t1\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DISAB_RLIST_PRI_V2_5_LOC\t\t2\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_INC_CMP_UNIT_IDLE_V2_5_LOC\t3\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5_LOC\t\t4\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ0_V2_5_LOC\t\t\t5\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OP_V2_5_LOC\t\t6\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_HALF_BW_V2_5_LOC\t\t7\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_SINGLE_OUT_V2_5_LOC\t\t8\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIR_DISAB_MULTI_V2_5_LOC\t\t9\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OP_V2_5_LOC\t\t10\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_HALF_BW_V2_5_LOC\t\t11\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_SINGLE_OUT_V2_5_LOC\t\t12\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATQ_DISAB_MULTI_V2_5_LOC\t\t13\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OP_V2_5_LOC\t14\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_HALF_BW_V2_5_LOC\t\t15\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_DIRRPL_SINGLE_OUT_V2_5_LOC\t16\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OP_V2_5_LOC\t\t17\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_HALF_BW_V2_5_LOC\t\t18\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LBRPL_SINGLE_OUT_V2_5_LOC\t19\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_SINGLE_OP_V2_5_LOC\t\t20\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_HALF_BW_V2_5_LOC\t\t21\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_DISAB_MULTI_V2_5_LOC\t\t22\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_SCH_V2_5_LOC\t\t23\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_ATM_SINGLE_CMP_V2_5_LOC\t\t24\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_LDB_CE_TOG_ARB_V2_5_LOC\t\t25\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_RSVZ1_V2_5_LOC\t\t\t26\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALID_SEL_V2_5_LOC\t\t27\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_VALUE_SEL_V2_5_LOC\t\t29\n-#define DLB2_LSP_CFG_CTRL_GENERAL_0_SMON0_COMPARE_SEL_V2_5_LOC\t30\n-\n-#define DLB2_LSP_SMON_COMPARE0 0xac000048\n-#define DLB2_LSP_SMON_COMPARE0_RST 0x0\n-\n-#define DLB2_LSP_SMON_COMPARE0_COMPARE0\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_COMPARE0_COMPARE0_LOC\t0\n-\n-#define DLB2_LSP_SMON_COMPARE1 0xac00004c\n-#define DLB2_LSP_SMON_COMPARE1_RST 0x0\n-\n-#define DLB2_LSP_SMON_COMPARE1_COMPARE1\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_COMPARE1_COMPARE1_LOC\t0\n-\n-#define DLB2_LSP_SMON_CFG0 0xac000050\n-#define DLB2_LSP_SMON_CFG0_RST 0x40000000\n-\n-#define DLB2_LSP_SMON_CFG0_SMON_ENABLE\t\t0x00000001\n-#define DLB2_LSP_SMON_CFG0_SMON_0TRIGGER_ENABLE\t0x00000002\n-#define DLB2_LSP_SMON_CFG0_RSVZ0\t\t\t0x0000000C\n-#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION\t\t0x00000070\n-#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_COMPARE\t0x00000080\n-#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION\t\t0x00000700\n-#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_COMPARE\t0x00000800\n-#define DLB2_LSP_SMON_CFG0_SMON_MODE\t\t\t0x0000F000\n-#define DLB2_LSP_SMON_CFG0_STOPCOUNTEROVFL\t\t0x00010000\n-#define DLB2_LSP_SMON_CFG0_INTCOUNTEROVFL\t\t0x00020000\n-#define DLB2_LSP_SMON_CFG0_STATCOUNTER0OVFL\t\t0x00040000\n-#define DLB2_LSP_SMON_CFG0_STATCOUNTER1OVFL\t\t0x00080000\n-#define DLB2_LSP_SMON_CFG0_STOPTIMEROVFL\t\t0x00100000\n-#define DLB2_LSP_SMON_CFG0_INTTIMEROVFL\t\t0x00200000\n-#define DLB2_LSP_SMON_CFG0_STATTIMEROVFL\t\t0x00400000\n-#define DLB2_LSP_SMON_CFG0_RSVZ1\t\t\t0x00800000\n-#define DLB2_LSP_SMON_CFG0_TIMER_PRESCALE\t\t0x1F000000\n-#define DLB2_LSP_SMON_CFG0_RSVZ2\t\t\t0x20000000\n-#define DLB2_LSP_SMON_CFG0_VERSION\t\t\t0xC0000000\n-#define DLB2_LSP_SMON_CFG0_SMON_ENABLE_LOC\t\t\t0\n-#define DLB2_LSP_SMON_CFG0_SMON_0TRIGGER_ENABLE_LOC\t\t1\n-#define DLB2_LSP_SMON_CFG0_RSVZ0_LOC\t\t\t\t2\n-#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_LOC\t\t4\n-#define DLB2_LSP_SMON_CFG0_SMON0_FUNCTION_COMPARE_LOC\t7\n-#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_LOC\t\t8\n-#define DLB2_LSP_SMON_CFG0_SMON1_FUNCTION_COMPARE_LOC\t11\n-#define DLB2_LSP_SMON_CFG0_SMON_MODE_LOC\t\t\t12\n-#define DLB2_LSP_SMON_CFG0_STOPCOUNTEROVFL_LOC\t\t16\n-#define DLB2_LSP_SMON_CFG0_INTCOUNTEROVFL_LOC\t\t17\n-#define DLB2_LSP_SMON_CFG0_STATCOUNTER0OVFL_LOC\t\t18\n-#define DLB2_LSP_SMON_CFG0_STATCOUNTER1OVFL_LOC\t\t19\n-#define DLB2_LSP_SMON_CFG0_STOPTIMEROVFL_LOC\t\t\t20\n-#define DLB2_LSP_SMON_CFG0_INTTIMEROVFL_LOC\t\t\t21\n-#define DLB2_LSP_SMON_CFG0_STATTIMEROVFL_LOC\t\t\t22\n-#define DLB2_LSP_SMON_CFG0_RSVZ1_LOC\t\t\t\t23\n-#define DLB2_LSP_SMON_CFG0_TIMER_PRESCALE_LOC\t\t24\n-#define DLB2_LSP_SMON_CFG0_RSVZ2_LOC\t\t\t\t29\n-#define DLB2_LSP_SMON_CFG0_VERSION_LOC\t\t\t30\n-\n-#define DLB2_LSP_SMON_CFG1 0xac000054\n-#define DLB2_LSP_SMON_CFG1_RST 0x0\n-\n-#define DLB2_LSP_SMON_CFG1_MODE0\t0x000000FF\n-#define DLB2_LSP_SMON_CFG1_MODE1\t0x0000FF00\n-#define DLB2_LSP_SMON_CFG1_RSVZ0\t0xFFFF0000\n-#define DLB2_LSP_SMON_CFG1_MODE0_LOC\t0\n-#define DLB2_LSP_SMON_CFG1_MODE1_LOC\t8\n-#define DLB2_LSP_SMON_CFG1_RSVZ0_LOC\t16\n-\n-#define DLB2_LSP_SMON_ACTIVITYCNTR0 0xac000058\n-#define DLB2_LSP_SMON_ACTIVITYCNTR0_RST 0x0\n-\n-#define DLB2_LSP_SMON_ACTIVITYCNTR0_COUNTER0\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_ACTIVITYCNTR0_COUNTER0_LOC\t0\n-\n-#define DLB2_LSP_SMON_ACTIVITYCNTR1 0xac00005c\n-#define DLB2_LSP_SMON_ACTIVITYCNTR1_RST 0x0\n-\n-#define DLB2_LSP_SMON_ACTIVITYCNTR1_COUNTER1\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_ACTIVITYCNTR1_COUNTER1_LOC\t0\n-\n-#define DLB2_LSP_SMON_MAX_TMR 0xac000060\n-#define DLB2_LSP_SMON_MAX_TMR_RST 0x0\n-\n-#define DLB2_LSP_SMON_MAX_TMR_MAXVALUE\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_MAX_TMR_MAXVALUE_LOC\t0\n-\n-#define DLB2_LSP_SMON_TMR 0xac000064\n-#define DLB2_LSP_SMON_TMR_RST 0x0\n-\n-#define DLB2_LSP_SMON_TMR_TIMER\t0xFFFFFFFF\n-#define DLB2_LSP_SMON_TMR_TIMER_LOC\t0\n-\n-#define DLB2_V2CM_DIAG_RESET_STS 0xb4000000\n-#define DLB2_V2_5CM_DIAG_RESET_STS 0xa4000000\n-#define DLB2_CM_DIAG_RESET_STS(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t V2CM_DIAG_RESET_STS : \\\n-\t V2_5CM_DIAG_RESET_STS)\n-#define DLB2_CM_DIAG_RESET_STS_RST 0x80000bff\n-\n-#define DLB2_CM_DIAG_RESET_STS_CHP_PF_RESET_DONE\t0x00000001\n-#define DLB2_CM_DIAG_RESET_STS_ROP_PF_RESET_DONE\t0x00000002\n-#define DLB2_CM_DIAG_RESET_STS_LSP_PF_RESET_DONE\t0x00000004\n-#define DLB2_CM_DIAG_RESET_STS_NALB_PF_RESET_DONE\t0x00000008\n-#define DLB2_CM_DIAG_RESET_STS_AP_PF_RESET_DONE\t0x00000010\n-#define DLB2_CM_DIAG_RESET_STS_DP_PF_RESET_DONE\t0x00000020\n-#define DLB2_CM_DIAG_RESET_STS_QED_PF_RESET_DONE\t0x00000040\n-#define DLB2_CM_DIAG_RESET_STS_DQED_PF_RESET_DONE\t0x00000080\n-#define DLB2_CM_DIAG_RESET_STS_AQED_PF_RESET_DONE\t0x00000100\n-#define DLB2_CM_DIAG_RESET_STS_SYS_PF_RESET_DONE\t0x00000200\n-#define DLB2_CM_DIAG_RESET_STS_PF_RESET_ACTIVE\t0x00000400\n-#define DLB2_CM_DIAG_RESET_STS_FLRSM_STATE\t\t0x0003F800\n-#define DLB2_CM_DIAG_RESET_STS_RSVD0\t\t\t0x7FFC0000\n-#define DLB2_CM_DIAG_RESET_STS_DLB_PROC_RESET_DONE\t0x80000000\n-#define DLB2_CM_DIAG_RESET_STS_CHP_PF_RESET_DONE_LOC\t\t0\n-#define DLB2_CM_DIAG_RESET_STS_ROP_PF_RESET_DONE_LOC\t\t1\n-#define DLB2_CM_DIAG_RESET_STS_LSP_PF_RESET_DONE_LOC\t\t2\n-#define DLB2_CM_DIAG_RESET_STS_NALB_PF_RESET_DONE_LOC\t3\n-#define DLB2_CM_DIAG_RESET_STS_AP_PF_RESET_DONE_LOC\t\t4\n-#define DLB2_CM_DIAG_RESET_STS_DP_PF_RESET_DONE_LOC\t\t5\n-#define DLB2_CM_DIAG_RESET_STS_QED_PF_RESET_DONE_LOC\t\t6\n-#define DLB2_CM_DIAG_RESET_STS_DQED_PF_RESET_DONE_LOC\t7\n-#define DLB2_CM_DIAG_RESET_STS_AQED_PF_RESET_DONE_LOC\t8\n-#define DLB2_CM_DIAG_RESET_STS_SYS_PF_RESET_DONE_LOC\t\t9\n-#define DLB2_CM_DIAG_RESET_STS_PF_RESET_ACTIVE_LOC\t\t10\n-#define DLB2_CM_DIAG_RESET_STS_FLRSM_STATE_LOC\t\t11\n-#define DLB2_CM_DIAG_RESET_STS_RSVD0_LOC\t\t\t18\n-#define DLB2_CM_DIAG_RESET_STS_DLB_PROC_RESET_DONE_LOC\t31\n-\n-#define DLB2_V2CM_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004\n-#define DLB2_V2_5CM_CFG_DIAGNOSTIC_IDLE_STATUS 0xa4000004\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CM_CFG_DIAGNOSTIC_IDLE_STATUS : \\\n-\t DLB2_V2_5CM_CFG_DIAGNOSTIC_IDLE_STATUS)\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff\n-\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_PIPEIDLE\t\t0x00000001\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_PIPEIDLE\t\t0x00000002\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_PIPEIDLE\t\t0x00000004\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_PIPEIDLE\t0x00000008\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_PIPEIDLE\t\t0x00000010\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_PIPEIDLE\t\t0x00000020\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_PIPEIDLE\t\t0x00000040\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_PIPEIDLE\t0x00000080\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_PIPEIDLE\t0x00000100\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_PIPEIDLE\t\t0x00000200\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_UNIT_IDLE\t0x00000400\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_UNIT_IDLE\t0x00000800\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_UNIT_IDLE\t0x00001000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_UNIT_IDLE\t0x00002000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_UNIT_IDLE\t\t0x00004000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_UNIT_IDLE\t\t0x00008000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_UNIT_IDLE\t0x00010000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_UNIT_IDLE\t0x00020000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_UNIT_IDLE\t0x00040000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_UNIT_IDLE\t0x00080000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD1\t\t0x00F00000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_RING_IDLE\t0x01000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_MSTR_IDLE\t0x02000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_FLR_CLKREQ_B\t0x04000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE\t0x08000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_MASKED 0x10000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD0\t\t 0x60000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE\t 0x80000000\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_PIPEIDLE_LOC\t\t0\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_PIPEIDLE_LOC\t\t1\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_PIPEIDLE_LOC\t\t2\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_PIPEIDLE_LOC\t\t3\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_PIPEIDLE_LOC\t\t4\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_PIPEIDLE_LOC\t\t5\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_PIPEIDLE_LOC\t\t6\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_PIPEIDLE_LOC\t\t7\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_PIPEIDLE_LOC\t\t8\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_PIPEIDLE_LOC\t\t9\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_CHP_UNIT_IDLE_LOC\t\t10\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_ROP_UNIT_IDLE_LOC\t\t11\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_LSP_UNIT_IDLE_LOC\t\t12\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_NALB_UNIT_IDLE_LOC\t13\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AP_UNIT_IDLE_LOC\t\t14\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DP_UNIT_IDLE_LOC\t\t15\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_QED_UNIT_IDLE_LOC\t\t16\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DQED_UNIT_IDLE_LOC\t17\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_AQED_UNIT_IDLE_LOC\t18\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_SYS_UNIT_IDLE_LOC\t\t19\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD1_LOC\t\t\t20\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_RING_IDLE_LOC\t24\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_CFG_MSTR_IDLE_LOC\t25\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_FLR_CLKREQ_B_LOC\t26\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_LOC\t27\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_MSTR_PROC_IDLE_MASKED_LOC\t28\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_RSVD0_LOC\t\t\t29\n-#define DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE_LOC\t\t31\n-\n-#define DLB2_V2CM_CFG_PM_STATUS 0xb4000014\n-#define DLB2_V2_5CM_CFG_PM_STATUS 0xa4000014\n-#define DLB2_CM_CFG_PM_STATUS(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CM_CFG_PM_STATUS : \\\n-\t DLB2_V2_5CM_CFG_PM_STATUS)\n-#define DLB2_CM_CFG_PM_STATUS_RST 0x100403e\n-\n-#define DLB2_CM_CFG_PM_STATUS_PROCHOT\t\t0x00000001\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_IDLE\t\t0x00000002\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_PG_RDY_ACK_B\t0x00000004\n-#define DLB2_CM_CFG_PM_STATUS_PMSM_PGCB_REQ_B\t0x00000008\n-#define DLB2_CM_CFG_PM_STATUS_PGBC_PMC_PG_REQ_B\t0x00000010\n-#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_PG_ACK_B\t0x00000020\n-#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_FET_EN_B\t0x00000040\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_FET_EN_B\t\t0x00000080\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ0\t\t\t0x00000100\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ1\t\t\t0x00000200\n-#define DLB2_CM_CFG_PM_STATUS_FUSE_FORCE_ON\t\t0x00000400\n-#define DLB2_CM_CFG_PM_STATUS_FUSE_PROC_DISABLE\t0x00000800\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ2\t\t\t0x00001000\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ3\t\t\t0x00002000\n-#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D0TOD3_OK\t0x00004000\n-#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D3TOD0_OK\t0x00008000\n-#define DLB2_CM_CFG_PM_STATUS_DLB_IN_D3\t\t0x00010000\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ4\t\t\t0x00FE0000\n-#define DLB2_CM_CFG_PM_STATUS_PMSM\t\t\t0xFF000000\n-#define DLB2_CM_CFG_PM_STATUS_PROCHOT_LOC\t\t\t0\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_IDLE_LOC\t\t1\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_DLB_PG_RDY_ACK_B_LOC\t2\n-#define DLB2_CM_CFG_PM_STATUS_PMSM_PGCB_REQ_B_LOC\t\t3\n-#define DLB2_CM_CFG_PM_STATUS_PGBC_PMC_PG_REQ_B_LOC\t\t4\n-#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_PG_ACK_B_LOC\t\t5\n-#define DLB2_CM_CFG_PM_STATUS_PMC_PGCB_FET_EN_B_LOC\t\t6\n-#define DLB2_CM_CFG_PM_STATUS_PGCB_FET_EN_B_LOC\t\t7\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ0_LOC\t\t\t8\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ1_LOC\t\t\t9\n-#define DLB2_CM_CFG_PM_STATUS_FUSE_FORCE_ON_LOC\t\t10\n-#define DLB2_CM_CFG_PM_STATUS_FUSE_PROC_DISABLE_LOC\t\t11\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ2_LOC\t\t\t12\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ3_LOC\t\t\t13\n-#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D0TOD3_OK_LOC\t\t14\n-#define DLB2_CM_CFG_PM_STATUS_PM_FSM_D3TOD0_OK_LOC\t\t15\n-#define DLB2_CM_CFG_PM_STATUS_DLB_IN_D3_LOC\t\t\t16\n-#define DLB2_CM_CFG_PM_STATUS_RSVZ4_LOC\t\t\t17\n-#define DLB2_CM_CFG_PM_STATUS_PMSM_LOC\t\t\t24\n-\n-#define DLB2_V2CM_CFG_PM_PMCSR_DISABLE 0xb4000018\n-#define DLB2_V2_5CM_CFG_PM_PMCSR_DISABLE 0xa4000018\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE(ver) \\\n-\t(ver == DLB2_HW_V2 ? \\\n-\t DLB2_V2CM_CFG_PM_PMCSR_DISABLE : \\\n-\t DLB2_V2_5CM_CFG_PM_PMCSR_DISABLE)\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RST 0x1\n-\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE_DISABLE\t0x00000001\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RSVZ0\t0xFFFFFFFE\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE_DISABLE_LOC\t0\n-#define DLB2_CM_CFG_PM_PMCSR_DISABLE_RSVZ0_LOC\t1\n-\n-#define DLB2_VF_VF2PF_MAILBOX_BYTES 256\n-#define DLB2_VF_VF2PF_MAILBOX(x) \\\n-\t(0x1000 + (x) * 0x4)\n-#define DLB2_VF_VF2PF_MAILBOX_RST 0x0\n-\n-#define DLB2_VF_VF2PF_MAILBOX_MSG\t0xFFFFFFFF\n-#define DLB2_VF_VF2PF_MAILBOX_MSG_LOC\t0\n-\n-#define DLB2_VF_VF2PF_MAILBOX_ISR 0x1f00\n-#define DLB2_VF_VF2PF_MAILBOX_ISR_RST 0x0\n-#define DLB2_VF_SIOV_MBOX_ISR_TRIGGER 0x8000\n-\n-#define DLB2_VF_VF2PF_MAILBOX_ISR_ISR\t0x00000001\n-#define DLB2_VF_VF2PF_MAILBOX_ISR_RSVD0\t0xFFFFFFFE\n-#define DLB2_VF_VF2PF_MAILBOX_ISR_ISR_LOC\t0\n-#define DLB2_VF_VF2PF_MAILBOX_ISR_RSVD0_LOC\t1\n-\n-#define DLB2_VF_PF2VF_MAILBOX_BYTES 64\n-#define DLB2_VF_PF2VF_MAILBOX(x) \\\n-\t(0x2000 + (x) * 0x4)\n-#define DLB2_VF_PF2VF_MAILBOX_RST 0x0\n-\n-#define DLB2_VF_PF2VF_MAILBOX_MSG\t0xFFFFFFFF\n-#define DLB2_VF_PF2VF_MAILBOX_MSG_LOC\t0\n-\n-#define DLB2_VF_PF2VF_MAILBOX_ISR 0x2f00\n-#define DLB2_VF_PF2VF_MAILBOX_ISR_RST 0x0\n-\n-#define DLB2_VF_PF2VF_MAILBOX_ISR_PF_ISR\t0x00000001\n-#define DLB2_VF_PF2VF_MAILBOX_ISR_RSVD0\t0xFFFFFFFE\n-#define DLB2_VF_PF2VF_MAILBOX_ISR_PF_ISR_LOC\t0\n-#define DLB2_VF_PF2VF_MAILBOX_ISR_RSVD0_LOC\t1\n-\n-#define DLB2_VF_VF_MSI_ISR_PEND 0x2f10\n-#define DLB2_VF_VF_MSI_ISR_PEND_RST 0x0\n-\n-#define DLB2_VF_VF_MSI_ISR_PEND_ISR_PEND\t0xFFFFFFFF\n-#define DLB2_VF_VF_MSI_ISR_PEND_ISR_PEND_LOC\t0\n-\n-#define DLB2_VF_VF_RESET_IN_PROGRESS 0x3000\n-#define DLB2_VF_VF_RESET_IN_PROGRESS_RST 0x1\n-\n-#define DLB2_VF_VF_RESET_IN_PROGRESS_RESET_IN_PROGRESS\t0x00000001\n-#define DLB2_VF_VF_RESET_IN_PROGRESS_RSVD0\t\t\t0xFFFFFFFE\n-#define DLB2_VF_VF_RESET_IN_PROGRESS_RESET_IN_PROGRESS_LOC\t0\n-#define DLB2_VF_VF_RESET_IN_PROGRESS_RSVD0_LOC\t\t1\n-\n-#define DLB2_VF_VF_MSI_ISR 0x4000\n-#define DLB2_VF_VF_MSI_ISR_RST 0x0\n-\n-#define DLB2_VF_VF_MSI_ISR_VF_MSI_ISR\t0xFFFFFFFF\n-#define DLB2_VF_VF_MSI_ISR_VF_MSI_ISR_LOC\t0\n-\n-#define DLB2_SYS_TOTAL_CREDITS 0x10000100\n-#define DLB2_SYS_TOTAL_CREDITS_RST 0x4000\n-\n-#define DLB2_SYS_TOTAL_CREDITS_TOTAL_CREDITS\t0xFFFFFFFF\n-#define DLB2_SYS_TOTAL_CREDITS_TOTAL_CREDITS_LOC\t0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_U(x) \\\n-\t(0x10000fa4 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_U_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_U_CQ_AI_ADDR_U\t0xFFFFFFFF\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_U_CQ_AI_ADDR_U_LOC\t0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L(x) \\\n-\t(0x10000fa0 + (x) * 0x1000)\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RST 0x0\n-\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RSVD0\t\t0x00000003\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L_CQ_AI_ADDR_L\t0xFFFFFFFC\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L_RSVD0_LOC\t\t0\n-#define DLB2_SYS_LDB_CQ_AI_ADDR_L_CQ_AI_ADDR_L_LOC\t2\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_U(x) \\\n-\t(0x10000fe4 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_U_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_U_CQ_AI_ADDR_U\t0xFFFFFFFF\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_U_CQ_AI_ADDR_U_LOC\t0\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L(x) \\\n-\t(0x10000fe0 + (x) * 0x1000)\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RST 0x0\n-\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RSVD0\t\t0x00000003\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L_CQ_AI_ADDR_L\t0xFFFFFFFC\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L_RSVD0_LOC\t\t0\n-#define DLB2_SYS_DIR_CQ_AI_ADDR_L_CQ_AI_ADDR_L_LOC\t2\n-\n-#define DLB2_SYS_WB_DIR_CQ_STATE(x) \\\n-\t(0x11c00000 + (x) * 0x1000)\n-#define DLB2_SYS_WB_DIR_CQ_STATE_RST 0x0\n-\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB0_V\t0x00000001\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB1_V\t0x00000002\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB2_V\t0x00000004\n-#define DLB2_SYS_WB_DIR_CQ_STATE_DIR_OPT\t0x00000008\n-#define DLB2_SYS_WB_DIR_CQ_STATE_CQ_OPT_CLR\t0x00000010\n-#define DLB2_SYS_WB_DIR_CQ_STATE_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB0_V_LOC\t\t0\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB1_V_LOC\t\t1\n-#define DLB2_SYS_WB_DIR_CQ_STATE_WB2_V_LOC\t\t2\n-#define DLB2_SYS_WB_DIR_CQ_STATE_DIR_OPT_LOC\t\t3\n-#define DLB2_SYS_WB_DIR_CQ_STATE_CQ_OPT_CLR_LOC\t4\n-#define DLB2_SYS_WB_DIR_CQ_STATE_RSVD0_LOC\t\t5\n-\n-#define DLB2_SYS_WB_LDB_CQ_STATE(x) \\\n-\t(0x11d00000 + (x) * 0x1000)\n-#define DLB2_SYS_WB_LDB_CQ_STATE_RST 0x0\n-\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB0_V\t0x00000001\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB1_V\t0x00000002\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB2_V\t0x00000004\n-#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD1\t0x00000008\n-#define DLB2_SYS_WB_LDB_CQ_STATE_CQ_OPT_CLR\t0x00000010\n-#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD0\t0xFFFFFFE0\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB0_V_LOC\t\t0\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB1_V_LOC\t\t1\n-#define DLB2_SYS_WB_LDB_CQ_STATE_WB2_V_LOC\t\t2\n-#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD1_LOC\t\t3\n-#define DLB2_SYS_WB_LDB_CQ_STATE_CQ_OPT_CLR_LOC\t4\n-#define DLB2_SYS_WB_LDB_CQ_STATE_RSVD0_LOC\t\t5\n-\n-#define DLB2_CHP_CFG_VAS_CRD(x) \\\n-\t(0x40000000 + (x) * 0x1000)\n-#define DLB2_CHP_CFG_VAS_CRD_RST 0x0\n-\n-#define DLB2_CHP_CFG_VAS_CRD_COUNT\t0x00007FFF\n-#define DLB2_CHP_CFG_VAS_CRD_RSVD0\t0xFFFF8000\n-#define DLB2_CHP_CFG_VAS_CRD_COUNT_LOC\t0\n-#define DLB2_CHP_CFG_VAS_CRD_RSVD0_LOC\t15\n-\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT(x) \\\n-\t(0x90b00000 + (x) * 0x1000)\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RST 0x0\n-\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_LIMIT\t0x00007FFF\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_V\t0x00008000\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RSVD0\t0xFFFF0000\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_LIMIT_LOC\t0\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_V_LOC\t\t15\n-#define DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RSVD0_LOC\t16\n-\n-#endif /* __DLB2_REGS_NEW_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 54b0207db..3661b940c 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -8,7 +8,7 @@\n #include \"dlb2_osdep.h\"\n #include \"dlb2_osdep_bitmap.h\"\n #include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs_new.h\"\n+#include \"dlb2_regs.h\"\n #include \"dlb2_resource.h\"\n \n #include \"../../dlb2_priv.h\"\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 1f6ccf8e4..b6ec85b47 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -13,7 +13,7 @@\n #include <rte_malloc.h>\n #include <rte_errno.h>\n \n-#include \"base/dlb2_regs_new.h\"\n+#include \"base/dlb2_regs.h\"\n #include \"base/dlb2_hw_types.h\"\n #include \"base/dlb2_resource.h\"\n #include \"base/dlb2_osdep.h\"\n",
    "prefixes": [
        "v4",
        "23/27"
    ]
}