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GET /api/patches/91503/?format=api
{ "id": 91503, "url": "https://patches.dpdk.org/api/patches/91503/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-20-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618451359-20693-20-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-20-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-15T01:49:11", "name": "[v4,19/27] event/dlb2: add v2.5 sequence number management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5a26e22071ace5a81aea4da3bceb4fcd8f89d5df", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-20-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16383, "url": "https://patches.dpdk.org/api/series/16383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383", "date": "2021-04-15T01:48:52", "name": "Add DLB v2.5", "version": 4, "mbox": "https://patches.dpdk.org/series/16383/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91503/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91503/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9E059A0562;\n\tThu, 15 Apr 2021 03:52:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 895E0161E93;\n\tThu, 15 Apr 2021 03:51:00 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 1AD84161E33\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:42 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:42 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:41 -0700" ], "IronPort-SDR": [ "\n 6yWuMnI877Kt5wUBtgmo/DlWA3QQ6rmYC+4LGghmNOJN3GS6M7UQTvTWu2QvMqZIEh41Hb66a2\n JgMfofX+Un3A==", "\n UAcRPOIDL6YEgNRYycwQpqmbln75o2IPik1VT3Ztx7n8ZER7rUhi5KvFvVHbHcnaMdKQo4Ho2s\n 11fZ/iQTk08Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"215272819\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"215272819\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569886\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net", "Date": "Wed, 14 Apr 2021 20:49:11 -0500", "Message-Id": "<1618451359-20693-20-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 19/27] event/dlb2: add v2.5 sequence number\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the low level HW functions that perform the sequence number\nmanagement functions. These include getting a groups number of\nsequence numbers per queue, managing in-use slots, getting the\ncurrent occupancy, and setting sequence numbers for a group.\n\nThe logic is very similar to what was done for v2.0,\nbut the new combined register map for v2.0 and v2.5\nuses new register names and bit names. Additionally,\nnew register access macros are used so that the code\ncan perform the correct action, based on the hardware.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 67 -----------\n drivers/event/dlb2/pf/base/dlb2_resource.h | 4 +-\n .../event/dlb2/pf/base/dlb2_resource_new.c | 105 ++++++++++++++++++\n 3 files changed, 107 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex d53cce643..e8a9d52f6 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -32,70 +32,3 @@\n #define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n \tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n \n-int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)\n-{\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\treturn hw->rsrcs.sn_groups[group_id].sequence_numbers_per_queue;\n-}\n-\n-int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,\n-\t\t\t\t\t unsigned int group_id)\n-{\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\treturn dlb2_sn_group_used_slots(&hw->rsrcs.sn_groups[group_id]);\n-}\n-\n-static void dlb2_log_set_group_sequence_numbers(struct dlb2_hw *hw,\n-\t\t\t\t\t\tunsigned int group_id,\n-\t\t\t\t\t\tunsigned long val)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB2 set group sequence numbers:\\n\");\n-\tDLB2_HW_DBG(hw, \"\\tGroup ID: %u\\n\", group_id);\n-\tDLB2_HW_DBG(hw, \"\\tValue: %lu\\n\", val);\n-}\n-\n-int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n-\t\t\t\t unsigned int group_id,\n-\t\t\t\t unsigned long val)\n-{\n-\tu32 valid_allocations[] = {64, 128, 256, 512, 1024};\n-\tunion dlb2_ro_pipe_grp_sn_mode r0 = { {0} };\n-\tstruct dlb2_sn_group *group;\n-\tint mode;\n-\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\tgroup = &hw->rsrcs.sn_groups[group_id];\n-\n-\t/*\n-\t * Once the first load-balanced queue using an SN group is configured,\n-\t * the group cannot be changed.\n-\t */\n-\tif (group->slot_use_bitmap != 0)\n-\t\treturn -EPERM;\n-\n-\tfor (mode = 0; mode < DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES; mode++)\n-\t\tif (val == valid_allocations[mode])\n-\t\t\tbreak;\n-\n-\tif (mode == DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES)\n-\t\treturn -EINVAL;\n-\n-\tgroup->mode = mode;\n-\tgroup->sequence_numbers_per_queue = val;\n-\n-\tr0.field.sn_mode_0 = hw->rsrcs.sn_groups[0].mode;\n-\tr0.field.sn_mode_1 = hw->rsrcs.sn_groups[1].mode;\n-\n-\tDLB2_CSR_WR(hw, DLB2_RO_PIPE_GRP_SN_MODE, r0.val);\n-\n-\tdlb2_log_set_group_sequence_numbers(hw, group_id, val);\n-\n-\treturn 0;\n-}\n-\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb2/pf/base/dlb2_resource.h\nindex 2e13193bb..00a0b6b57 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.h\n@@ -792,8 +792,8 @@ int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,\n * ordered queue is configured.\n */\n int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n-\t\t\t\t unsigned int group_id,\n-\t\t\t\t unsigned long val);\n+\t\t\t\t u32 group_id,\n+\t\t\t\t u32 val);\n \n /**\n * dlb2_reset_domain() - reset a scheduling domain\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 0f18bfeff..927b65568 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -6128,3 +6128,108 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n \tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);\n }\n \n+/**\n+ * dlb2_get_group_sequence_numbers() - return a group's number of SNs per queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the configured number of sequence numbers per queue\n+ * for the specified group.\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.\n+ */\n+int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, u32 group_id)\n+{\n+\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n+\t\treturn -EINVAL;\n+\n+\treturn hw->rsrcs.sn_groups[group_id].sequence_numbers_per_queue;\n+}\n+\n+/**\n+ * dlb2_get_group_sequence_number_occupancy() - return a group's in-use slots\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ *\n+ * This function returns the group's number of in-use slots (i.e. load-balanced\n+ * queues using the specified group).\n+ *\n+ * Return:\n+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.\n+ */\n+int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw, u32 group_id)\n+{\n+\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n+\t\treturn -EINVAL;\n+\n+\treturn dlb2_sn_group_used_slots(&hw->rsrcs.sn_groups[group_id]);\n+}\n+\n+static void dlb2_log_set_group_sequence_numbers(struct dlb2_hw *hw,\n+\t\t\t\t\t\tu32 group_id,\n+\t\t\t\t\t\tu32 val)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 set group sequence numbers:\\n\");\n+\tDLB2_HW_DBG(hw, \"\\tGroup ID: %u\\n\", group_id);\n+\tDLB2_HW_DBG(hw, \"\\tValue: %u\\n\", val);\n+}\n+\n+/**\n+ * dlb2_set_group_sequence_numbers() - assign a group's number of SNs per queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @group_id: sequence number group ID.\n+ * @val: requested amount of sequence numbers per queue.\n+ *\n+ * This function configures the group's number of sequence numbers per queue.\n+ * val can be a power-of-two between 32 and 1024, inclusive. This setting can\n+ * be configured until the first ordered load-balanced queue is configured, at\n+ * which point the configuration is locked.\n+ *\n+ * Return:\n+ * Returns 0 upon success; -EINVAL if group_id or val is invalid, -EPERM if an\n+ * ordered queue is configured.\n+ */\n+int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n+\t\t\t\t u32 group_id,\n+\t\t\t\t u32 val)\n+{\n+\tconst u32 valid_allocations[] = {64, 128, 256, 512, 1024};\n+\tstruct dlb2_sn_group *group;\n+\tu32 sn_mode = 0;\n+\tint mode;\n+\n+\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n+\t\treturn -EINVAL;\n+\n+\tgroup = &hw->rsrcs.sn_groups[group_id];\n+\n+\t/*\n+\t * Once the first load-balanced queue using an SN group is configured,\n+\t * the group cannot be changed.\n+\t */\n+\tif (group->slot_use_bitmap != 0)\n+\t\treturn -EPERM;\n+\n+\tfor (mode = 0; mode < DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES; mode++)\n+\t\tif (val == valid_allocations[mode])\n+\t\t\tbreak;\n+\n+\tif (mode == DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES)\n+\t\treturn -EINVAL;\n+\n+\tgroup->mode = mode;\n+\tgroup->sequence_numbers_per_queue = val;\n+\n+\tDLB2_BITS_SET(sn_mode, hw->rsrcs.sn_groups[0].mode,\n+\t\t DLB2_RO_GRP_SN_MODE_SN_MODE_0);\n+\tDLB2_BITS_SET(sn_mode, hw->rsrcs.sn_groups[1].mode,\n+\t\t DLB2_RO_GRP_SN_MODE_SN_MODE_1);\n+\n+\tDLB2_CSR_WR(hw, DLB2_RO_GRP_SN_MODE(hw->ver), sn_mode);\n+\n+\tdlb2_log_set_group_sequence_numbers(hw, group_id, val);\n+\n+\treturn 0;\n+}\n+\n", "prefixes": [ "v4", "19/27" ] }