Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/91502/?format=api
{ "id": 91502, "url": "https://patches.dpdk.org/api/patches/91502/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-19-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618451359-20693-19-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-19-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-15T01:49:10", "name": "[v4,18/27] event/dlb2: add v2.5 sparse cq mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "65989c9c0d54c98fe63613f7403bc0e1ee5630b8", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-19-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16383, "url": "https://patches.dpdk.org/api/series/16383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383", "date": "2021-04-15T01:48:52", "name": "Add DLB v2.5", "version": 4, "mbox": "https://patches.dpdk.org/series/16383/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91502/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91502/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA9E8A0562;\n\tThu, 15 Apr 2021 03:52:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4B737161E8E;\n\tThu, 15 Apr 2021 03:50:59 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id D7FE1161E37\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:41 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:41 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:40 -0700" ], "IronPort-SDR": [ "\n 7xFzpfoa4lMUGxQfxbbMFPL7sMXFzS1uHxmR23wWDhP04vWCYp1NpL+kYku/38SPf99WVN9NI5\n vNF5LhKeH96Q==", "\n 8/ekaPq1Uqbj6QEvjqJzttdZEtqfrgQNUffTxNX071o9QaWr3C73C09O+TGhgLN09x2qtIsUvB\n NXS4BN+r/iyg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"215272815\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"215272815\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569882\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net", "Date": "Wed, 14 Apr 2021 20:49:10 -0500", "Message-Id": "<1618451359-20693-19-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 18/27] event/dlb2: add v2.5 sparse cq mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the low level HW functions responsible for\nconfiguring sparse CQ mode, where each cache line\ncontains just one QE instead of 4.\n\nThe logic is very similar to what was done for v2.0,\nbut the new combined register map for v2.0 and v2.5\nuses new register names and bit names. Additionally,\nnew register access macros are used so that the code\ncan perform the correct action, based on the hardware.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 22 -----------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 39 +++++++++++++++++++\n 2 files changed, 39 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex f05f750f5..d53cce643 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -32,28 +32,6 @@\n #define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n \tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n \n-void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n-{\n-\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n-\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n-\n-\tr0.field.cfg_64bytes_qe_dir_cq_mode = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n-}\n-\n-void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n-{\n-\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n-\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n-\n-\tr0.field.cfg_64bytes_qe_ldb_cq_mode = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n-}\n-\n int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)\n {\n \tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 8cd1762cf..0f18bfeff 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -6089,3 +6089,42 @@ unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n \n \treturn num;\n }\n+\n+/**\n+ * dlb2_hw_enable_sparse_dir_cq_mode() - enable sparse mode for directed ports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+\n+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tDLB2_BIT_SET(ctrl,\n+\t\t DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE);\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);\n+}\n+\n+/**\n+ * dlb2_hw_enable_sparse_ldb_cq_mode() - enable sparse mode for load-balanced\n+ *\tports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tDLB2_BIT_SET(ctrl,\n+\t\t DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE);\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);\n+}\n+\n", "prefixes": [ "v4", "18/27" ] }