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GET /api/patches/91493/?format=api
{ "id": 91493, "url": "https://patches.dpdk.org/api/patches/91493/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-11-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618451359-20693-11-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618451359-20693-11-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-15T01:49:02", "name": "[v4,10/27] event/dlb2: add v2.5 create dir port", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8790b4205715719960850d1f4f4eb460baa02ddb", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618451359-20693-11-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16383, "url": "https://patches.dpdk.org/api/series/16383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16383", "date": "2021-04-15T01:48:52", "name": "Add DLB v2.5", "version": 4, "mbox": "https://patches.dpdk.org/series/16383/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91493/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91493/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5FF45A0562;\n\tThu, 15 Apr 2021 03:51:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 036D2161E34;\n\tThu, 15 Apr 2021 03:50:46 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 5B41D161E17\n for <dev@dpdk.org>; Thu, 15 Apr 2021 03:50:37 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 18:50:36 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga003.jf.intel.com with ESMTP; 14 Apr 2021 18:50:36 -0700" ], "IronPort-SDR": [ "\n gq9jckow17v8t3HkLTHFM54em/6AuLKFek6hm3gRTGTmxo257hgB6t2Sf+6SmHc6O313Vrdw1j\n Dp0jRftrXClg==", "\n Js8ISlHgIP60zGXPVHLO732K94+x0eFWBsmhuLqxcecR7ehJ7vmMfLof8U08CdKp4uiSUKaFfF\n IZa93hC4kCMg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9954\"; a=\"215272804\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"215272804\"", "E=Sophos;i=\"5.82,223,1613462400\"; d=\"scan'208\";a=\"382569845\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net", "Date": "Wed, 14 Apr 2021 20:49:02 -0500", "Message-Id": "<1618451359-20693-11-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618451359-20693-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 10/27] event/dlb2: add v2.5 create dir port", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the low level HW functions responsible for\ncreating directed ports. These functions create the\nproducer port (PP), configure the consumer queue (CQ),\nconfigure queue depth, and validate the port creation\narguments.\n\nThe logic is very similar to what was done for v2.0,\nbut the new combined register map for v2.0 and v2.5\nuses new register names and bit names. Additionally,\nnew register access macros are used so that the code\ncan perform the correct action, based on the hardware\nversion, v2.0 or v2.5.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 426 ------------------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 414 +++++++++++++++++\n 2 files changed, 414 insertions(+), 426 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 45d096eec..70c52e908 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -65,18 +65,6 @@ static inline void dlb2_flush_csr(struct dlb2_hw *hw)\n \tDLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);\n }\n \n-static void dlb2_dir_port_cq_enable(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_dir_pq_pair *port)\n-{\n-\tunion dlb2_lsp_cq_dir_dsbl reg;\n-\n-\treg.field.disabled = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_DIR_DSBL(port->id.phys_id), reg.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n static u32 dlb2_dir_queue_depth(struct dlb2_hw *hw,\n \t\t\t\tstruct dlb2_dir_pq_pair *queue)\n {\n@@ -1216,25 +1204,6 @@ int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n \treturn 0;\n }\n \n-static void\n-dlb2_log_create_dir_port_args(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t uintptr_t cq_dma_base,\n-\t\t\t struct dlb2_create_dir_port_args *args,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB2 create directed port arguments:\\n\");\n-\tif (vdev_req)\n-\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n-\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n-\t\t domain_id);\n-\tDLB2_HW_DBG(hw, \"\\tCQ depth: %d\\n\",\n-\t\t args->cq_depth);\n-\tDLB2_HW_DBG(hw, \"\\tCQ base address: 0x%lx\\n\",\n-\t\t cq_dma_base);\n-}\n-\n static struct dlb2_dir_pq_pair *\n dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,\n \t\t\t u32 id,\n@@ -1256,401 +1225,6 @@ dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,\n \treturn NULL;\n }\n \n-static int\n-dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,\n-\t\t\t\t u32 domain_id,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_dir_port_args *args,\n-\t\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\n-\tif (domain == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!domain->configured) {\n-\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (domain->started) {\n-\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/*\n-\t * If the user claims the queue is already configured, validate\n-\t * the queue ID, its domain, and whether the queue is configured.\n-\t */\n-\tif (args->queue_id != -1) {\n-\t\tstruct dlb2_dir_pq_pair *queue;\n-\n-\t\tqueue = dlb2_get_domain_used_dir_pq(hw,\n-\t\t\t\t\t\t args->queue_id,\n-\t\t\t\t\t\t vdev_req,\n-\t\t\t\t\t\t domain);\n-\n-\t\tif (queue == NULL || queue->domain_id.phys_id !=\n-\t\t\t\tdomain->id.phys_id ||\n-\t\t\t\t!queue->queue_configured) {\n-\t\t\tresp->status = DLB2_ST_INVALID_DIR_QUEUE_ID;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/*\n-\t * If the port's queue is not configured, validate that a free\n-\t * port-queue pair is available.\n-\t */\n-\tif (args->queue_id == -1 &&\n-\t dlb2_list_empty(&domain->avail_dir_pq_pairs)) {\n-\t\tresp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check cache-line alignment */\n-\tif ((cq_dma_base & 0x3F) != 0) {\n-\t\tresp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->cq_depth != 1 &&\n-\t args->cq_depth != 2 &&\n-\t args->cq_depth != 4 &&\n-\t args->cq_depth != 8 &&\n-\t args->cq_depth != 16 &&\n-\t args->cq_depth != 32 &&\n-\t args->cq_depth != 64 &&\n-\t args->cq_depth != 128 &&\n-\t args->cq_depth != 256 &&\n-\t args->cq_depth != 512 &&\n-\t args->cq_depth != 1024) {\n-\t\tresp->status = DLB2_ST_INVALID_CQ_DEPTH;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void dlb2_dir_port_configure_pp(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_dir_pq_pair *port,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tunion dlb2_sys_dir_pp2vas r0 = { {0} };\n-\tunion dlb2_sys_dir_pp_v r4 = { {0} };\n-\n-\tr0.field.vas = domain->id.phys_id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_PP2VAS(port->id.phys_id), r0.val);\n-\n-\tif (vdev_req) {\n-\t\tunion dlb2_sys_vf_dir_vpp2pp r1 = { {0} };\n-\t\tunion dlb2_sys_dir_pp2vdev r2 = { {0} };\n-\t\tunion dlb2_sys_vf_dir_vpp_v r3 = { {0} };\n-\t\tunsigned int offs;\n-\t\tu32 virt_id;\n-\n-\t\t/*\n-\t\t * DLB uses producer port address bits 17:12 to determine the\n-\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n-\t\t * through the PF MMIO window for the physical producer port,\n-\t\t * so for translation purposes the virtual and physical port\n-\t\t * IDs are equal.\n-\t\t */\n-\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n-\t\t\tvirt_id = port->id.virt_id;\n-\t\telse\n-\t\t\tvirt_id = port->id.phys_id;\n-\n-\t\tr1.field.pp = port->id.phys_id;\n-\n-\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) + virt_id;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP2PP(offs), r1.val);\n-\n-\t\tr2.field.vdev = vdev_id;\n-\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_SYS_DIR_PP2VDEV(port->id.phys_id),\n-\t\t\t r2.val);\n-\n-\t\tr3.field.vpp_v = 1;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), r3.val);\n-\t}\n-\n-\tr4.field.pp_v = 1;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_SYS_DIR_PP_V(port->id.phys_id),\n-\t\t r4.val);\n-}\n-\n-static int dlb2_dir_port_configure_cq(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_dir_pq_pair *port,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_dir_port_args *args,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tunion dlb2_sys_dir_cq_addr_l r0 = { {0} };\n-\tunion dlb2_sys_dir_cq_addr_u r1 = { {0} };\n-\tunion dlb2_sys_dir_cq2vf_pf_ro r2 = { {0} };\n-\tunion dlb2_chp_dir_cq_tkn_depth_sel r3 = { {0} };\n-\tunion dlb2_lsp_cq_dir_tkn_depth_sel_dsi r4 = { {0} };\n-\tunion dlb2_sys_dir_cq_fmt r9 = { {0} };\n-\tunion dlb2_sys_dir_cq_at r10 = { {0} };\n-\tunion dlb2_sys_dir_cq_pasid r11 = { {0} };\n-\tunion dlb2_chp_dir_cq2vas r12 = { {0} };\n-\n-\t/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */\n-\tr0.field.addr_l = cq_dma_base >> 6;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_L(port->id.phys_id), r0.val);\n-\n-\tr1.field.addr_u = cq_dma_base >> 32;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_U(port->id.phys_id), r1.val);\n-\n-\t/*\n-\t * 'ro' == relaxed ordering. This setting allows DLB2 to write\n-\t * cache lines out-of-order (but QEs within a cache line are always\n-\t * updated in-order).\n-\t */\n-\tr2.field.vf = vdev_id;\n-\tr2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);\n-\tr2.field.ro = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ2VF_PF_RO(port->id.phys_id), r2.val);\n-\n-\tif (args->cq_depth <= 8) {\n-\t\tr3.field.token_depth_select = 1;\n-\t} else if (args->cq_depth == 16) {\n-\t\tr3.field.token_depth_select = 2;\n-\t} else if (args->cq_depth == 32) {\n-\t\tr3.field.token_depth_select = 3;\n-\t} else if (args->cq_depth == 64) {\n-\t\tr3.field.token_depth_select = 4;\n-\t} else if (args->cq_depth == 128) {\n-\t\tr3.field.token_depth_select = 5;\n-\t} else if (args->cq_depth == 256) {\n-\t\tr3.field.token_depth_select = 6;\n-\t} else if (args->cq_depth == 512) {\n-\t\tr3.field.token_depth_select = 7;\n-\t} else if (args->cq_depth == 1024) {\n-\t\tr3.field.token_depth_select = 8;\n-\t} else {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: invalid CQ depth\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(port->id.phys_id),\n-\t\t r3.val);\n-\n-\t/*\n-\t * To support CQs with depth less than 8, program the token count\n-\t * register with a non-zero initial value. Operations such as domain\n-\t * reset must take this initial value into account when quiescing the\n-\t * CQ.\n-\t */\n-\tport->init_tkn_cnt = 0;\n-\n-\tif (args->cq_depth < 8) {\n-\t\tunion dlb2_lsp_cq_dir_tkn_cnt r13 = { {0} };\n-\n-\t\tport->init_tkn_cnt = 8 - args->cq_depth;\n-\n-\t\tr13.field.count = port->init_tkn_cnt;\n-\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),\n-\t\t\t r13.val);\n-\t} else {\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),\n-\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT_RST);\n-\t}\n-\n-\tr4.field.token_depth_select = r3.field.token_depth_select;\n-\tr4.field.disable_wb_opt = 0;\n-\tr4.field.ignore_depth = 0;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(port->id.phys_id),\n-\t\t r4.val);\n-\n-\t/* Reset the CQ write pointer */\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_CHP_DIR_CQ_WPTR(port->id.phys_id),\n-\t\t DLB2_CHP_DIR_CQ_WPTR_RST);\n-\n-\t/* Virtualize the PPID */\n-\tr9.field.keep_pf_ppid = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_FMT(port->id.phys_id), r9.val);\n-\n-\t/*\n-\t * Address translation (AT) settings: 0: untranslated, 2: translated\n-\t * (see ATS spec regarding Address Type field for more details)\n-\t */\n-\tr10.field.cq_at = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_AT(port->id.phys_id), r10.val);\n-\n-\tif (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {\n-\t\tr11.field.pasid = hw->pasid[vdev_id];\n-\t\tr11.field.fmt2 = 1;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_SYS_DIR_CQ_PASID(port->id.phys_id),\n-\t\t r11.val);\n-\n-\tr12.field.cq2vas = domain->id.phys_id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_DIR_CQ2VAS(port->id.phys_id), r12.val);\n-\n-\treturn 0;\n-}\n-\n-static int dlb2_configure_dir_port(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_dir_pq_pair *port,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_dir_port_args *args,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tint ret;\n-\n-\tret = dlb2_dir_port_configure_cq(hw,\n-\t\t\t\t\t domain,\n-\t\t\t\t\t port,\n-\t\t\t\t\t cq_dma_base,\n-\t\t\t\t\t args,\n-\t\t\t\t\t vdev_req,\n-\t\t\t\t\t vdev_id);\n-\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tdlb2_dir_port_configure_pp(hw,\n-\t\t\t\t domain,\n-\t\t\t\t port,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\n-\tdlb2_dir_port_cq_enable(hw, port);\n-\n-\tport->enabled = true;\n-\n-\tport->port_configured = true;\n-\n-\treturn 0;\n-}\n-\n-/**\n- * dlb2_hw_create_dir_port() - Allocate and initialize a DLB directed port\n- *\tand queue. The port/queue pair have the same ID and name.\n- * @hw:\tContains the current state of the DLB2 hardware.\n- * @domain_id: Domain ID\n- * @args: User-provided arguments.\n- * @cq_dma_base: Base DMA address for consumer queue memory\n- * @resp: Response to user.\n- * @vdev_req: Request came from a virtual device.\n- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.\n- *\n- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to\n- * satisfy a request, resp->status will be set accordingly.\n- */\n-int dlb2_hw_create_dir_port(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t struct dlb2_create_dir_port_args *args,\n-\t\t\t uintptr_t cq_dma_base,\n-\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_dir_pq_pair *port;\n-\tstruct dlb2_hw_domain *domain;\n-\tint ret;\n-\n-\tdlb2_log_create_dir_port_args(hw,\n-\t\t\t\t domain_id,\n-\t\t\t\t cq_dma_base,\n-\t\t\t\t args,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\n-\t/*\n-\t * Verify that hardware resources are available before attempting to\n-\t * satisfy the request. This simplifies the error unwinding code.\n-\t */\n-\tret = dlb2_verify_create_dir_port_args(hw,\n-\t\t\t\t\t domain_id,\n-\t\t\t\t\t cq_dma_base,\n-\t\t\t\t\t args,\n-\t\t\t\t\t resp,\n-\t\t\t\t\t vdev_req,\n-\t\t\t\t\t vdev_id);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\n-\tif (args->queue_id != -1)\n-\t\tport = dlb2_get_domain_used_dir_pq(hw,\n-\t\t\t\t\t\t args->queue_id,\n-\t\t\t\t\t\t vdev_req,\n-\t\t\t\t\t\t domain);\n-\telse\n-\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_dir_pq_pairs,\n-\t\t\t\t\t typeof(*port));\n-\tif (port == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: no available dir ports\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tret = dlb2_configure_dir_port(hw,\n-\t\t\t\t domain,\n-\t\t\t\t port,\n-\t\t\t\t cq_dma_base,\n-\t\t\t\t args,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\t/*\n-\t * Configuration succeeded, so move the resource from the 'avail' to\n-\t * the 'used' list (if it's not already there).\n-\t */\n-\tif (args->queue_id == -1) {\n-\t\tdlb2_list_del(&domain->avail_dir_pq_pairs, &port->domain_list);\n-\n-\t\tdlb2_list_add(&domain->used_dir_pq_pairs, &port->domain_list);\n-\t}\n-\n-\tresp->status = 0;\n-\tresp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;\n-\n-\treturn 0;\n-}\n-\n static void dlb2_configure_dir_queue(struct dlb2_hw *hw,\n \t\t\t\t struct dlb2_hw_domain *domain,\n \t\t\t\t struct dlb2_dir_pq_pair *queue,\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 2eb39e23d..4e4b390dd 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -4443,3 +4443,417 @@ int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,\n \n \treturn 0;\n }\n+\n+static void\n+dlb2_log_create_dir_port_args(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t uintptr_t cq_dma_base,\n+\t\t\t struct dlb2_create_dir_port_args *args,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 create directed port arguments:\\n\");\n+\tif (vdev_req)\n+\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n+\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n+\t\t domain_id);\n+\tDLB2_HW_DBG(hw, \"\\tCQ depth: %d\\n\",\n+\t\t args->cq_depth);\n+\tDLB2_HW_DBG(hw, \"\\tCQ base address: 0x%lx\\n\",\n+\t\t cq_dma_base);\n+}\n+\n+static struct dlb2_dir_pq_pair *\n+dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,\n+\t\t\t u32 id,\n+\t\t\t bool vdev_req,\n+\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter;\n+\tstruct dlb2_dir_pq_pair *port;\n+\tRTE_SET_USED(iter);\n+\n+\tif (id >= DLB2_MAX_NUM_DIR_PORTS(hw->ver))\n+\t\treturn NULL;\n+\n+\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter) {\n+\t\tif ((!vdev_req && port->id.phys_id == id) ||\n+\t\t (vdev_req && port->id.virt_id == id))\n+\t\t\treturn port;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_dir_port_args *args,\n+\t\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id,\n+\t\t\t\t struct dlb2_hw_domain **out_domain,\n+\t\t\t\t struct dlb2_dir_pq_pair **out_port)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_dir_pq_pair *pq;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n+\n+\tif (!domain) {\n+\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!domain->configured) {\n+\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (domain->started) {\n+\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->queue_id != -1) {\n+\t\t/*\n+\t\t * If the user claims the queue is already configured, validate\n+\t\t * the queue ID, its domain, and whether the queue is\n+\t\t * configured.\n+\t\t */\n+\t\tpq = dlb2_get_domain_used_dir_pq(hw,\n+\t\t\t\t\t\t args->queue_id,\n+\t\t\t\t\t\t vdev_req,\n+\t\t\t\t\t\t domain);\n+\n+\t\tif (!pq || pq->domain_id.phys_id != domain->id.phys_id ||\n+\t\t !pq->queue_configured) {\n+\t\t\tresp->status = DLB2_ST_INVALID_DIR_QUEUE_ID;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * If the port's queue is not configured, validate that a free\n+\t\t * port-queue pair is available.\n+\t\t */\n+\t\tpq = DLB2_DOM_LIST_HEAD(domain->avail_dir_pq_pairs,\n+\t\t\t\t\ttypeof(*pq));\n+\t\tif (!pq) {\n+\t\t\tresp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* Check cache-line alignment */\n+\tif ((cq_dma_base & 0x3F) != 0) {\n+\t\tresp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!dlb2_cq_depth_is_valid(args->cq_depth)) {\n+\t\tresp->status = DLB2_ST_INVALID_CQ_DEPTH;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*out_domain = domain;\n+\t*out_port = pq;\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_dir_port_configure_pp(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_dir_pq_pair *port,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tu32 reg = 0;\n+\n+\tDLB2_BITS_SET(reg, domain->id.phys_id, DLB2_SYS_DIR_PP2VAS_VAS);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_PP2VAS(port->id.phys_id), reg);\n+\n+\tif (vdev_req) {\n+\t\tunsigned int offs;\n+\t\tu32 virt_id;\n+\n+\t\t/*\n+\t\t * DLB uses producer port address bits 17:12 to determine the\n+\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n+\t\t * through the PF MMIO window for the physical producer port,\n+\t\t * so for translation purposes the virtual and physical port\n+\t\t * IDs are equal.\n+\t\t */\n+\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\tvirt_id = port->id.virt_id;\n+\t\telse\n+\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, port->id.phys_id, DLB2_SYS_VF_DIR_VPP2PP_PP);\n+\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) + virt_id;\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP2PP(offs), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, vdev_id, DLB2_SYS_DIR_PP2VDEV_VDEV);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_PP2VDEV(port->id.phys_id), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BIT_SET(reg, DLB2_SYS_VF_DIR_VPP_V_VPP_V);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), reg);\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BIT_SET(reg, DLB2_SYS_DIR_PP_V_PP_V);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_PP_V(port->id.phys_id), reg);\n+}\n+\n+static int dlb2_dir_port_configure_cq(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_dir_pq_pair *port,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_dir_port_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tu32 reg = 0;\n+\tu32 ds = 0;\n+\n+\t/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */\n+\tDLB2_BITS_SET(reg, cq_dma_base >> 6, DLB2_SYS_DIR_CQ_ADDR_L_ADDR_L);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_L(port->id.phys_id), reg);\n+\n+\treg = cq_dma_base >> 32;\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_U(port->id.phys_id), reg);\n+\n+\t/*\n+\t * 'ro' == relaxed ordering. This setting allows DLB2 to write\n+\t * cache lines out-of-order (but QEs within a cache line are always\n+\t * updated in-order).\n+\t */\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, vdev_id, DLB2_SYS_DIR_CQ2VF_PF_RO_VF);\n+\tDLB2_BITS_SET(reg, !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV),\n+\t\t DLB2_SYS_DIR_CQ2VF_PF_RO_IS_PF);\n+\tDLB2_BIT_SET(reg, DLB2_SYS_DIR_CQ2VF_PF_RO_RO);\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ2VF_PF_RO(port->id.phys_id), reg);\n+\n+\tif (args->cq_depth <= 8) {\n+\t\tds = 1;\n+\t} else if (args->cq_depth == 16) {\n+\t\tds = 2;\n+\t} else if (args->cq_depth == 32) {\n+\t\tds = 3;\n+\t} else if (args->cq_depth == 64) {\n+\t\tds = 4;\n+\t} else if (args->cq_depth == 128) {\n+\t\tds = 5;\n+\t} else if (args->cq_depth == 256) {\n+\t\tds = 6;\n+\t} else if (args->cq_depth == 512) {\n+\t\tds = 7;\n+\t} else if (args->cq_depth == 1024) {\n+\t\tds = 8;\n+\t} else {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: invalid CQ depth\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, ds,\n+\t\t DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\t/*\n+\t * To support CQs with depth less than 8, program the token count\n+\t * register with a non-zero initial value. Operations such as domain\n+\t * reset must take this initial value into account when quiescing the\n+\t * CQ.\n+\t */\n+\tport->init_tkn_cnt = 0;\n+\n+\tif (args->cq_depth < 8) {\n+\t\treg = 0;\n+\t\tport->init_tkn_cnt = 8 - args->cq_depth;\n+\n+\t\tDLB2_BITS_SET(reg, port->init_tkn_cnt,\n+\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT_COUNT);\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT(hw->ver, port->id.phys_id),\n+\t\t\t reg);\n+\t} else {\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT(hw->ver, port->id.phys_id),\n+\t\t\t DLB2_LSP_CQ_DIR_TKN_CNT_RST);\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, ds,\n+\t\t DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_TOKEN_DEPTH_SELECT_V2);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(hw->ver,\n+\t\t\t\t\t\t port->id.phys_id),\n+\t\t reg);\n+\n+\t/* Reset the CQ write pointer */\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_DIR_CQ_WPTR(hw->ver, port->id.phys_id),\n+\t\t DLB2_CHP_DIR_CQ_WPTR_RST);\n+\n+\t/* Virtualize the PPID */\n+\treg = 0;\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_FMT(port->id.phys_id), reg);\n+\n+\t/*\n+\t * Address translation (AT) settings: 0: untranslated, 2: translated\n+\t * (see ATS spec regarding Address Type field for more details)\n+\t */\n+\tif (hw->ver == DLB2_HW_V2) {\n+\t\treg = 0;\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_AT(port->id.phys_id), reg);\n+\t}\n+\n+\tif (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {\n+\t\tDLB2_BITS_SET(reg, hw->pasid[vdev_id],\n+\t\t\t DLB2_SYS_DIR_CQ_PASID_PASID);\n+\t\tDLB2_BIT_SET(reg, DLB2_SYS_DIR_CQ_PASID_FMT2);\n+\t}\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_PASID(hw->ver, port->id.phys_id), reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, domain->id.phys_id, DLB2_CHP_DIR_CQ2VAS_CQ2VAS);\n+\tDLB2_CSR_WR(hw, DLB2_CHP_DIR_CQ2VAS(hw->ver, port->id.phys_id), reg);\n+\n+\treturn 0;\n+}\n+\n+static int dlb2_configure_dir_port(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_dir_pq_pair *port,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_dir_port_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tint ret;\n+\n+\tret = dlb2_dir_port_configure_cq(hw,\n+\t\t\t\t\t domain,\n+\t\t\t\t\t port,\n+\t\t\t\t\t cq_dma_base,\n+\t\t\t\t\t args,\n+\t\t\t\t\t vdev_req,\n+\t\t\t\t\t vdev_id);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdlb2_dir_port_configure_pp(hw,\n+\t\t\t\t domain,\n+\t\t\t\t port,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\n+\tdlb2_dir_port_cq_enable(hw, port);\n+\n+\tport->enabled = true;\n+\n+\tport->port_configured = true;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_hw_create_dir_port() - create a directed port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.\n+ *\n+ * This function creates a directed port.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_req is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t pointer address is not properly aligned, the domain is not\n+ *\t configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_dir_port(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_create_dir_port_args *args,\n+\t\t\t uintptr_t cq_dma_base,\n+\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_dir_pq_pair *port;\n+\tstruct dlb2_hw_domain *domain;\n+\tint ret;\n+\n+\tdlb2_log_create_dir_port_args(hw,\n+\t\t\t\t domain_id,\n+\t\t\t\t cq_dma_base,\n+\t\t\t\t args,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\n+\t/*\n+\t * Verify that hardware resources are available before attempting to\n+\t * satisfy the request. This simplifies the error unwinding code.\n+\t */\n+\tret = dlb2_verify_create_dir_port_args(hw,\n+\t\t\t\t\t domain_id,\n+\t\t\t\t\t cq_dma_base,\n+\t\t\t\t\t args,\n+\t\t\t\t\t resp,\n+\t\t\t\t\t vdev_req,\n+\t\t\t\t\t vdev_id,\n+\t\t\t\t\t &domain,\n+\t\t\t\t\t &port);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dlb2_configure_dir_port(hw,\n+\t\t\t\t domain,\n+\t\t\t\t port,\n+\t\t\t\t cq_dma_base,\n+\t\t\t\t args,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * Configuration succeeded, so move the resource from the 'avail' to\n+\t * the 'used' list (if it's not already there).\n+\t */\n+\tif (args->queue_id == -1) {\n+\t\tdlb2_list_del(&domain->avail_dir_pq_pairs, &port->domain_list);\n+\n+\t\tdlb2_list_add(&domain->used_dir_pq_pairs, &port->domain_list);\n+\t}\n+\n+\tresp->status = 0;\n+\tresp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v4", "10/27" ] }