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GET /api/patches/91456/?format=api
{ "id": 91456, "url": "https://patches.dpdk.org/api/patches/91456/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech>", "list_archive_url": "https://inbox.dpdk.org/dev/1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech", "date": "2021-04-14T12:58:38", "name": "[v20,3/3] config: fix Arm implementer and its SoCs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "44d32628975da96957a1ca63800cea4f037c2649", "submitter": { "id": 1626, "url": "https://patches.dpdk.org/api/people/1626/?format=api", "name": "Juraj Linkeš", "email": "juraj.linkes@pantheon.tech" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech/mbox/", "series": [ { "id": 16372, "url": "https://patches.dpdk.org/api/series/16372/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16372", "date": "2021-04-14T12:58:35", "name": "Arm build options rework", "version": 20, "mbox": "https://patches.dpdk.org/series/16372/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91456/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91456/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2DEDFA0562;\n\tWed, 14 Apr 2021 14:59:05 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DA7D1161AAA;\n\tWed, 14 Apr 2021 14:58:51 +0200 (CEST)", "from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20])\n by mails.dpdk.org (Postfix) with ESMTP id CCA03161A95\n for <dev@dpdk.org>; Wed, 14 Apr 2021 14:58:46 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n by lb.pantheon.sk (Postfix) with ESMTP id 04D62C566D;\n Wed, 14 Apr 2021 14:58:44 +0200 (CEST)", "from lb.pantheon.sk ([127.0.0.1])\n by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id 4Tsf1ITSKCh1; Wed, 14 Apr 2021 14:58:44 +0200 (CEST)", "from service-node1.lab.pantheon.local (unknown [46.229.239.141])\n by lb.pantheon.sk (Postfix) with ESMTP id 96E28C5671;\n Wed, 14 Apr 2021 14:58:41 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at siecit.sk", "From": "=?utf-8?q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech>", "To": "bruce.richardson@intel.com, Ruifeng.Wang@arm.com,\n Honnappa.Nagarahalli@arm.com, Phil.Yang@arm.com, vcchunga@amazon.com,\n Dharmik.Thakkar@arm.com, jerinjacobk@gmail.com, hemant.agrawal@nxp.com,\n ajit.khaparde@broadcom.com, ferruh.yigit@intel.com, aboyer@pensando.io", "Cc": "dev@dpdk.org, =?utf-8?q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech>,\n lironh@marvell.com, yskoh@mellanox.com", "Date": "Wed, 14 Apr 2021 14:58:38 +0200", "Message-Id": "<1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1618405118-20187-1-git-send-email-juraj.linkes@pantheon.tech>", "References": "<1617957679-7751-1-git-send-email-juraj.linkes@pantheon.tech>\n <1618405118-20187-1-git-send-email-juraj.linkes@pantheon.tech>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v20 3/3] config: fix Arm implementer and its SoCs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Fix the implementer and part number of DPAA and ARMADA SoCs.\nThe current values of 16 cores and 1 NUMA node don't cover all SoCs from\nthe Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.\nIncrease these to 64 and 4 to widen the coverage.\nAlso increase the neoverse-n1 MAX_LCORE and MAX_NUMA_NODES to reflect\nnew available hardware (Amplere Altra).\nAdd configuration to SoC options where smaller values are needed.\n\nFixes: 6ec78c2463ac (\"build: add meson support for dpaaX platforms\")\nCc: hemant.agrawal@nxp.com\nFixes: dd1cd845c102 (\"config: add Marvell ARMADA based on armv8-a\")\nCc: lironh@marvell.com\nFixes: d97108a33231 (\"config: change defaults of armv8\")\nCc: yskoh@mellanox.com\n\nSigned-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nReviewed-by: Liron Himi <lironh@marvell.com>\nAcked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n config/arm/meson.build | 60 +++++++++++++++++++-----------------------\n 1 file changed, 27 insertions(+), 33 deletions(-)", "diff": "diff --git a/config/arm/meson.build b/config/arm/meson.build\nindex c484fe26c0..1b7c4c1cc6 100644\n--- a/config/arm/meson.build\n+++ b/config/arm/meson.build\n@@ -57,7 +57,8 @@ part_number_config_arm = {\n \t\t\t['RTE_MACHINE', '\"neoverse-n1\"'],\n \t\t\t['RTE_ARM_FEATURE_ATOMICS', true],\n \t\t\t['RTE_MAX_MEM_MB', 1048576],\n-\t\t\t['RTE_MAX_LCORE', 80]\n+\t\t\t['RTE_MAX_LCORE', 160],\n+\t\t\t['RTE_MAX_NUMA_NODES', 2]\n \t\t]\n \t},\n \t'0xd49': {\n@@ -65,7 +66,8 @@ part_number_config_arm = {\n \t\t'flags': [\n \t\t\t['RTE_MACHINE', '\"neoverse-n2\"'],\n \t\t\t['RTE_ARM_FEATURE_ATOMICS', true],\n-\t\t\t['RTE_MAX_LCORE', 64]\n+\t\t\t['RTE_MAX_LCORE', 64],\n+\t\t\t['RTE_MAX_NUMA_NODES', 1]\n \t\t]\n \t}\n }\n@@ -75,8 +77,8 @@ implementer_arm = {\n \t\t['RTE_MACHINE', '\"armv8a\"'],\n \t\t['RTE_USE_C11_MEM_MODEL', true],\n \t\t['RTE_CACHE_LINE_SIZE', 64],\n-\t\t['RTE_MAX_LCORE', 16],\n-\t\t['RTE_MAX_NUMA_NODES', 1]\n+\t\t['RTE_MAX_LCORE', 64],\n+\t\t['RTE_MAX_NUMA_NODES', 4]\n \t],\n \t'part_number_config': part_number_config_arm\n }\n@@ -158,39 +160,13 @@ implementer_qualcomm = {\n \t}\n }\n \n-implementer_marvell = {\n-\t'description': 'Marvell ARMADA',\n-\t'flags': [\n-\t\t['RTE_MACHINE', '\"armv8a\"'],\n-\t\t['RTE_CACHE_LINE_SIZE', 64],\n-\t\t['RTE_MAX_LCORE', 16],\n-\t\t['RTE_MAX_NUMA_NODES', 1]\n-\t],\n-\t'part_number_config': part_number_config_arm\n-}\n-\n-implementer_dpaa = {\n-\t'description': 'NXP DPAA',\n-\t'flags': [\n-\t\t['RTE_MACHINE', '\"dpaa\"'],\n-\t\t['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],\n-\t\t['RTE_USE_C11_MEM_MODEL', true],\n-\t\t['RTE_CACHE_LINE_SIZE', 64],\n-\t\t['RTE_MAX_LCORE', 16],\n-\t\t['RTE_MAX_NUMA_NODES', 1]\n-\t],\n-\t'part_number_config': part_number_config_arm\n-}\n-\n ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)\n implementers = {\n \t'generic': implementer_generic,\n \t'0x41': implementer_arm,\n \t'0x43': implementer_cavium,\n \t'0x50': implementer_ampere,\n-\t'0x51': implementer_qualcomm,\n-\t'0x56': implementer_marvell,\n-\t'dpaa': implementer_dpaa\n+\t'0x51': implementer_qualcomm\n }\n \n # soc specific aarch64 flags have the highest priority\n@@ -203,8 +179,12 @@ soc_generic = {\n \n soc_armada = {\n \t'description': 'Marvell ARMADA',\n-\t'implementer': '0x56',\n+\t'implementer': '0x41',\n \t'part_number': '0xd08',\n+\t'flags': [\n+\t\t['RTE_MAX_LCORE', 16],\n+\t\t['RTE_MAX_NUMA_NODES', 1]\n+\t],\n \t'numa': false\n }\n \n@@ -212,13 +192,23 @@ soc_bluefield = {\n \t'description': 'NVIDIA BlueField',\n \t'implementer': '0x41',\n \t'part_number': '0xd08',\n+\t'flags': [\n+\t\t['RTE_MAX_LCORE', 16],\n+\t\t['RTE_MAX_NUMA_NODES', 1]\n+\t],\n \t'numa': false\n }\n \n soc_dpaa = {\n \t'description': 'NXP DPAA',\n-\t'implementer': 'dpaa',\n+\t'implementer': '0x41',\n \t'part_number': '0xd08',\n+\t'flags': [\n+\t\t['RTE_MACHINE', '\"dpaa\"'],\n+\t\t['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],\n+\t\t['RTE_MAX_LCORE', 16],\n+\t\t['RTE_MAX_NUMA_NODES', 1]\n+\t],\n \t'numa': false\n }\n \n@@ -262,6 +252,10 @@ soc_octeontx2 = {\n soc_stingray = {\n \t'description': 'Broadcom Stingray',\n \t'implementer': '0x41',\n+\t'flags': [\n+\t\t['RTE_MAX_LCORE', 16],\n+\t\t['RTE_MAX_NUMA_NODES', 1]\n+\t],\n \t'part_number': '0xd08',\n \t'numa': false\n }\n", "prefixes": [ "v20", "3/3" ] }