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GET /api/patches/91319/?format=api
{ "id": 91319, "url": "https://patches.dpdk.org/api/patches/91319/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-22-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618344896-2090-22-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618344896-2090-22-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-13T20:14:51", "name": "[v3,21/26] event/dlb2: use new implementation of HW types header", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "68bece27bffe7544294f4cdda0fd9554f358d926", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-22-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16345, "url": "https://patches.dpdk.org/api/series/16345/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16345", "date": "2021-04-13T20:14:31", "name": "Add DLB V2.5", "version": 3, "mbox": "https://patches.dpdk.org/series/16345/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91319/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91319/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 04E24A0524;\n\tTue, 13 Apr 2021 22:18:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9E884161361;\n\tTue, 13 Apr 2021 22:16:45 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 5A3B11612EA\n for <dev@dpdk.org>; Tue, 13 Apr 2021 22:16:23 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 13:16:22 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:21 -0700" ], "IronPort-SDR": [ "\n eWryjRff5+/Yu+vpJyE0g68bX3soAs6pc+JH34Y7WifLsmTzbuFx0mvYrDi3psHEllVg5OhaxQ\n ljbWAry3GsEw==", "\n fw4fDwz1Q2bYKr05RgHVIQB71dEPG6MSkYocvwZzIpBMjV7ecyCeHZrB8FBkkNA9fqG5QirIMH\n Qs51R2Orpsgw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"194519748\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"194519748\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"424406592\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Tue, 13 Apr 2021 15:14:51 -0500", "Message-Id": "<1618344896-2090-22-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 21/26] event/dlb2: use new implementation of\n HW types header", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "As support for DLB v2.5 was added, modifications were made to\ndlb_hw_types_new.h, but the old file needed to be preserved during\nthe port in order to meet the requirement that individual patches in\na series each compile successfully. Since the DLB v2.5 support is\ncompletely integrated, it is now safe to remove the old (original)\nfile, as well as the DLB2_USE_NEW_HEADERS define that was used to\ncontrol which version of the file was to be included in certain\nsource files.\nIt is now safe to rename the new file, and use it unconditionally\nin all DLB source files.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_hw_types.h | 38 +-\n .../event/dlb2/pf/base/dlb2_hw_types_new.h | 357 ------------------\n drivers/event/dlb2/pf/base/dlb2_resource.c | 4 +-\n drivers/event/dlb2/pf/dlb2_main.c | 4 +-\n drivers/event/dlb2/pf/dlb2_main.h | 4 -\n drivers/event/dlb2/pf/dlb2_pf.c | 4 +-\n 6 files changed, 33 insertions(+), 378 deletions(-)\n delete mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nindex b007e1674..4a6037775 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -2,14 +2,21 @@\n * Copyright(c) 2016-2020 Intel Corporation\n */\n \n-#ifndef __DLB2_HW_TYPES_H\n-#define __DLB2_HW_TYPES_H\n+#ifndef __DLB2_HW_TYPES_NEW_H\n+#define __DLB2_HW_TYPES_NEW_H\n \n #include \"../../dlb2_priv.h\"\n #include \"dlb2_user.h\"\n \n #include \"dlb2_osdep_list.h\"\n #include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs_new.h\"\n+\n+#define DLB2_BITS_SET(x, val, mask)\t(x = ((x) & ~(mask)) \\\n+\t\t\t\t | (((val) << (mask##_LOC)) & (mask)))\n+#define DLB2_BITS_CLR(x, mask)\t(x &= ~(mask))\n+#define DLB2_BIT_SET(x, mask)\t((x) |= (mask))\n+#define DLB2_BITS_GET(x, mask)\t(((x) & (mask)) >> (mask##_LOC))\n \n #define DLB2_MAX_NUM_VDEVS\t\t\t16\n #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n@@ -141,7 +148,7 @@ struct dlb2_dir_pq_pair {\n };\n \n enum dlb2_qid_map_state {\n-\t/* The slot doesn't contain a valid queue mapping */\n+\t/* The slot does not contain a valid queue mapping */\n \tDLB2_QUEUE_UNMAPPED,\n \t/* The slot contains a valid queue mapping */\n \tDLB2_QUEUE_MAPPED,\n@@ -174,6 +181,7 @@ struct dlb2_ldb_port {\n \tu32 hist_list_entry_base;\n \tu32 hist_list_entry_limit;\n \tu32 ref_cnt;\n+\tu8 cq_depth;\n \tu8 init_tkn_cnt;\n \tu8 num_pending_removals;\n \tu8 num_mappings;\n@@ -245,8 +253,15 @@ struct dlb2_hw_domain {\n \tu32 avail_hist_list_entries;\n \tu32 hist_list_entry_base;\n \tu32 hist_list_entry_offset;\n-\tu32 num_ldb_credits;\n-\tu32 num_dir_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu32 num_ldb_credits;\n+\t\t\tu32 num_dir_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tu32 num_credits;\n+\t\t};\n+\t};\n \tu32 num_avail_aqed_entries;\n \tu32 num_used_aqed_entries;\n \tstruct dlb2_resource_id id;\n@@ -269,8 +284,15 @@ struct dlb2_function_resources {\n \tu32 num_avail_ldb_queues;\n \tu32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n \tu32 num_avail_dir_pq_pairs;\n-\tu32 num_avail_qed_entries;\n-\tu32 num_avail_dqed_entries;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu32 num_avail_qed_entries;\n+\t\t\tu32 num_avail_dqed_entries;\n+\t\t};\n+\t\tstruct {\n+\t\t\tu32 num_avail_entries;\n+\t\t};\n+\t};\n \tu32 num_avail_aqed_entries;\n \tu8 locked; /* (VDEV only) */\n };\n@@ -332,4 +354,4 @@ struct dlb2_hw {\n \tunsigned int pasid[DLB2_MAX_NUM_VDEVS];\n };\n \n-#endif /* __DLB2_HW_TYPES_H */\n+#endif /* __DLB2_HW_TYPES_NEW_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h b/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h\ndeleted file mode 100644\nindex 4a6037775..000000000\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h\n+++ /dev/null\n@@ -1,357 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2020 Intel Corporation\n- */\n-\n-#ifndef __DLB2_HW_TYPES_NEW_H\n-#define __DLB2_HW_TYPES_NEW_H\n-\n-#include \"../../dlb2_priv.h\"\n-#include \"dlb2_user.h\"\n-\n-#include \"dlb2_osdep_list.h\"\n-#include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs_new.h\"\n-\n-#define DLB2_BITS_SET(x, val, mask)\t(x = ((x) & ~(mask)) \\\n-\t\t\t\t | (((val) << (mask##_LOC)) & (mask)))\n-#define DLB2_BITS_CLR(x, mask)\t(x &= ~(mask))\n-#define DLB2_BIT_SET(x, mask)\t((x) |= (mask))\n-#define DLB2_BITS_GET(x, mask)\t(((x) & (mask)) >> (mask##_LOC))\n-\n-#define DLB2_MAX_NUM_VDEVS\t\t\t16\n-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n-#define DLB2_NUM_ARB_WEIGHTS\t\t\t8\n-#define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n-#define DLB2_MAX_WEIGHT\t\t\t\t255\n-#define DLB2_NUM_COS_DOMAINS\t\t\t4\n-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n-#define DLB2_MAX_CQ_COMP_CHECK_LOOPS\t\t409600\n-#define DLB2_MAX_QID_EMPTY_CHECK_LOOPS\t\t(32 * 64 * 1024 * (800 / 30))\n-\n-#define DLB2_FUNC_BAR\t\t\t\t0\n-#define DLB2_CSR_BAR\t\t\t\t2\n-\n-#define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710\n-#define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711\n-\n-#define PCI_DEVICE_ID_INTEL_DLB2_5_PF 0x2714\n-#define PCI_DEVICE_ID_INTEL_DLB2_5_VF 0x2715\n-\n-#define DLB2_ALARM_HW_SOURCE_SYS 0\n-#define DLB2_ALARM_HW_SOURCE_DLB 1\n-\n-#define DLB2_ALARM_HW_UNIT_CHP 4\n-\n-#define DLB2_ALARM_SYS_AID_ILLEGAL_QID\t\t3\n-#define DLB2_ALARM_SYS_AID_DISABLED_QID\t\t4\n-#define DLB2_ALARM_SYS_AID_ILLEGAL_HCW\t\t5\n-#define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ\t1\n-#define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2\n-\n-/*\n- * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by\n- * the PF driver.\n- */\n-#define DLB2_DRV_LDB_PP_BASE 0x2300000\n-#define DLB2_DRV_LDB_PP_STRIDE 0x1000\n-#define DLB2_DRV_LDB_PP_BOUND (DLB2_DRV_LDB_PP_BASE + \\\n-\t\t\t\tDLB2_DRV_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n-#define DLB2_DRV_DIR_PP_BASE 0x2200000\n-#define DLB2_DRV_DIR_PP_STRIDE 0x1000\n-#define DLB2_DRV_DIR_PP_BOUND (DLB2_DRV_DIR_PP_BASE + \\\n-\t\t\t\tDLB2_DRV_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)\n-#define DLB2_LDB_PP_BASE 0x2100000\n-#define DLB2_LDB_PP_STRIDE 0x1000\n-#define DLB2_LDB_PP_BOUND (DLB2_LDB_PP_BASE + \\\n-\t\t\t\tDLB2_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n-#define DLB2_LDB_PP_OFFS(id) (DLB2_LDB_PP_BASE + (id) * DLB2_PP_SIZE)\n-#define DLB2_DIR_PP_BASE 0x2000000\n-#define DLB2_DIR_PP_STRIDE 0x1000\n-#define DLB2_DIR_PP_BOUND (DLB2_DIR_PP_BASE + \\\n-\t\t\t\tDLB2_DIR_PP_STRIDE * \\\n-\t\t\t\tDLB2_MAX_NUM_DIR_PORTS_V2_5)\n-#define DLB2_DIR_PP_OFFS(id) (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)\n-\n-struct dlb2_resource_id {\n-\tu32 phys_id;\n-\tu32 virt_id;\n-\tu8 vdev_owned;\n-\tu8 vdev_id;\n-};\n-\n-struct dlb2_freelist {\n-\tu32 base;\n-\tu32 bound;\n-\tu32 offset;\n-};\n-\n-static inline u32 dlb2_freelist_count(struct dlb2_freelist *list)\n-{\n-\treturn list->bound - list->base - list->offset;\n-}\n-\n-struct dlb2_hcw {\n-\tu64 data;\n-\t/* Word 3 */\n-\tu16 opaque;\n-\tu8 qid;\n-\tu8 sched_type:2;\n-\tu8 priority:3;\n-\tu8 msg_type:3;\n-\t/* Word 4 */\n-\tu16 lock_id;\n-\tu8 ts_flag:1;\n-\tu8 rsvd1:2;\n-\tu8 no_dec:1;\n-\tu8 cmp_id:4;\n-\tu8 cq_token:1;\n-\tu8 qe_comp:1;\n-\tu8 qe_frag:1;\n-\tu8 qe_valid:1;\n-\tu8 int_arm:1;\n-\tu8 error:1;\n-\tu8 rsvd:2;\n-};\n-\n-struct dlb2_ldb_queue {\n-\tstruct dlb2_list_entry domain_list;\n-\tstruct dlb2_list_entry func_list;\n-\tstruct dlb2_resource_id id;\n-\tstruct dlb2_resource_id domain_id;\n-\tu32 num_qid_inflights;\n-\tu32 aqed_limit;\n-\tu32 sn_group; /* sn == sequence number */\n-\tu32 sn_slot;\n-\tu32 num_mappings;\n-\tu8 sn_cfg_valid;\n-\tu8 num_pending_additions;\n-\tu8 owned;\n-\tu8 configured;\n-};\n-\n-/*\n- * Directed ports and queues are paired by nature, so the driver tracks them\n- * with a single data structure.\n- */\n-struct dlb2_dir_pq_pair {\n-\tstruct dlb2_list_entry domain_list;\n-\tstruct dlb2_list_entry func_list;\n-\tstruct dlb2_resource_id id;\n-\tstruct dlb2_resource_id domain_id;\n-\tu32 ref_cnt;\n-\tu8 init_tkn_cnt;\n-\tu8 queue_configured;\n-\tu8 port_configured;\n-\tu8 owned;\n-\tu8 enabled;\n-};\n-\n-enum dlb2_qid_map_state {\n-\t/* The slot does not contain a valid queue mapping */\n-\tDLB2_QUEUE_UNMAPPED,\n-\t/* The slot contains a valid queue mapping */\n-\tDLB2_QUEUE_MAPPED,\n-\t/* The driver is mapping a queue into this slot */\n-\tDLB2_QUEUE_MAP_IN_PROG,\n-\t/* The driver is unmapping a queue from this slot */\n-\tDLB2_QUEUE_UNMAP_IN_PROG,\n-\t/*\n-\t * The driver is unmapping a queue from this slot, and once complete\n-\t * will replace it with another mapping.\n-\t */\n-\tDLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP,\n-};\n-\n-struct dlb2_ldb_port_qid_map {\n-\tenum dlb2_qid_map_state state;\n-\tu16 qid;\n-\tu16 pending_qid;\n-\tu8 priority;\n-\tu8 pending_priority;\n-};\n-\n-struct dlb2_ldb_port {\n-\tstruct dlb2_list_entry domain_list;\n-\tstruct dlb2_list_entry func_list;\n-\tstruct dlb2_resource_id id;\n-\tstruct dlb2_resource_id domain_id;\n-\t/* The qid_map represents the hardware QID mapping state. */\n-\tstruct dlb2_ldb_port_qid_map qid_map[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];\n-\tu32 hist_list_entry_base;\n-\tu32 hist_list_entry_limit;\n-\tu32 ref_cnt;\n-\tu8 cq_depth;\n-\tu8 init_tkn_cnt;\n-\tu8 num_pending_removals;\n-\tu8 num_mappings;\n-\tu8 owned;\n-\tu8 enabled;\n-\tu8 configured;\n-};\n-\n-struct dlb2_sn_group {\n-\tu32 mode;\n-\tu32 sequence_numbers_per_queue;\n-\tu32 slot_use_bitmap;\n-\tu32 id;\n-};\n-\n-static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)\n-{\n-\tconst u32 mask[] = {\n-\t\t0x0000ffff, /* 64 SNs per queue */\n-\t\t0x000000ff, /* 128 SNs per queue */\n-\t\t0x0000000f, /* 256 SNs per queue */\n-\t\t0x00000003, /* 512 SNs per queue */\n-\t\t0x00000001}; /* 1024 SNs per queue */\n-\n-\treturn group->slot_use_bitmap == mask[group->mode];\n-}\n-\n-static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)\n-{\n-\tconst u32 bound[] = {16, 8, 4, 2, 1};\n-\tu32 i;\n-\n-\tfor (i = 0; i < bound[group->mode]; i++) {\n-\t\tif (!(group->slot_use_bitmap & (1 << i))) {\n-\t\t\tgroup->slot_use_bitmap |= 1 << i;\n-\t\t\treturn i;\n-\t\t}\n-\t}\n-\n-\treturn -1;\n-}\n-\n-static inline void\n-dlb2_sn_group_free_slot(struct dlb2_sn_group *group, int slot)\n-{\n-\tgroup->slot_use_bitmap &= ~(1 << slot);\n-}\n-\n-static inline int dlb2_sn_group_used_slots(struct dlb2_sn_group *group)\n-{\n-\tint i, cnt = 0;\n-\n-\tfor (i = 0; i < 32; i++)\n-\t\tcnt += !!(group->slot_use_bitmap & (1 << i));\n-\n-\treturn cnt;\n-}\n-\n-struct dlb2_hw_domain {\n-\tstruct dlb2_function_resources *parent_func;\n-\tstruct dlb2_list_entry func_list;\n-\tstruct dlb2_list_head used_ldb_queues;\n-\tstruct dlb2_list_head used_ldb_ports[DLB2_NUM_COS_DOMAINS];\n-\tstruct dlb2_list_head used_dir_pq_pairs;\n-\tstruct dlb2_list_head avail_ldb_queues;\n-\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n-\tstruct dlb2_list_head avail_dir_pq_pairs;\n-\tu32 total_hist_list_entries;\n-\tu32 avail_hist_list_entries;\n-\tu32 hist_list_entry_base;\n-\tu32 hist_list_entry_offset;\n-\tunion {\n-\t\tstruct {\n-\t\t\tu32 num_ldb_credits;\n-\t\t\tu32 num_dir_credits;\n-\t\t};\n-\t\tstruct {\n-\t\t\tu32 num_credits;\n-\t\t};\n-\t};\n-\tu32 num_avail_aqed_entries;\n-\tu32 num_used_aqed_entries;\n-\tstruct dlb2_resource_id id;\n-\tint num_pending_removals;\n-\tint num_pending_additions;\n-\tu8 configured;\n-\tu8 started;\n-};\n-\n-struct dlb2_bitmap;\n-\n-struct dlb2_function_resources {\n-\tstruct dlb2_list_head avail_domains;\n-\tstruct dlb2_list_head used_domains;\n-\tstruct dlb2_list_head avail_ldb_queues;\n-\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n-\tstruct dlb2_list_head avail_dir_pq_pairs;\n-\tstruct dlb2_bitmap *avail_hist_list_entries;\n-\tu32 num_avail_domains;\n-\tu32 num_avail_ldb_queues;\n-\tu32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n-\tu32 num_avail_dir_pq_pairs;\n-\tunion {\n-\t\tstruct {\n-\t\t\tu32 num_avail_qed_entries;\n-\t\t\tu32 num_avail_dqed_entries;\n-\t\t};\n-\t\tstruct {\n-\t\t\tu32 num_avail_entries;\n-\t\t};\n-\t};\n-\tu32 num_avail_aqed_entries;\n-\tu8 locked; /* (VDEV only) */\n-};\n-\n-/*\n- * After initialization, each resource in dlb2_hw_resources is located in one\n- * of the following lists:\n- * -- The PF's available resources list. These are unconfigured resources owned\n- *\tby the PF and not allocated to a dlb2 scheduling domain.\n- * -- A VDEV's available resources list. These are VDEV-owned unconfigured\n- *\tresources not allocated to a dlb2 scheduling domain.\n- * -- A domain's available resources list. These are domain-owned unconfigured\n- *\tresources.\n- * -- A domain's used resources list. These are domain-owned configured\n- *\tresources.\n- *\n- * A resource moves to a new list when a VDEV or domain is created or destroyed,\n- * or when the resource is configured.\n- */\n-struct dlb2_hw_resources {\n-\tstruct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];\n-\tstruct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];\n-\tstruct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS_V2_5];\n-\tstruct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];\n-};\n-\n-struct dlb2_mbox {\n-\tu32 *mbox;\n-\tu32 *isr_in_progress;\n-};\n-\n-struct dlb2_sw_mbox {\n-\tstruct dlb2_mbox vdev_to_pf;\n-\tstruct dlb2_mbox pf_to_vdev;\n-\tvoid (*pf_to_vdev_inject)(void *arg);\n-\tvoid *pf_to_vdev_inject_arg;\n-};\n-\n-struct dlb2_hw {\n-\tuint8_t ver;\n-\n-\t/* BAR 0 address */\n-\tvoid *csr_kva;\n-\tunsigned long csr_phys_addr;\n-\t/* BAR 2 address */\n-\tvoid *func_kva;\n-\tunsigned long func_phys_addr;\n-\n-\t/* Resource tracking */\n-\tstruct dlb2_hw_resources rsrcs;\n-\tstruct dlb2_function_resources pf;\n-\tstruct dlb2_function_resources vdev[DLB2_MAX_NUM_VDEVS];\n-\tstruct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS];\n-\tu8 cos_reservation[DLB2_NUM_COS_DOMAINS];\n-\n-\t/* Virtualization */\n-\tint virt_mode;\n-\tstruct dlb2_sw_mbox mbox[DLB2_MAX_NUM_VDEVS];\n-\tunsigned int pasid[DLB2_MAX_NUM_VDEVS];\n-};\n-\n-#endif /* __DLB2_HW_TYPES_NEW_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 2f66b2c71..54b0207db 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -2,11 +2,9 @@\n * Copyright(c) 2016-2020 Intel Corporation\n */\n \n-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n-\n #include \"dlb2_user.h\"\n \n-#include \"dlb2_hw_types_new.h\"\n+#include \"dlb2_hw_types.h\"\n #include \"dlb2_osdep.h\"\n #include \"dlb2_osdep_bitmap.h\"\n #include \"dlb2_osdep_types.h\"\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex bac07f097..1f6ccf8e4 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -13,10 +13,8 @@\n #include <rte_malloc.h>\n #include <rte_errno.h>\n \n-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n-\n #include \"base/dlb2_regs_new.h\"\n-#include \"base/dlb2_hw_types_new.h\"\n+#include \"base/dlb2_hw_types.h\"\n #include \"base/dlb2_resource.h\"\n #include \"base/dlb2_osdep.h\"\n #include \"dlb2_main.h\"\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb2/pf/dlb2_main.h\nindex 892298d7a..9eeda482a 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.h\n+++ b/drivers/event/dlb2/pf/dlb2_main.h\n@@ -12,11 +12,7 @@\n #include <rte_bus_pci.h>\n #include <rte_eal_paging.h>\n \n-#ifdef DLB2_USE_NEW_HEADERS\n-#include \"base/dlb2_hw_types_new.h\"\n-#else\n #include \"base/dlb2_hw_types.h\"\n-#endif\n #include \"../dlb2_user.h\"\n \n #define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 880964a29..f57dc1584 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -32,13 +32,11 @@\n #include <rte_memory.h>\n #include <rte_string_fns.h>\n \n-#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n-\n #include \"../dlb2_priv.h\"\n #include \"../dlb2_iface.h\"\n #include \"../dlb2_inline_fns.h\"\n #include \"dlb2_main.h\"\n-#include \"base/dlb2_hw_types_new.h\"\n+#include \"base/dlb2_hw_types.h\"\n #include \"base/dlb2_osdep.h\"\n #include \"base/dlb2_resource.h\"\n \n", "prefixes": [ "v3", "21/26" ] }