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GET /api/patches/91300/?format=api
{ "id": 91300, "url": "https://patches.dpdk.org/api/patches/91300/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-4-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618344896-2090-4-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618344896-2090-4-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-13T20:14:33", "name": "[v3,03/26] event/dlb2: add v2.5 HW init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "205a85720800f85a8c8cfddf9706949147de6dca", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-4-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16345, "url": "https://patches.dpdk.org/api/series/16345/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16345", "date": "2021-04-13T20:14:31", "name": "Add DLB V2.5", "version": 3, "mbox": "https://patches.dpdk.org/series/16345/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91300/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/91300/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 64B5CA0524;\n\tTue, 13 Apr 2021 22:16:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5A0EA1612D0;\n\tTue, 13 Apr 2021 22:16:17 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 23C2C1612C2\n for <dev@dpdk.org>; Tue, 13 Apr 2021 22:16:12 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 13:16:10 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:10 -0700" ], "IronPort-SDR": [ "\n zhzQ894aGObPERzuaxrg6SxshePPQ3NKuskYpblX0EfEWUJV9MCrp8Fqa/Z59dbSJIoiPvt5RU\n frKvaNBt5a8Q==", "\n tsVFrN7zhJFZecyWie/MbVYK5Zv7H6oxVsDZ2HGMlIg9E8tJpJkWEe6nFJpT+tVbuw6FhyOlZV\n Rqft9M5SWDAA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"194519686\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"194519686\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"424406467\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Tue, 13 Apr 2021 15:14:33 -0500", "Message-Id": "<1618344896-2090-4-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 03/26] event/dlb2: add v2.5 HW init", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds support for DLB v2.5 probe-time hardware init,\nand sets up a framework for incorporating the remaining\nchanges required to support DLB v2.5.\n\nDLB v2.0 and DLB v2.5 are similar in many respects, but their\nregister offsets and definitions are different. As a result of these,\ndifferences, the low level hardware functions must take the device\nversion into consideration. This requires that the hardware version be\npassed to many of the low level functions, so that the PMD can\ntake the appropriate action based on the device version.\n\nTo ease the transition and keep the individual patches small, three\ntemporary files are added in this commit. These files have \"new\"\nin their names. The files with \"new\" contain changes specific to a\nconsolidated PMD that supports both DLB v2.0 and DLB 2.5. Their sister\nfiles of the same name (minus \"new\") contain the old DLB v2.0 specific\ncode. The intent is to remove code from the original files as that code\nis ported to the combined DLB 2.0/2.5 PMD model and added to the \"new\"\nfiles in a series of commits. At end of the patch series, the old files\nwill be empty and the \"new\" files will have the logic needed\nto implement a single PMD that supports both DLB v2.0 and DLB v2.5.\nAt that time, the original DLB v2.0 specific files will be deleted,\nand the \"new\" files will be renamed and replace them.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2_priv.h | 5 +\n drivers/event/dlb2/meson.build | 1 +\n .../event/dlb2/pf/base/dlb2_hw_types_new.h | 356 ++++++++++++++++++\n drivers/event/dlb2/pf/base/dlb2_osdep.h | 4 +\n drivers/event/dlb2/pf/base/dlb2_resource.c | 180 +--------\n drivers/event/dlb2/pf/base/dlb2_resource.h | 36 --\n .../event/dlb2/pf/base/dlb2_resource_new.c | 259 +++++++++++++\n .../event/dlb2/pf/base/dlb2_resource_new.h | 73 ++++\n drivers/event/dlb2/pf/dlb2_main.c | 41 +-\n drivers/event/dlb2/pf/dlb2_main.h | 4 +\n drivers/event/dlb2/pf/dlb2_pf.c | 6 +-\n 11 files changed, 735 insertions(+), 230 deletions(-)\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_hw_types_new.h\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.c\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource_new.h", "diff": "diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 1cd78ad94..f3a9fe0aa 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -114,6 +114,11 @@\n #define EV_TO_DLB2_PRIO(x) ((x) >> 5)\n #define DLB2_TO_EV_PRIO(x) ((x) << 5)\n \n+enum dlb2_hw_ver {\n+\tDLB2_HW_VER_2,\n+\tDLB2_HW_VER_2_5,\n+};\n+\n enum dlb2_hw_port_types {\n \tDLB2_LDB_PORT,\n \tDLB2_DIR_PORT,\ndiff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build\nindex f22638b8e..bded07e06 100644\n--- a/drivers/event/dlb2/meson.build\n+++ b/drivers/event/dlb2/meson.build\n@@ -14,6 +14,7 @@ sources = files('dlb2.c',\n \t\t'pf/dlb2_main.c',\n \t\t'pf/dlb2_pf.c',\n \t\t'pf/base/dlb2_resource.c',\n+\t\t'pf/base/dlb2_resource_new.c',\n \t\t'rte_pmd_dlb2.c',\n \t\t'dlb2_selftest.c'\n )\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h b/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h\nnew file mode 100644\nindex 000000000..4a4185acd\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types_new.h\n@@ -0,0 +1,356 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_HW_TYPES_NEW_H\n+#define __DLB2_HW_TYPES_NEW_H\n+\n+#include \"../../dlb2_priv.h\"\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_osdep_list.h\"\n+#include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs_new.h\"\n+\n+#define DLB2_BITS_SET(x, val, mask)\t(x = ((x) & ~(mask)) \\\n+\t\t\t\t | (((val) << (mask##_LOC)) & (mask)))\n+#define DLB2_BITS_CLR(x, mask)\t(x &= ~(mask))\n+#define DLB2_BIT_SET(x, mask)\t((x) |= (mask))\n+#define DLB2_BITS_GET(x, mask)\t(((x) & (mask)) >> (mask##_LOC))\n+\n+#define DLB2_MAX_NUM_VDEVS\t\t\t16\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n+#define DLB2_NUM_ARB_WEIGHTS\t\t\t8\n+#define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n+#define DLB2_MAX_WEIGHT\t\t\t\t255\n+#define DLB2_NUM_COS_DOMAINS\t\t\t4\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n+#define DLB2_MAX_CQ_COMP_CHECK_LOOPS\t\t409600\n+#define DLB2_MAX_QID_EMPTY_CHECK_LOOPS\t\t(32 * 64 * 1024 * (800 / 30))\n+\n+#define DLB2_FUNC_BAR\t\t\t\t0\n+#define DLB2_CSR_BAR\t\t\t\t2\n+\n+#define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710\n+#define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711\n+\n+#define PCI_DEVICE_ID_INTEL_DLB2_5_PF 0x2714\n+#define PCI_DEVICE_ID_INTEL_DLB2_5_VF 0x2715\n+\n+#define DLB2_ALARM_HW_SOURCE_SYS 0\n+#define DLB2_ALARM_HW_SOURCE_DLB 1\n+\n+#define DLB2_ALARM_HW_UNIT_CHP 4\n+\n+#define DLB2_ALARM_SYS_AID_ILLEGAL_QID\t\t3\n+#define DLB2_ALARM_SYS_AID_DISABLED_QID\t\t4\n+#define DLB2_ALARM_SYS_AID_ILLEGAL_HCW\t\t5\n+#define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ\t1\n+#define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2\n+\n+/*\n+ * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by\n+ * the PF driver.\n+ */\n+#define DLB2_DRV_LDB_PP_BASE 0x2300000\n+#define DLB2_DRV_LDB_PP_STRIDE 0x1000\n+#define DLB2_DRV_LDB_PP_BOUND (DLB2_DRV_LDB_PP_BASE + \\\n+\t\t\t\tDLB2_DRV_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_DRV_DIR_PP_BASE 0x2200000\n+#define DLB2_DRV_DIR_PP_STRIDE 0x1000\n+#define DLB2_DRV_DIR_PP_BOUND (DLB2_DRV_DIR_PP_BASE + \\\n+\t\t\t\tDLB2_DRV_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)\n+#define DLB2_LDB_PP_BASE 0x2100000\n+#define DLB2_LDB_PP_STRIDE 0x1000\n+#define DLB2_LDB_PP_BOUND (DLB2_LDB_PP_BASE + \\\n+\t\t\t\tDLB2_LDB_PP_STRIDE * DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_LDB_PP_OFFS(id) (DLB2_LDB_PP_BASE + (id) * DLB2_PP_SIZE)\n+#define DLB2_DIR_PP_BASE 0x2000000\n+#define DLB2_DIR_PP_STRIDE 0x1000\n+#define DLB2_DIR_PP_BOUND (DLB2_DIR_PP_BASE + \\\n+\t\t\t\tDLB2_DIR_PP_STRIDE * \\\n+\t\t\t\tDLB2_MAX_NUM_DIR_PORTS_V2_5)\n+#define DLB2_DIR_PP_OFFS(id) (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)\n+\n+struct dlb2_resource_id {\n+\tu32 phys_id;\n+\tu32 virt_id;\n+\tu8 vdev_owned;\n+\tu8 vdev_id;\n+};\n+\n+struct dlb2_freelist {\n+\tu32 base;\n+\tu32 bound;\n+\tu32 offset;\n+};\n+\n+static inline u32 dlb2_freelist_count(struct dlb2_freelist *list)\n+{\n+\treturn list->bound - list->base - list->offset;\n+}\n+\n+struct dlb2_hcw {\n+\tu64 data;\n+\t/* Word 3 */\n+\tu16 opaque;\n+\tu8 qid;\n+\tu8 sched_type:2;\n+\tu8 priority:3;\n+\tu8 msg_type:3;\n+\t/* Word 4 */\n+\tu16 lock_id;\n+\tu8 ts_flag:1;\n+\tu8 rsvd1:2;\n+\tu8 no_dec:1;\n+\tu8 cmp_id:4;\n+\tu8 cq_token:1;\n+\tu8 qe_comp:1;\n+\tu8 qe_frag:1;\n+\tu8 qe_valid:1;\n+\tu8 int_arm:1;\n+\tu8 error:1;\n+\tu8 rsvd:2;\n+};\n+\n+struct dlb2_ldb_queue {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\tu32 num_qid_inflights;\n+\tu32 aqed_limit;\n+\tu32 sn_group; /* sn == sequence number */\n+\tu32 sn_slot;\n+\tu32 num_mappings;\n+\tu8 sn_cfg_valid;\n+\tu8 num_pending_additions;\n+\tu8 owned;\n+\tu8 configured;\n+};\n+\n+/*\n+ * Directed ports and queues are paired by nature, so the driver tracks them\n+ * with a single data structure.\n+ */\n+struct dlb2_dir_pq_pair {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\tu32 ref_cnt;\n+\tu8 init_tkn_cnt;\n+\tu8 queue_configured;\n+\tu8 port_configured;\n+\tu8 owned;\n+\tu8 enabled;\n+};\n+\n+enum dlb2_qid_map_state {\n+\t/* The slot does not contain a valid queue mapping */\n+\tDLB2_QUEUE_UNMAPPED,\n+\t/* The slot contains a valid queue mapping */\n+\tDLB2_QUEUE_MAPPED,\n+\t/* The driver is mapping a queue into this slot */\n+\tDLB2_QUEUE_MAP_IN_PROG,\n+\t/* The driver is unmapping a queue from this slot */\n+\tDLB2_QUEUE_UNMAP_IN_PROG,\n+\t/*\n+\t * The driver is unmapping a queue from this slot, and once complete\n+\t * will replace it with another mapping.\n+\t */\n+\tDLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP,\n+};\n+\n+struct dlb2_ldb_port_qid_map {\n+\tenum dlb2_qid_map_state state;\n+\tu16 qid;\n+\tu16 pending_qid;\n+\tu8 priority;\n+\tu8 pending_priority;\n+};\n+\n+struct dlb2_ldb_port {\n+\tstruct dlb2_list_entry domain_list;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_resource_id id;\n+\tstruct dlb2_resource_id domain_id;\n+\t/* The qid_map represents the hardware QID mapping state. */\n+\tstruct dlb2_ldb_port_qid_map qid_map[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_limit;\n+\tu32 ref_cnt;\n+\tu8 init_tkn_cnt;\n+\tu8 num_pending_removals;\n+\tu8 num_mappings;\n+\tu8 owned;\n+\tu8 enabled;\n+\tu8 configured;\n+};\n+\n+struct dlb2_sn_group {\n+\tu32 mode;\n+\tu32 sequence_numbers_per_queue;\n+\tu32 slot_use_bitmap;\n+\tu32 id;\n+};\n+\n+static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)\n+{\n+\tconst u32 mask[] = {\n+\t\t0x0000ffff, /* 64 SNs per queue */\n+\t\t0x000000ff, /* 128 SNs per queue */\n+\t\t0x0000000f, /* 256 SNs per queue */\n+\t\t0x00000003, /* 512 SNs per queue */\n+\t\t0x00000001}; /* 1024 SNs per queue */\n+\n+\treturn group->slot_use_bitmap == mask[group->mode];\n+}\n+\n+static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)\n+{\n+\tconst u32 bound[] = {16, 8, 4, 2, 1};\n+\tu32 i;\n+\n+\tfor (i = 0; i < bound[group->mode]; i++) {\n+\t\tif (!(group->slot_use_bitmap & (1 << i))) {\n+\t\t\tgroup->slot_use_bitmap |= 1 << i;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static inline void\n+dlb2_sn_group_free_slot(struct dlb2_sn_group *group, int slot)\n+{\n+\tgroup->slot_use_bitmap &= ~(1 << slot);\n+}\n+\n+static inline int dlb2_sn_group_used_slots(struct dlb2_sn_group *group)\n+{\n+\tint i, cnt = 0;\n+\n+\tfor (i = 0; i < 32; i++)\n+\t\tcnt += !!(group->slot_use_bitmap & (1 << i));\n+\n+\treturn cnt;\n+}\n+\n+struct dlb2_hw_domain {\n+\tstruct dlb2_function_resources *parent_func;\n+\tstruct dlb2_list_entry func_list;\n+\tstruct dlb2_list_head used_ldb_queues;\n+\tstruct dlb2_list_head used_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head used_dir_pq_pairs;\n+\tstruct dlb2_list_head avail_ldb_queues;\n+\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head avail_dir_pq_pairs;\n+\tu32 total_hist_list_entries;\n+\tu32 avail_hist_list_entries;\n+\tu32 hist_list_entry_base;\n+\tu32 hist_list_entry_offset;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu32 num_ldb_credits;\n+\t\t\tu32 num_dir_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tu32 num_credits;\n+\t\t};\n+\t};\n+\tu32 num_avail_aqed_entries;\n+\tu32 num_used_aqed_entries;\n+\tstruct dlb2_resource_id id;\n+\tint num_pending_removals;\n+\tint num_pending_additions;\n+\tu8 configured;\n+\tu8 started;\n+};\n+\n+struct dlb2_bitmap;\n+\n+struct dlb2_function_resources {\n+\tstruct dlb2_list_head avail_domains;\n+\tstruct dlb2_list_head used_domains;\n+\tstruct dlb2_list_head avail_ldb_queues;\n+\tstruct dlb2_list_head avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tstruct dlb2_list_head avail_dir_pq_pairs;\n+\tstruct dlb2_bitmap *avail_hist_list_entries;\n+\tu32 num_avail_domains;\n+\tu32 num_avail_ldb_queues;\n+\tu32 num_avail_ldb_ports[DLB2_NUM_COS_DOMAINS];\n+\tu32 num_avail_dir_pq_pairs;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu32 num_avail_qed_entries;\n+\t\t\tu32 num_avail_dqed_entries;\n+\t\t};\n+\t\tstruct {\n+\t\t\tu32 num_avail_entries;\n+\t\t};\n+\t};\n+\tu32 num_avail_aqed_entries;\n+\tu8 locked; /* (VDEV only) */\n+};\n+\n+/*\n+ * After initialization, each resource in dlb2_hw_resources is located in one\n+ * of the following lists:\n+ * -- The PF's available resources list. These are unconfigured resources owned\n+ *\tby the PF and not allocated to a dlb2 scheduling domain.\n+ * -- A VDEV's available resources list. These are VDEV-owned unconfigured\n+ *\tresources not allocated to a dlb2 scheduling domain.\n+ * -- A domain's available resources list. These are domain-owned unconfigured\n+ *\tresources.\n+ * -- A domain's used resources list. These are domain-owned configured\n+ *\tresources.\n+ *\n+ * A resource moves to a new list when a VDEV or domain is created or destroyed,\n+ * or when the resource is configured.\n+ */\n+struct dlb2_hw_resources {\n+\tstruct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];\n+\tstruct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];\n+\tstruct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS_V2_5];\n+\tstruct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];\n+};\n+\n+struct dlb2_mbox {\n+\tu32 *mbox;\n+\tu32 *isr_in_progress;\n+};\n+\n+struct dlb2_sw_mbox {\n+\tstruct dlb2_mbox vdev_to_pf;\n+\tstruct dlb2_mbox pf_to_vdev;\n+\tvoid (*pf_to_vdev_inject)(void *arg);\n+\tvoid *pf_to_vdev_inject_arg;\n+};\n+\n+struct dlb2_hw {\n+\tuint8_t ver;\n+\n+\t/* BAR 0 address */\n+\tvoid *csr_kva;\n+\tunsigned long csr_phys_addr;\n+\t/* BAR 2 address */\n+\tvoid *func_kva;\n+\tunsigned long func_phys_addr;\n+\n+\t/* Resource tracking */\n+\tstruct dlb2_hw_resources rsrcs;\n+\tstruct dlb2_function_resources pf;\n+\tstruct dlb2_function_resources vdev[DLB2_MAX_NUM_VDEVS];\n+\tstruct dlb2_hw_domain domains[DLB2_MAX_NUM_DOMAINS];\n+\tu8 cos_reservation[DLB2_NUM_COS_DOMAINS];\n+\n+\t/* Virtualization */\n+\tint virt_mode;\n+\tstruct dlb2_sw_mbox mbox[DLB2_MAX_NUM_VDEVS];\n+\tunsigned int pasid[DLB2_MAX_NUM_VDEVS];\n+};\n+\n+#endif /* __DLB2_HW_TYPES_NEW_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep.h b/drivers/event/dlb2/pf/base/dlb2_osdep.h\nindex aa101a49a..3b0ca84ba 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_osdep.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep.h\n@@ -16,7 +16,11 @@\n #include <rte_log.h>\n #include <rte_spinlock.h>\n #include \"../dlb2_main.h\"\n+\n+/* TEMPORARY inclusion of both headers for merge */\n+#include \"dlb2_resource_new.h\"\n #include \"dlb2_resource.h\"\n+\n #include \"../../dlb2_log.h\"\n #include \"../../dlb2_user.h\"\n \ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 1cb0b9f50..7ba6521ef 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -47,19 +47,6 @@ static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)\n \t\tdlb2_list_init_head(&domain->avail_ldb_ports[i]);\n }\n \n-static void dlb2_init_fn_rsrc_lists(struct dlb2_function_resources *rsrc)\n-{\n-\tint i;\n-\n-\tdlb2_list_init_head(&rsrc->avail_domains);\n-\tdlb2_list_init_head(&rsrc->used_domains);\n-\tdlb2_list_init_head(&rsrc->avail_ldb_queues);\n-\tdlb2_list_init_head(&rsrc->avail_dir_pq_pairs);\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n-\t\tdlb2_list_init_head(&rsrc->avail_ldb_ports[i]);\n-}\n-\n void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n {\n \tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n@@ -130,171 +117,6 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n \tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n }\n \n-void dlb2_resource_free(struct dlb2_hw *hw)\n-{\n-\tint i;\n-\n-\tif (hw->pf.avail_hist_list_entries)\n-\t\tdlb2_bitmap_free(hw->pf.avail_hist_list_entries);\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n-\t\tif (hw->vdev[i].avail_hist_list_entries)\n-\t\t\tdlb2_bitmap_free(hw->vdev[i].avail_hist_list_entries);\n-\t}\n-}\n-\n-int dlb2_resource_init(struct dlb2_hw *hw)\n-{\n-\tstruct dlb2_list_entry *list;\n-\tunsigned int i;\n-\tint ret;\n-\n-\t/*\n-\t * For optimal load-balancing, ports that map to one or more QIDs in\n-\t * common should not be in numerical sequence. This is application\n-\t * dependent, but the driver interleaves port IDs as much as possible\n-\t * to reduce the likelihood of this. This initial allocation maximizes\n-\t * the average distance between an ID and its immediate neighbors (i.e.\n-\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n-\t * 3, etc.).\n-\t */\n-\tu8 init_ldb_port_allocation[DLB2_MAX_NUM_LDB_PORTS] = {\n-\t\t0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9,\n-\t\t16, 23, 30, 21, 28, 19, 26, 17, 24, 31, 22, 29, 20, 27, 18, 25,\n-\t\t32, 39, 46, 37, 44, 35, 42, 33, 40, 47, 38, 45, 36, 43, 34, 41,\n-\t\t48, 55, 62, 53, 60, 51, 58, 49, 56, 63, 54, 61, 52, 59, 50, 57,\n-\t};\n-\n-\t/* Zero-out resource tracking data structures */\n-\tmemset(&hw->rsrcs, 0, sizeof(hw->rsrcs));\n-\tmemset(&hw->pf, 0, sizeof(hw->pf));\n-\n-\tdlb2_init_fn_rsrc_lists(&hw->pf);\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n-\t\tmemset(&hw->vdev[i], 0, sizeof(hw->vdev[i]));\n-\t\tdlb2_init_fn_rsrc_lists(&hw->vdev[i]);\n-\t}\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n-\t\tmemset(&hw->domains[i], 0, sizeof(hw->domains[i]));\n-\t\tdlb2_init_domain_rsrc_lists(&hw->domains[i]);\n-\t\thw->domains[i].parent_func = &hw->pf;\n-\t}\n-\n-\t/* Give all resources to the PF driver */\n-\thw->pf.num_avail_domains = DLB2_MAX_NUM_DOMAINS;\n-\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n-\t\tlist = &hw->domains[i].func_list;\n-\n-\t\tdlb2_list_add(&hw->pf.avail_domains, list);\n-\t}\n-\n-\thw->pf.num_avail_ldb_queues = DLB2_MAX_NUM_LDB_QUEUES;\n-\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n-\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n-\n-\t\tdlb2_list_add(&hw->pf.avail_ldb_queues, list);\n-\t}\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n-\t\thw->pf.num_avail_ldb_ports[i] =\n-\t\t\tDLB2_MAX_NUM_LDB_PORTS / DLB2_NUM_COS_DOMAINS;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n-\t\tint cos_id = i >> DLB2_NUM_COS_DOMAINS;\n-\t\tstruct dlb2_ldb_port *port;\n-\n-\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n-\n-\t\tdlb2_list_add(&hw->pf.avail_ldb_ports[cos_id],\n-\t\t\t &port->func_list);\n-\t}\n-\n-\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS(hw->ver);\n-\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n-\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n-\n-\t\tdlb2_list_add(&hw->pf.avail_dir_pq_pairs, list);\n-\t}\n-\n-\thw->pf.num_avail_qed_entries = DLB2_MAX_NUM_LDB_CREDITS;\n-\thw->pf.num_avail_dqed_entries =\n-\t\tDLB2_MAX_NUM_DIR_CREDITS(hw->ver);\n-\n-\thw->pf.num_avail_aqed_entries = DLB2_MAX_NUM_AQED_ENTRIES;\n-\n-\tret = dlb2_bitmap_alloc(&hw->pf.avail_hist_list_entries,\n-\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n-\tif (ret)\n-\t\tgoto unwind;\n-\n-\tret = dlb2_bitmap_fill(hw->pf.avail_hist_list_entries);\n-\tif (ret)\n-\t\tgoto unwind;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n-\t\tret = dlb2_bitmap_alloc(&hw->vdev[i].avail_hist_list_entries,\n-\t\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n-\t\tif (ret)\n-\t\t\tgoto unwind;\n-\n-\t\tret = dlb2_bitmap_zero(hw->vdev[i].avail_hist_list_entries);\n-\t\tif (ret)\n-\t\t\tgoto unwind;\n-\t}\n-\n-\t/* Initialize the hardware resource IDs */\n-\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n-\t\thw->domains[i].id.phys_id = i;\n-\t\thw->domains[i].id.vdev_owned = false;\n-\t}\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_LDB_QUEUES; i++) {\n-\t\thw->rsrcs.ldb_queues[i].id.phys_id = i;\n-\t\thw->rsrcs.ldb_queues[i].id.vdev_owned = false;\n-\t}\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n-\t\thw->rsrcs.ldb_ports[i].id.phys_id = i;\n-\t\thw->rsrcs.ldb_ports[i].id.vdev_owned = false;\n-\t}\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS(hw->ver); i++) {\n-\t\thw->rsrcs.dir_pq_pairs[i].id.phys_id = i;\n-\t\thw->rsrcs.dir_pq_pairs[i].id.vdev_owned = false;\n-\t}\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n-\t\thw->rsrcs.sn_groups[i].id = i;\n-\t\t/* Default mode (0) is 64 sequence numbers per queue */\n-\t\thw->rsrcs.sn_groups[i].mode = 0;\n-\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 64;\n-\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n-\t}\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n-\t\thw->cos_reservation[i] = 100 / DLB2_NUM_COS_DOMAINS;\n-\n-\treturn 0;\n-\n-unwind:\n-\tdlb2_resource_free(hw);\n-\n-\treturn ret;\n-}\n-\n-void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw)\n-{\n-\tunion dlb2_cfg_mstr_cfg_pm_pmcsr_disable r0;\n-\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE);\n-\n-\tr0.field.disable = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE, r0.val);\n-}\n-\n static void dlb2_configure_domain_credits(struct dlb2_hw *hw,\n \t\t\t\t\t struct dlb2_hw_domain *domain)\n {\n@@ -5876,7 +5698,7 @@ static void dlb2_log_start_domain(struct dlb2_hw *hw,\n int\n dlb2_hw_start_domain(struct dlb2_hw *hw,\n \t\t u32 domain_id,\n-\t\t __attribute((unused)) struct dlb2_start_domain_args *arg,\n+\t\t struct dlb2_start_domain_args *arg,\n \t\t struct dlb2_cmd_response *resp,\n \t\t bool vdev_req,\n \t\t unsigned int vdev_id)\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb2/pf/base/dlb2_resource.h\nindex 503fdf317..2e13193bb 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.h\n@@ -6,35 +6,8 @@\n #define __DLB2_RESOURCE_H\n \n #include \"dlb2_user.h\"\n-\n-#include \"dlb2_hw_types.h\"\n #include \"dlb2_osdep_types.h\"\n \n-/**\n- * dlb2_resource_init() - initialize the device\n- * @hw: pointer to struct dlb2_hw.\n- *\n- * This function initializes the device's software state (pointed to by the hw\n- * argument) and programs global scheduling QoS registers. This function should\n- * be called during driver initialization.\n- *\n- * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the\n- * device is reset.\n- *\n- * Return:\n- * Returns 0 upon success, <0 otherwise.\n- */\n-int dlb2_resource_init(struct dlb2_hw *hw);\n-\n-/**\n- * dlb2_resource_free() - free device state memory\n- * @hw: dlb2_hw handle for a particular device.\n- *\n- * This function frees software state pointed to by dlb2_hw. This function\n- * should be called when resetting the device or unloading the driver.\n- */\n-void dlb2_resource_free(struct dlb2_hw *hw);\n-\n /**\n * dlb2_resource_reset() - reset in-use resources to their initial state\n * @hw: dlb2_hw handle for a particular device.\n@@ -1485,15 +1458,6 @@ int dlb2_notify_vf(struct dlb2_hw *hw,\n */\n int dlb2_vdev_in_use(struct dlb2_hw *hw, unsigned int id);\n \n-/**\n- * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic\n- * @hw: dlb2_hw handle for a particular device.\n- *\n- * Clearing the PMCSR must be done at initialization to make the device fully\n- * operational.\n- */\n-void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw);\n-\n /**\n * dlb2_hw_get_ldb_queue_depth() - returns the depth of a load-balanced queue\n * @hw: dlb2_hw handle for a particular device.\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nnew file mode 100644\nindex 000000000..175b0799e\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -0,0 +1,259 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n+\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_hw_types_new.h\"\n+#include \"dlb2_osdep.h\"\n+#include \"dlb2_osdep_bitmap.h\"\n+#include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs_new.h\"\n+#include \"dlb2_resource_new.h\" /* TEMP FOR UPSTREAMPATCHES */\n+\n+#include \"../../dlb2_priv.h\"\n+#include \"../../dlb2_inline_fns.h\"\n+\n+#define DLB2_DOM_LIST_HEAD(head, type) \\\n+\tDLB2_LIST_HEAD((head), type, domain_list)\n+\n+#define DLB2_FUNC_LIST_HEAD(head, type) \\\n+\tDLB2_LIST_HEAD((head), type, func_list)\n+\n+#define DLB2_DOM_LIST_FOR(head, ptr, iter) \\\n+\tDLB2_LIST_FOR_EACH(head, ptr, domain_list, iter)\n+\n+#define DLB2_FUNC_LIST_FOR(head, ptr, iter) \\\n+\tDLB2_LIST_FOR_EACH(head, ptr, func_list, iter)\n+\n+#define DLB2_DOM_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n+\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, domain_list, it, it_tmp)\n+\n+#define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n+\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n+\n+static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)\n+{\n+\tint i;\n+\n+\tdlb2_list_init_head(&domain->used_ldb_queues);\n+\tdlb2_list_init_head(&domain->used_dir_pq_pairs);\n+\tdlb2_list_init_head(&domain->avail_ldb_queues);\n+\tdlb2_list_init_head(&domain->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->used_ldb_ports[i]);\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->avail_ldb_ports[i]);\n+}\n+\n+static void dlb2_init_fn_rsrc_lists(struct dlb2_function_resources *rsrc)\n+{\n+\tint i;\n+\tdlb2_list_init_head(&rsrc->avail_domains);\n+\tdlb2_list_init_head(&rsrc->used_domains);\n+\tdlb2_list_init_head(&rsrc->avail_ldb_queues);\n+\tdlb2_list_init_head(&rsrc->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&rsrc->avail_ldb_ports[i]);\n+}\n+\n+/**\n+ * dlb2_resource_free() - free device state memory\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function frees software state pointed to by dlb2_hw. This function\n+ * should be called when resetting the device or unloading the driver.\n+ */\n+void dlb2_resource_free(struct dlb2_hw *hw)\n+{\n+\tint i;\n+\n+\tif (hw->pf.avail_hist_list_entries)\n+\t\tdlb2_bitmap_free(hw->pf.avail_hist_list_entries);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tif (hw->vdev[i].avail_hist_list_entries)\n+\t\t\tdlb2_bitmap_free(hw->vdev[i].avail_hist_list_entries);\n+\t}\n+}\n+\n+/**\n+ * dlb2_resource_init() - initialize the device\n+ * @hw: pointer to struct dlb2_hw.\n+ * @ver: device version.\n+ *\n+ * This function initializes the device's software state (pointed to by the hw\n+ * argument) and programs global scheduling QoS registers. This function should\n+ * be called during driver initialization, and the dlb2_hw structure should\n+ * be zero-initialized before calling the function.\n+ *\n+ * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the\n+ * device is reset.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ */\n+int dlb2_resource_init(struct dlb2_hw *hw, enum dlb2_hw_ver ver)\n+{\n+\tstruct dlb2_list_entry *list;\n+\tunsigned int i;\n+\tint ret;\n+\n+\t/*\n+\t * For optimal load-balancing, ports that map to one or more QIDs in\n+\t * common should not be in numerical sequence. The port->QID mapping is\n+\t * application dependent, but the driver interleaves port IDs as much\n+\t * as possible to reduce the likelihood of sequential ports mapping to\n+\t * the same QID(s). This initial allocation of port IDs maximizes the\n+\t * average distance between an ID and its immediate neighbors (i.e.\n+\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n+\t * 3, etc.).\n+\t */\n+\tconst u8 init_ldb_port_allocation[DLB2_MAX_NUM_LDB_PORTS] = {\n+\t\t0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9,\n+\t\t16, 23, 30, 21, 28, 19, 26, 17, 24, 31, 22, 29, 20, 27, 18, 25,\n+\t\t32, 39, 46, 37, 44, 35, 42, 33, 40, 47, 38, 45, 36, 43, 34, 41,\n+\t\t48, 55, 62, 53, 60, 51, 58, 49, 56, 63, 54, 61, 52, 59, 50, 57,\n+\t};\n+\n+\thw->ver = ver;\n+\n+\tdlb2_init_fn_rsrc_lists(&hw->pf);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++)\n+\t\tdlb2_init_fn_rsrc_lists(&hw->vdev[i]);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tdlb2_init_domain_rsrc_lists(&hw->domains[i]);\n+\t\thw->domains[i].parent_func = &hw->pf;\n+\t}\n+\n+\t/* Give all resources to the PF driver */\n+\thw->pf.num_avail_domains = DLB2_MAX_NUM_DOMAINS;\n+\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n+\t\tlist = &hw->domains[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_domains, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_queues = DLB2_MAX_NUM_LDB_QUEUES;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n+\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_queues, list);\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->pf.num_avail_ldb_ports[i] =\n+\t\t\tDLB2_MAX_NUM_LDB_PORTS / DLB2_NUM_COS_DOMAINS;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\tint cos_id = i >> DLB2_NUM_COS_DOMAINS;\n+\t\tstruct dlb2_ldb_port *port;\n+\n+\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_ports[cos_id],\n+\t\t\t &port->func_list);\n+\t}\n+\n+\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS(hw->ver);\n+\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n+\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_dir_pq_pairs, list);\n+\t}\n+\n+\tif (hw->ver == DLB2_HW_V2) {\n+\t\thw->pf.num_avail_qed_entries = DLB2_MAX_NUM_LDB_CREDITS;\n+\t\thw->pf.num_avail_dqed_entries =\n+\t\t\tDLB2_MAX_NUM_DIR_CREDITS(hw->ver);\n+\t} else {\n+\t\thw->pf.num_avail_entries = DLB2_MAX_NUM_CREDITS(hw->ver);\n+\t}\n+\n+\thw->pf.num_avail_aqed_entries = DLB2_MAX_NUM_AQED_ENTRIES;\n+\n+\tret = dlb2_bitmap_alloc(&hw->pf.avail_hist_list_entries,\n+\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tret = dlb2_bitmap_fill(hw->pf.avail_hist_list_entries);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tret = dlb2_bitmap_alloc(&hw->vdev[i].avail_hist_list_entries,\n+\t\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\n+\t\tret = dlb2_bitmap_zero(hw->vdev[i].avail_hist_list_entries);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\t}\n+\n+\t/* Initialize the hardware resource IDs */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\thw->domains[i].id.phys_id = i;\n+\t\thw->domains[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_QUEUES; i++) {\n+\t\thw->rsrcs.ldb_queues[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_queues[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\thw->rsrcs.ldb_ports[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_ports[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS(hw->ver); i++) {\n+\t\thw->rsrcs.dir_pq_pairs[i].id.phys_id = i;\n+\t\thw->rsrcs.dir_pq_pairs[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\thw->rsrcs.sn_groups[i].id = i;\n+\t\t/* Default mode (0) is 64 sequence numbers per queue */\n+\t\thw->rsrcs.sn_groups[i].mode = 0;\n+\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 64;\n+\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->cos_reservation[i] = 100 / DLB2_NUM_COS_DOMAINS;\n+\n+\treturn 0;\n+\n+unwind:\n+\tdlb2_resource_free(hw);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @ver: device version.\n+ *\n+ * Clearing the PMCSR must be done at initialization to make the device fully\n+ * operational.\n+ */\n+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver)\n+{\n+\tu32 pmcsr_dis;\n+\n+\tpmcsr_dis = DLB2_CSR_RD(hw, DLB2_CM_CFG_PM_PMCSR_DISABLE(ver));\n+\n+\tDLB2_BITS_CLR(pmcsr_dis, DLB2_CM_CFG_PM_PMCSR_DISABLE_DISABLE);\n+\n+\tDLB2_CSR_WR(hw, DLB2_CM_CFG_PM_PMCSR_DISABLE(ver), pmcsr_dis);\n+}\n+\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.h b/drivers/event/dlb2/pf/base/dlb2_resource_new.h\nnew file mode 100644\nindex 000000000..51f31543c\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.h\n@@ -0,0 +1,73 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef __DLB2_RESOURCE_NEW_H\n+#define __DLB2_RESOURCE_NEW_H\n+\n+#include \"dlb2_user.h\"\n+#include \"dlb2_osdep_types.h\"\n+\n+/**\n+ * dlb2_resource_init() - initialize the device\n+ * @hw: pointer to struct dlb2_hw.\n+ * @ver: device version.\n+ *\n+ * This function initializes the device's software state (pointed to by the hw\n+ * argument) and programs global scheduling QoS registers. This function should\n+ * be called during driver initialization.\n+ *\n+ * The dlb2_hw struct must be unique per DLB 2.0 device and persist until the\n+ * device is reset.\n+ *\n+ * Return:\n+ * Returns 0 upon success, <0 otherwise.\n+ */\n+int dlb2_resource_init(struct dlb2_hw *hw, enum dlb2_hw_ver ver);\n+\n+/**\n+ * dlb2_clr_pmcsr_disable() - power on bulk of DLB 2.0 logic\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @ver: device version.\n+ *\n+ * Clearing the PMCSR must be done at initialization to make the device fully\n+ * operational.\n+ */\n+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver);\n+\n+/**\n+ * dlb2_finish_unmap_qid_procedures() - finish any pending unmap procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding unmap procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_finish_map_qid_procedures() - finish any pending map procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding map procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw);\n+\n+/**\n+ * dlb2_resource_free() - free device state memory\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function frees software state pointed to by dlb2_hw. This function\n+ * should be called when resetting the device or unloading the driver.\n+ */\n+void dlb2_resource_free(struct dlb2_hw *hw);\n+\n+#endif /* __DLB2_RESOURCE_NEW_H */\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex a9d407f2f..5c0640b3c 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -13,9 +13,12 @@\n #include <rte_malloc.h>\n #include <rte_errno.h>\n \n-#include \"base/dlb2_resource.h\"\n+#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n+\n+#include \"base/dlb2_regs_new.h\"\n+#include \"base/dlb2_hw_types_new.h\"\n+#include \"base/dlb2_resource_new.h\"\n #include \"base/dlb2_osdep.h\"\n-#include \"base/dlb2_regs.h\"\n #include \"dlb2_main.h\"\n #include \"../dlb2_user.h\"\n #include \"../dlb2_priv.h\"\n@@ -103,25 +106,34 @@ dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)\n \n static void dlb2_pf_enable_pm(struct dlb2_dev *dlb2_dev)\n {\n-\tdlb2_clr_pmcsr_disable(&dlb2_dev->hw);\n+\tint version;\n+\tversion = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev);\n+\n+\tdlb2_clr_pmcsr_disable(&dlb2_dev->hw, version);\n }\n \n #define DLB2_READY_RETRY_LIMIT 1000\n-static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev)\n+static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev,\n+\t\t\t\t\t int dlb_version)\n {\n \tu32 retries = 0;\n \n \t/* Allow at least 1s for the device to become active after power-on */\n \tfor (retries = 0; retries < DLB2_READY_RETRY_LIMIT; retries++) {\n-\t\tunion dlb2_cfg_mstr_cfg_diagnostic_idle_status idle;\n-\t\tunion dlb2_cfg_mstr_cfg_pm_status pm_st;\n+\t\tu32 idle_val;\n+\t\tu32 idle_dlb_func_idle;\n+\t\tu32 pm_st_val;\n+\t\tu32 pm_st_pmsm;\n \t\tu32 addr;\n \n-\t\taddr = DLB2_CFG_MSTR_CFG_PM_STATUS;\n-\t\tpm_st.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n-\t\taddr = DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS;\n-\t\tidle.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n-\t\tif (pm_st.field.pmsm == 1 && idle.field.dlb_func_idle == 1)\n+\t\taddr = DLB2_CM_CFG_PM_STATUS(dlb_version);\n+\t\tpm_st_val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n+\t\taddr = DLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS(dlb_version);\n+\t\tidle_val = DLB2_CSR_RD(&dlb2_dev->hw, addr);\n+\t\tidle_dlb_func_idle = idle_val &\n+\t\t\tDLB2_CM_CFG_DIAGNOSTIC_IDLE_STATUS_DLB_FUNC_IDLE;\n+\t\tpm_st_pmsm = pm_st_val & DLB2_CM_CFG_PM_STATUS_PMSM;\n+\t\tif (pm_st_pmsm && idle_dlb_func_idle)\n \t\t\tbreak;\n \n \t\trte_delay_ms(1);\n@@ -141,6 +153,7 @@ dlb2_probe(struct rte_pci_device *pdev)\n {\n \tstruct dlb2_dev *dlb2_dev;\n \tint ret = 0;\n+\tint dlb_version = 0;\n \n \tDLB2_INFO(dlb2_dev, \"probe\\n\");\n \n@@ -152,6 +165,8 @@ dlb2_probe(struct rte_pci_device *pdev)\n \t\tgoto dlb2_dev_malloc_fail;\n \t}\n \n+\tdlb_version = DLB2_HW_DEVICE_FROM_PCI_ID(pdev);\n+\n \t/* PCI Bus driver has already mapped bar space into process.\n \t * Save off our IO register and FUNC addresses.\n \t */\n@@ -191,7 +206,7 @@ dlb2_probe(struct rte_pci_device *pdev)\n \t */\n \tdlb2_pf_enable_pm(dlb2_dev);\n \n-\tret = dlb2_pf_wait_for_device_ready(dlb2_dev);\n+\tret = dlb2_pf_wait_for_device_ready(dlb2_dev, dlb_version);\n \tif (ret)\n \t\tgoto wait_for_device_ready_fail;\n \n@@ -203,7 +218,7 @@ dlb2_probe(struct rte_pci_device *pdev)\n \tif (ret)\n \t\tgoto init_driver_state_fail;\n \n-\tret = dlb2_resource_init(&dlb2_dev->hw);\n+\tret = dlb2_resource_init(&dlb2_dev->hw, dlb_version);\n \tif (ret)\n \t\tgoto resource_init_fail;\n \ndiff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb2/pf/dlb2_main.h\nindex 9eeda482a..892298d7a 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.h\n+++ b/drivers/event/dlb2/pf/dlb2_main.h\n@@ -12,7 +12,11 @@\n #include <rte_bus_pci.h>\n #include <rte_eal_paging.h>\n \n+#ifdef DLB2_USE_NEW_HEADERS\n+#include \"base/dlb2_hw_types_new.h\"\n+#else\n #include \"base/dlb2_hw_types.h\"\n+#endif\n #include \"../dlb2_user.h\"\n \n #define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex f57dc1584..1e815f20d 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -32,13 +32,15 @@\n #include <rte_memory.h>\n #include <rte_string_fns.h>\n \n+#define DLB2_USE_NEW_HEADERS /* TEMPORARY FOR MERGE */\n+\n #include \"../dlb2_priv.h\"\n #include \"../dlb2_iface.h\"\n #include \"../dlb2_inline_fns.h\"\n #include \"dlb2_main.h\"\n-#include \"base/dlb2_hw_types.h\"\n+#include \"base/dlb2_hw_types_new.h\"\n #include \"base/dlb2_osdep.h\"\n-#include \"base/dlb2_resource.h\"\n+#include \"base/dlb2_resource_new.h\"\n \n static const char *event_dlb2_pf_name = RTE_STR(EVDEV_DLB2_NAME_PMD);\n \n", "prefixes": [ "v3", "03/26" ] }