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GET /api/patches/91299/?format=api
{ "id": 91299, "url": "https://patches.dpdk.org/api/patches/91299/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-2-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618344896-2090-2-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618344896-2090-2-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-13T20:14:31", "name": "[v3,01/26] event/dlb2: add v2.5 probe", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7414ed3bd6280ef8fe366253fb98630aa532306e", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-2-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16345, "url": "https://patches.dpdk.org/api/series/16345/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16345", "date": "2021-04-13T20:14:31", "name": "Add DLB V2.5", "version": 3, "mbox": "https://patches.dpdk.org/series/16345/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91299/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91299/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 64B80A0524;\n\tTue, 13 Apr 2021 22:16:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E6EFD1612C4;\n\tTue, 13 Apr 2021 22:16:14 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 0A5651612B3\n for <dev@dpdk.org>; Tue, 13 Apr 2021 22:16:11 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 13:16:09 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:08 -0700" ], "IronPort-SDR": [ "\n HGeeLWMOZByZXHbWBHoGD6fC7ZZTRvrUvyI0GX4fW3coJjJY+TS0haUql5Vf/TaJiBZHBOgY3B\n W4PaXkSK7U/w==", "\n Kcbl+IJP5Cov1d7gB/QY3NzI85XnIHkkcePbIFGSsATpTwqUHSONScMEEPV9E2gMPmnh4oNJ+Z\n 4egpgS4ceGIw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"194519677\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"194519677\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"424406452\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Tue, 13 Apr 2021 15:14:31 -0500", "Message-Id": "<1618344896-2090-2-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 01/26] event/dlb2: add v2.5 probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds dlb v2.5 probe support, and updates\nparameter parsing.\n\nThe dlb v2.5 device differs from dlb v2, in that the\nnumber of resources (ports, queues, ...) is different,\nso macros have been added to take the device version\ninto account.\n\nThis commit also cleans up a few issues in the original\ndlb2 source:\n- eliminate duplicate constant definitions\n- removed unused constant definitions\n- remove #ifdef FPGA\n- remove unused include file, dlb2_mbox.h\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 99 +++-\n drivers/event/dlb2/dlb2_priv.h | 151 ++++--\n drivers/event/dlb2/dlb2_xstats.c | 37 +-\n drivers/event/dlb2/pf/base/dlb2_hw_types.h | 68 +--\n drivers/event/dlb2/pf/base/dlb2_mbox.h | 596 ---------------------\n drivers/event/dlb2/pf/base/dlb2_resource.c | 48 +-\n drivers/event/dlb2/pf/dlb2_pf.c | 62 ++-\n 7 files changed, 318 insertions(+), 743 deletions(-)\n delete mode 100644 drivers/event/dlb2/pf/base/dlb2_mbox.h", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex fb5ff012a..7f5b9141b 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -59,7 +59,8 @@ static struct rte_event_dev_info evdev_dlb2_default_info = {\n \t.max_event_port_enqueue_depth = DLB2_MAX_ENQUEUE_DEPTH,\n \t.max_event_port_links = DLB2_MAX_NUM_QIDS_PER_LDB_CQ,\n \t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n-\t.max_single_link_event_port_queue_pairs = DLB2_MAX_NUM_DIR_PORTS,\n+\t.max_single_link_event_port_queue_pairs =\n+\t\tDLB2_MAX_NUM_DIR_PORTS(DLB2_HW_V2),\n \t.event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |\n \t\t\t RTE_EVENT_DEV_CAP_EVENT_QOS |\n \t\t\t RTE_EVENT_DEV_CAP_BURST_MODE |\n@@ -69,7 +70,7 @@ static struct rte_event_dev_info evdev_dlb2_default_info = {\n };\n \n struct process_local_port_data\n-dlb2_port[DLB2_MAX_NUM_PORTS][DLB2_NUM_PORT_TYPES];\n+dlb2_port[DLB2_MAX_NUM_PORTS_ALL][DLB2_NUM_PORT_TYPES];\n \n static void\n dlb2_free_qe_mem(struct dlb2_port *qm_port)\n@@ -97,7 +98,7 @@ dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,\n {\n \tint q;\n \n-\tfor (q = 0; q < DLB2_MAX_NUM_QUEUES; q++) {\n+\tfor (q = 0; q < DLB2_MAX_NUM_QUEUES(dlb2->version); q++) {\n \t\tif (qid_depth_thresholds[q] != 0)\n \t\t\tdlb2->ev_queues[q].depth_threshold =\n \t\t\t\tqid_depth_thresholds[q];\n@@ -247,9 +248,9 @@ set_num_dir_credits(const char *key __rte_unused,\n \t\treturn ret;\n \n \tif (*num_dir_credits < 0 ||\n-\t *num_dir_credits > DLB2_MAX_NUM_DIR_CREDITS) {\n+\t *num_dir_credits > DLB2_MAX_NUM_DIR_CREDITS(DLB2_HW_V2)) {\n \t\tDLB2_LOG_ERR(\"dlb2: num_dir_credits must be between 0 and %d\\n\",\n-\t\t\t DLB2_MAX_NUM_DIR_CREDITS);\n+\t\t\t DLB2_MAX_NUM_DIR_CREDITS(DLB2_HW_V2));\n \t\treturn -EINVAL;\n \t}\n \n@@ -306,7 +307,6 @@ set_cos(const char *key __rte_unused,\n \treturn 0;\n }\n \n-\n static int\n set_qid_depth_thresh(const char *key __rte_unused,\n \t\t const char *value,\n@@ -327,7 +327,7 @@ set_qid_depth_thresh(const char *key __rte_unused,\n \t */\n \tif (sscanf(value, \"all:%d\", &thresh) == 1) {\n \t\tfirst = 0;\n-\t\tlast = DLB2_MAX_NUM_QUEUES - 1;\n+\t\tlast = DLB2_MAX_NUM_QUEUES(DLB2_HW_V2) - 1;\n \t} else if (sscanf(value, \"%d-%d:%d\", &first, &last, &thresh) == 3) {\n \t\t/* we have everything we need */\n \t} else if (sscanf(value, \"%d:%d\", &first, &thresh) == 2) {\n@@ -337,7 +337,56 @@ set_qid_depth_thresh(const char *key __rte_unused,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (first > last || first < 0 || last >= DLB2_MAX_NUM_QUEUES) {\n+\tif (first > last || first < 0 ||\n+\t\tlast >= DLB2_MAX_NUM_QUEUES(DLB2_HW_V2)) {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth devarg, invalid qid value\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (thresh < 0 || thresh > DLB2_MAX_QUEUE_DEPTH_THRESHOLD) {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth devarg, threshold > %d\\n\",\n+\t\t\t DLB2_MAX_QUEUE_DEPTH_THRESHOLD);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = first; i <= last; i++)\n+\t\tqid_thresh->val[i] = thresh; /* indexed by qid */\n+\n+\treturn 0;\n+}\n+\n+static int\n+set_qid_depth_thresh_v2_5(const char *key __rte_unused,\n+\t\t\t const char *value,\n+\t\t\t void *opaque)\n+{\n+\tstruct dlb2_qid_depth_thresholds *qid_thresh = opaque;\n+\tint first, last, thresh, i;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* command line override may take one of the following 3 forms:\n+\t * qid_depth_thresh=all:<threshold_value> ... all queues\n+\t * qid_depth_thresh=qidA-qidB:<threshold_value> ... a range of queues\n+\t * qid_depth_thresh=qid:<threshold_value> ... just one queue\n+\t */\n+\tif (sscanf(value, \"all:%d\", &thresh) == 1) {\n+\t\tfirst = 0;\n+\t\tlast = DLB2_MAX_NUM_QUEUES(DLB2_HW_V2_5) - 1;\n+\t} else if (sscanf(value, \"%d-%d:%d\", &first, &last, &thresh) == 3) {\n+\t\t/* we have everything we need */\n+\t} else if (sscanf(value, \"%d:%d\", &first, &thresh) == 2) {\n+\t\tlast = first;\n+\t} else {\n+\t\tDLB2_LOG_ERR(\"Error parsing qid depth devarg. Should be all:val, qid-qid:val, or qid:val\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (first > last || first < 0 ||\n+\t\tlast >= DLB2_MAX_NUM_QUEUES(DLB2_HW_V2_5)) {\n \t\tDLB2_LOG_ERR(\"Error parsing qid depth devarg, invalid qid value\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -521,7 +570,7 @@ dlb2_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig)\n \tfor (i = 0; i < dlb2->num_queues; i++)\n \t\tdlb2->ev_queues[i].qm_queue.config_state = config_state;\n \n-\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES; i++)\n+\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES(DLB2_HW_V2_5); i++)\n \t\tdlb2->ev_queues[i].setup_done = false;\n \n \tdlb2->num_ports = 0;\n@@ -1453,7 +1502,7 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev,\n \n \tdlb2 = dlb2_pmd_priv(dev);\n \n-\tif (ev_port_id >= DLB2_MAX_NUM_PORTS)\n+\tif (ev_port_id >= DLB2_MAX_NUM_PORTS(dlb2->version))\n \t\treturn -EINVAL;\n \n \tif (port_conf->dequeue_depth >\n@@ -3895,7 +3944,7 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \t}\n \n \t/* Initialize each port's token pop mode */\n-\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++)\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version); i++)\n \t\tdlb2->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;\n \n \trte_spinlock_init(&dlb2->qm_instance.resource_lock);\n@@ -3945,7 +3994,8 @@ dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,\n int\n dlb2_parse_params(const char *params,\n \t\t const char *name,\n-\t\t struct dlb2_devargs *dlb2_args)\n+\t\t struct dlb2_devargs *dlb2_args,\n+\t\t uint8_t version)\n {\n \tint ret = 0;\n \tstatic const char * const args[] = { NUMA_NODE_ARG,\n@@ -3984,17 +4034,18 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n-\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\tif (version == DLB2_HW_V2) {\n+\t\t\t\tret = rte_kvargs_process(kvlist,\n \t\t\t\t\tDLB2_NUM_DIR_CREDITS,\n \t\t\t\t\tset_num_dir_credits,\n \t\t\t\t\t&dlb2_args->num_dir_credits_override);\n-\t\t\tif (ret != 0) {\n-\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing num_dir_credits parameter\",\n-\t\t\t\t\t name);\n-\t\t\t\trte_kvargs_free(kvlist);\n-\t\t\t\treturn ret;\n+\t\t\t\tif (ret != 0) {\n+\t\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing num_dir_credits parameter\",\n+\t\t\t\t\t\t name);\n+\t\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\t\treturn ret;\n+\t\t\t\t}\n \t\t\t}\n-\n \t\t\tret = rte_kvargs_process(kvlist, DEV_ID_ARG,\n \t\t\t\t\t\t set_dev_id,\n \t\t\t\t\t\t &dlb2_args->dev_id);\n@@ -4005,11 +4056,19 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n-\t\t\tret = rte_kvargs_process(\n+\t\t\tif (version == DLB2_HW_V2) {\n+\t\t\t\tret = rte_kvargs_process(\n \t\t\t\t\tkvlist,\n \t\t\t\t\tDLB2_QID_DEPTH_THRESH_ARG,\n \t\t\t\t\tset_qid_depth_thresh,\n \t\t\t\t\t&dlb2_args->qid_depth_thresholds);\n+\t\t\t} else {\n+\t\t\t\tret = rte_kvargs_process(\n+\t\t\t\t\tkvlist,\n+\t\t\t\t\tDLB2_QID_DEPTH_THRESH_ARG,\n+\t\t\t\t\tset_qid_depth_thresh_v2_5,\n+\t\t\t\t\t&dlb2_args->qid_depth_thresholds);\n+\t\t\t}\n \t\t\tif (ret != 0) {\n \t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing qid_depth_thresh parameter\",\n \t\t\t\t\t name);\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex eb1a93239..1cd78ad94 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -33,19 +33,31 @@\n \n /* Begin HW related defines and structs */\n \n+#define DLB2_HW_V2 0\n+#define DLB2_HW_V2_5 1\n #define DLB2_MAX_NUM_DOMAINS 32\n #define DLB2_MAX_NUM_VFS 16\n #define DLB2_MAX_NUM_LDB_QUEUES 32\n #define DLB2_MAX_NUM_LDB_PORTS 64\n-#define DLB2_MAX_NUM_DIR_PORTS 64\n-#define DLB2_MAX_NUM_DIR_QUEUES 64\n+#define DLB2_MAX_NUM_DIR_PORTS_V2\t\tDLB2_MAX_NUM_DIR_QUEUES_V2\n+#define DLB2_MAX_NUM_DIR_PORTS_V2_5\t\tDLB2_MAX_NUM_DIR_QUEUES_V2_5\n+#define DLB2_MAX_NUM_DIR_PORTS(ver)\t\t(ver == DLB2_HW_V2 ? \\\n+\t\t\t\t\t\t DLB2_MAX_NUM_DIR_PORTS_V2 : \\\n+\t\t\t\t\t\t DLB2_MAX_NUM_DIR_PORTS_V2_5)\n+#define DLB2_MAX_NUM_DIR_QUEUES_V2\t\t64 /* DIR == directed */\n+#define DLB2_MAX_NUM_DIR_QUEUES_V2_5\t\t96\n+/* When needed for array sizing, the DLB 2.5 macro is used */\n+#define DLB2_MAX_NUM_DIR_QUEUES(ver)\t\t(ver == DLB2_HW_V2 ? \\\n+\t\t\t\t\t\t DLB2_MAX_NUM_DIR_QUEUES_V2 : \\\n+\t\t\t\t\t\t DLB2_MAX_NUM_DIR_QUEUES_V2_5)\n #define DLB2_MAX_NUM_FLOWS (64 * 1024)\n #define DLB2_MAX_NUM_LDB_CREDITS (8 * 1024)\n-#define DLB2_MAX_NUM_DIR_CREDITS (2 * 1024)\n+#define DLB2_MAX_NUM_DIR_CREDITS(ver)\t\t(ver == DLB2_HW_V2 ? 4096 : 0)\n+#define DLB2_MAX_NUM_CREDITS(ver)\t\t(ver == DLB2_HW_V2 ? \\\n+\t\t\t\t\t\t 0 : DLB2_MAX_NUM_LDB_CREDITS)\n #define DLB2_MAX_NUM_LDB_CREDIT_POOLS 64\n #define DLB2_MAX_NUM_DIR_CREDIT_POOLS 64\n #define DLB2_MAX_NUM_HIST_LIST_ENTRIES 2048\n-#define DLB2_MAX_NUM_AQOS_ENTRIES 2048\n #define DLB2_MAX_NUM_QIDS_PER_LDB_CQ 8\n #define DLB2_QID_PRIORITIES 8\n #define DLB2_MAX_DEVICE_PATH 32\n@@ -68,6 +80,11 @@\n #define DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT \\\n \tDLB2_MAX_CQ_DEPTH\n \n+#define DLB2_HW_DEVICE_FROM_PCI_ID(_pdev) \\\n+\t(((_pdev->id.device_id == PCI_DEVICE_ID_INTEL_DLB2_5_PF) || \\\n+\t (_pdev->id.device_id == PCI_DEVICE_ID_INTEL_DLB2_5_VF)) ? \\\n+\t\tDLB2_HW_V2_5 : DLB2_HW_V2)\n+\n /*\n * Static per queue/port provisioning values\n */\n@@ -109,6 +126,8 @@ enum dlb2_hw_queue_types {\n \tDLB2_NUM_QUEUE_TYPES /* Must be last */\n };\n \n+#define DLB2_COMBINED_POOL DLB2_LDB_QUEUE\n+\n #define PORT_TYPE(p) ((p)->is_directed ? DLB2_DIR_PORT : DLB2_LDB_PORT)\n \n /* Do not change - must match hardware! */\n@@ -127,8 +146,15 @@ struct dlb2_hw_rsrcs {\n \tuint32_t num_ldb_queues;\t/* Number of available ldb queues */\n \tuint32_t num_ldb_ports; /* Number of load balanced ports */\n \tuint32_t num_dir_ports; /* Number of directed ports */\n-\tuint32_t num_ldb_credits; /* Number of load balanced credits */\n-\tuint32_t num_dir_credits; /* Number of directed credits */\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t num_ldb_credits; /* Number of ldb credits */\n+\t\t\tuint32_t num_dir_credits; /* Number of dir credits */\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint32_t num_credits; /* Number of combined credits */\n+\t\t};\n+\t};\n \tuint32_t reorder_window_size; /* Size of reorder window */\n };\n \n@@ -292,9 +318,17 @@ struct dlb2_port {\n \tenum dlb2_token_pop_mode token_pop_mode;\n \tunion dlb2_port_config cfg;\n \tuint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */\n-\tuint16_t cached_ldb_credits;\n-\tuint16_t ldb_credits;\n-\tuint16_t cached_dir_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t cached_ldb_credits;\n+\t\t\tuint16_t ldb_credits;\n+\t\t\tuint16_t cached_dir_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint16_t cached_credits;\n+\t\t\tuint16_t credits;\n+\t\t};\n+\t};\n \tbool int_armed;\n \tuint16_t owed_tokens;\n \tint16_t issued_releases;\n@@ -325,11 +359,22 @@ struct process_local_port_data {\n \n struct dlb2_eventdev;\n \n+struct dlb2_port_low_level_io_functions {\n+\tvoid (*pp_enqueue_four)(void *qe4, void *pp_addr);\n+};\n+\n struct dlb2_config {\n \tint configured;\n \tint reserved;\n-\tuint32_t num_ldb_credits;\n-\tuint32_t num_dir_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t num_ldb_credits;\n+\t\t\tuint32_t num_dir_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint32_t num_credits;\n+\t\t};\n+\t};\n \tstruct dlb2_create_sched_domain_args resources;\n };\n \n@@ -354,10 +399,18 @@ struct dlb2_hw_dev {\n \n /* Begin DLB2 PMD Eventdev related defines and structs */\n \n-#define DLB2_MAX_NUM_QUEUES \\\n-\t(DLB2_MAX_NUM_DIR_QUEUES + DLB2_MAX_NUM_LDB_QUEUES)\n+#define DLB2_MAX_NUM_QUEUES(ver) \\\n+\t(DLB2_MAX_NUM_DIR_QUEUES(ver) + DLB2_MAX_NUM_LDB_QUEUES)\n \n-#define DLB2_MAX_NUM_PORTS (DLB2_MAX_NUM_DIR_PORTS + DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_MAX_NUM_PORTS(ver) \\\n+\t(DLB2_MAX_NUM_DIR_PORTS(ver) + DLB2_MAX_NUM_LDB_PORTS)\n+\n+#define DLB2_MAX_NUM_DIR_QUEUES_V2_5 96\n+#define DLB2_MAX_NUM_DIR_PORTS_V2_5 DLB2_MAX_NUM_DIR_QUEUES_V2_5\n+#define DLB2_MAX_NUM_QUEUES_ALL \\\n+\t(DLB2_MAX_NUM_DIR_QUEUES_V2_5 + DLB2_MAX_NUM_LDB_QUEUES)\n+#define DLB2_MAX_NUM_PORTS_ALL \\\n+\t(DLB2_MAX_NUM_DIR_PORTS_V2_5 + DLB2_MAX_NUM_LDB_PORTS)\n #define DLB2_MAX_INPUT_QUEUE_DEPTH 256\n \n /** Structure to hold the queue to port link establishment attributes */\n@@ -377,8 +430,15 @@ struct dlb2_traffic_stats {\n \tuint64_t tx_ok;\n \tuint64_t total_polls;\n \tuint64_t zero_polls;\n-\tuint64_t tx_nospc_ldb_hw_credits;\n-\tuint64_t tx_nospc_dir_hw_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t tx_nospc_ldb_hw_credits;\n+\t\t\tuint64_t tx_nospc_dir_hw_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint64_t tx_nospc_hw_credits;\n+\t\t};\n+\t};\n \tuint64_t tx_nospc_inflight_max;\n \tuint64_t tx_nospc_new_event_limit;\n \tuint64_t tx_nospc_inflight_credits;\n@@ -411,7 +471,7 @@ struct dlb2_port_stats {\n \tuint64_t tx_invalid;\n \tuint64_t rx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];\n \tuint64_t rx_sched_invalid;\n-\tstruct dlb2_queue_stats queue[DLB2_MAX_NUM_QUEUES];\n+\tstruct dlb2_queue_stats queue[DLB2_MAX_NUM_QUEUES_ALL];\n };\n \n struct dlb2_eventdev_port {\n@@ -462,16 +522,16 @@ enum dlb2_run_state {\n };\n \n struct dlb2_eventdev {\n-\tstruct dlb2_eventdev_port ev_ports[DLB2_MAX_NUM_PORTS];\n-\tstruct dlb2_eventdev_queue ev_queues[DLB2_MAX_NUM_QUEUES];\n-\tuint8_t qm_ldb_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];\n-\tuint8_t qm_dir_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];\n+\tstruct dlb2_eventdev_port ev_ports[DLB2_MAX_NUM_PORTS_ALL];\n+\tstruct dlb2_eventdev_queue ev_queues[DLB2_MAX_NUM_QUEUES_ALL];\n+\tuint8_t qm_ldb_to_ev_queue_id[DLB2_MAX_NUM_QUEUES_ALL];\n+\tuint8_t qm_dir_to_ev_queue_id[DLB2_MAX_NUM_QUEUES_ALL];\n \t/* store num stats and offset of the stats for each queue */\n-\tuint16_t xstats_count_per_qid[DLB2_MAX_NUM_QUEUES];\n-\tuint16_t xstats_offset_for_qid[DLB2_MAX_NUM_QUEUES];\n+\tuint16_t xstats_count_per_qid[DLB2_MAX_NUM_QUEUES_ALL];\n+\tuint16_t xstats_offset_for_qid[DLB2_MAX_NUM_QUEUES_ALL];\n \t/* store num stats and offset of the stats for each port */\n-\tuint16_t xstats_count_per_port[DLB2_MAX_NUM_PORTS];\n-\tuint16_t xstats_offset_for_port[DLB2_MAX_NUM_PORTS];\n+\tuint16_t xstats_count_per_port[DLB2_MAX_NUM_PORTS_ALL];\n+\tuint16_t xstats_offset_for_port[DLB2_MAX_NUM_PORTS_ALL];\n \tstruct dlb2_get_num_resources_args hw_rsrc_query_results;\n \tuint32_t xstats_count_mode_queue;\n \tstruct dlb2_hw_dev qm_instance; /* strictly hw related */\n@@ -487,8 +547,15 @@ struct dlb2_eventdev {\n \tint num_dir_credits_override;\n \tvolatile enum dlb2_run_state run_state;\n \tuint16_t num_dir_queues; /* total num of evdev dir queues requested */\n-\tuint16_t num_dir_credits;\n-\tuint16_t num_ldb_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t num_dir_credits;\n+\t\t\tuint16_t num_ldb_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint16_t num_credits;\n+\t\t};\n+\t};\n \tuint16_t num_queues; /* total queues */\n \tuint16_t num_ldb_queues; /* total num of evdev ldb queues requested */\n \tuint16_t num_ports; /* total num of evdev ports requested */\n@@ -499,21 +566,28 @@ struct dlb2_eventdev {\n \tbool defer_sched;\n \tenum dlb2_cq_poll_modes poll_mode;\n \tuint8_t revision;\n+\tuint8_t version;\n \tbool configured;\n-\tuint16_t max_ldb_credits;\n-\tuint16_t max_dir_credits;\n-\n-\t/* force hw credit pool counters into exclusive cache lines */\n-\n-\t/* use __atomic builtins */ /* shared hw cred */\n-\tuint32_t ldb_credit_pool __rte_cache_aligned;\n-\t/* use __atomic builtins */ /* shared hw cred */\n-\tuint32_t dir_credit_pool __rte_cache_aligned;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint16_t max_ldb_credits;\n+\t\t\tuint16_t max_dir_credits;\n+\t\t\t/* use __atomic builtins */ /* shared hw cred */\n+\t\t\tuint32_t ldb_credit_pool __rte_cache_aligned;\n+\t\t\t/* use __atomic builtins */ /* shared hw cred */\n+\t\t\tuint32_t dir_credit_pool __rte_cache_aligned;\n+\t\t};\n+\t\tstruct {\n+\t\t\tuint16_t max_credits;\n+\t\t\t/* use __atomic builtins */ /* shared hw cred */\n+\t\t\tuint32_t credit_pool __rte_cache_aligned;\n+\t\t};\n+\t};\n };\n \n /* used for collecting and passing around the dev args */\n struct dlb2_qid_depth_thresholds {\n-\tint val[DLB2_MAX_NUM_QUEUES];\n+\tint val[DLB2_MAX_NUM_QUEUES_ALL];\n };\n \n struct dlb2_devargs {\n@@ -568,7 +642,8 @@ uint32_t dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,\n \n int dlb2_parse_params(const char *params,\n \t\t const char *name,\n-\t\t struct dlb2_devargs *dlb2_args);\n+\t\t struct dlb2_devargs *dlb2_args,\n+\t\t uint8_t version);\n \n /* Extern globals */\n extern struct process_local_port_data dlb2_port[][DLB2_NUM_PORT_TYPES];\ndiff --git a/drivers/event/dlb2/dlb2_xstats.c b/drivers/event/dlb2/dlb2_xstats.c\nindex 8c3c3cda9..b62e62060 100644\n--- a/drivers/event/dlb2/dlb2_xstats.c\n+++ b/drivers/event/dlb2/dlb2_xstats.c\n@@ -95,7 +95,7 @@ dlb2_device_traffic_stat_get(struct dlb2_eventdev *dlb2,\n \tint i;\n \tuint64_t val = 0;\n \n-\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++) {\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {\n \t\tstruct dlb2_eventdev_port *port = &dlb2->ev_ports[i];\n \n \t\tif (!port->setup_done)\n@@ -269,7 +269,7 @@ dlb2_get_threshold_stat(struct dlb2_eventdev *dlb2, int qid, int stat)\n \tint port = 0;\n \tuint64_t tally = 0;\n \n-\tfor (port = 0; port < DLB2_MAX_NUM_PORTS; port++)\n+\tfor (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++)\n \t\ttally += dlb2->ev_ports[port].stats.queue[qid].qid_depth[stat];\n \n \treturn tally;\n@@ -281,7 +281,7 @@ dlb2_get_enq_ok_stat(struct dlb2_eventdev *dlb2, int qid)\n \tint port = 0;\n \tuint64_t enq_ok_tally = 0;\n \n-\tfor (port = 0; port < DLB2_MAX_NUM_PORTS; port++)\n+\tfor (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++)\n \t\tenq_ok_tally += dlb2->ev_ports[port].stats.queue[qid].enq_ok;\n \n \treturn enq_ok_tally;\n@@ -561,8 +561,8 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \n \t/* other vars */\n \tconst unsigned int count = RTE_DIM(dev_stats) +\n-\t\t\tDLB2_MAX_NUM_PORTS * RTE_DIM(port_stats) +\n-\t\t\tDLB2_MAX_NUM_QUEUES * RTE_DIM(qid_stats);\n+\t\tDLB2_MAX_NUM_PORTS(dlb2->version) * RTE_DIM(port_stats) +\n+\t\tDLB2_MAX_NUM_QUEUES(dlb2->version) * RTE_DIM(qid_stats);\n \tunsigned int i, port, qid, stat_id = 0;\n \n \tdlb2->xstats = rte_zmalloc_socket(NULL,\n@@ -583,7 +583,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \t}\n \tdlb2->xstats_count_mode_dev = stat_id;\n \n-\tfor (port = 0; port < DLB2_MAX_NUM_PORTS; port++) {\n+\tfor (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++) {\n \t\tdlb2->xstats_offset_for_port[port] = stat_id;\n \n \t\tuint32_t count_offset = stat_id;\n@@ -605,7 +605,7 @@ dlb2_xstats_init(struct dlb2_eventdev *dlb2)\n \n \tdlb2->xstats_count_mode_port = stat_id - dlb2->xstats_count_mode_dev;\n \n-\tfor (qid = 0; qid < DLB2_MAX_NUM_QUEUES; qid++) {\n+\tfor (qid = 0; qid < DLB2_MAX_NUM_QUEUES(dlb2->version); qid++) {\n \t\tuint32_t count_offset = stat_id;\n \n \t\tdlb2->xstats_offset_for_qid[qid] = stat_id;\n@@ -658,16 +658,15 @@ dlb2_eventdev_xstats_get_names(const struct rte_eventdev *dev,\n \t\txstats_mode_count = dlb2->xstats_count_mode_dev;\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_PORT:\n-\t\tif (queue_port_id >= DLB2_MAX_NUM_PORTS)\n+\t\tif (queue_port_id >= DLB2_MAX_NUM_PORTS(dlb2->version))\n \t\t\tbreak;\n \t\txstats_mode_count = dlb2->xstats_count_per_port[queue_port_id];\n \t\tstart_offset = dlb2->xstats_offset_for_port[queue_port_id];\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n-#if (DLB2_MAX_NUM_QUEUES <= 255) /* max 8 bit value */\n-\t\tif (queue_port_id >= DLB2_MAX_NUM_QUEUES)\n+\t\tif (queue_port_id >= DLB2_MAX_NUM_QUEUES(dlb2->version) &&\n+\t\t (DLB2_MAX_NUM_QUEUES(dlb2->version) <= 255))\n \t\t\tbreak;\n-#endif\n \t\txstats_mode_count = dlb2->xstats_count_per_qid[queue_port_id];\n \t\tstart_offset = dlb2->xstats_offset_for_qid[queue_port_id];\n \t\tbreak;\n@@ -709,13 +708,13 @@ dlb2_xstats_update(struct dlb2_eventdev *dlb2,\n \t\txstats_mode_count = dlb2->xstats_count_mode_dev;\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_PORT:\n-\t\tif (queue_port_id >= DLB2_MAX_NUM_PORTS)\n+\t\tif (queue_port_id >= DLB2_MAX_NUM_PORTS(dlb2->version))\n \t\t\tgoto invalid_value;\n \t\txstats_mode_count = dlb2->xstats_count_per_port[queue_port_id];\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n-#if (DLB2_MAX_NUM_QUEUES <= 255) /* max 8 bit value */\n-\t\tif (queue_port_id >= DLB2_MAX_NUM_QUEUES)\n+#if (DLB2_MAX_NUM_QUEUES(DLB2_HW_V2_5) <= 255) /* max 8 bit value */\n+\t\tif (queue_port_id >= DLB2_MAX_NUM_QUEUES(dlb2->version))\n \t\t\tgoto invalid_value;\n #endif\n \t\txstats_mode_count = dlb2->xstats_count_per_qid[queue_port_id];\n@@ -936,12 +935,13 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_PORT:\n \t\tif (queue_port_id == -1) {\n-\t\t\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++) {\n+\t\t\tfor (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version);\n+\t\t\t\t\ti++) {\n \t\t\t\tif (dlb2_xstats_reset_port(dlb2, i,\n \t\t\t\t\t\t\t ids, nb_ids))\n \t\t\t\t\treturn -EINVAL;\n \t\t\t}\n-\t\t} else if (queue_port_id < DLB2_MAX_NUM_PORTS) {\n+\t\t} else if (queue_port_id < DLB2_MAX_NUM_PORTS(dlb2->version)) {\n \t\t\tif (dlb2_xstats_reset_port(dlb2, queue_port_id,\n \t\t\t\t\t\t ids, nb_ids))\n \t\t\t\treturn -EINVAL;\n@@ -949,12 +949,13 @@ dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n \t\tif (queue_port_id == -1) {\n-\t\t\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES; i++) {\n+\t\t\tfor (i = 0; i < DLB2_MAX_NUM_QUEUES(dlb2->version);\n+\t\t\t\t\ti++) {\n \t\t\t\tif (dlb2_xstats_reset_queue(dlb2, i,\n \t\t\t\t\t\t\t ids, nb_ids))\n \t\t\t\t\treturn -EINVAL;\n \t\t\t}\n-\t\t} else if (queue_port_id < DLB2_MAX_NUM_QUEUES) {\n+\t\t} else if (queue_port_id < DLB2_MAX_NUM_QUEUES(dlb2->version)) {\n \t\t\tif (dlb2_xstats_reset_queue(dlb2, queue_port_id,\n \t\t\t\t\t\t ids, nb_ids))\n \t\t\t\treturn -EINVAL;\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nindex 1d99f1e01..b007e1674 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -5,54 +5,31 @@\n #ifndef __DLB2_HW_TYPES_H\n #define __DLB2_HW_TYPES_H\n \n+#include \"../../dlb2_priv.h\"\n #include \"dlb2_user.h\"\n \n #include \"dlb2_osdep_list.h\"\n #include \"dlb2_osdep_types.h\"\n \n #define DLB2_MAX_NUM_VDEVS\t\t\t16\n-#define DLB2_MAX_NUM_DOMAINS\t\t\t32\n-#define DLB2_MAX_NUM_LDB_QUEUES\t\t\t32 /* LDB == load-balanced */\n-#define DLB2_MAX_NUM_DIR_QUEUES\t\t\t64 /* DIR == directed */\n-#define DLB2_MAX_NUM_LDB_PORTS\t\t\t64\n-#define DLB2_MAX_NUM_DIR_PORTS\t\t\t64\n-#define DLB2_MAX_NUM_LDB_CREDITS\t\t(8 * 1024)\n-#define DLB2_MAX_NUM_DIR_CREDITS\t\t(2 * 1024)\n-#define DLB2_MAX_NUM_HIST_LIST_ENTRIES\t\t2048\n-#define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n-#define DLB2_MAX_NUM_QIDS_PER_LDB_CQ\t\t8\n #define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n-#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n-#define DLB2_QID_PRIORITIES\t\t\t8\n #define DLB2_NUM_ARB_WEIGHTS\t\t\t8\n+#define DLB2_MAX_NUM_AQED_ENTRIES\t\t2048\n #define DLB2_MAX_WEIGHT\t\t\t\t255\n #define DLB2_NUM_COS_DOMAINS\t\t\t4\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS\t2\n+#define DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES\t5\n #define DLB2_MAX_CQ_COMP_CHECK_LOOPS\t\t409600\n #define DLB2_MAX_QID_EMPTY_CHECK_LOOPS\t\t(32 * 64 * 1024 * (800 / 30))\n-#ifdef FPGA\n-#define DLB2_HZ\t\t\t\t\t2000000\n-#else\n-#define DLB2_HZ\t\t\t\t\t800000000\n-#endif\n+\n+#define DLB2_FUNC_BAR\t\t\t\t0\n+#define DLB2_CSR_BAR\t\t\t\t2\n \n #define PCI_DEVICE_ID_INTEL_DLB2_PF 0x2710\n #define PCI_DEVICE_ID_INTEL_DLB2_VF 0x2711\n \n-/* Interrupt related macros */\n-#define DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n-#define DLB2_PF_NUM_CQ_INTERRUPT_VECTORS 64\n-#define DLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS \\\n-\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n-\t DLB2_PF_NUM_CQ_INTERRUPT_VECTORS)\n-#define DLB2_PF_NUM_COMPRESSED_MODE_VECTORS \\\n-\t(DLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS + 1)\n-#define DLB2_PF_NUM_PACKED_MODE_VECTORS \\\n-\tDLB2_PF_TOTAL_NUM_INTERRUPT_VECTORS\n-#define DLB2_PF_COMPRESSED_MODE_CQ_VECTOR_ID \\\n-\tDLB2_PF_NUM_NON_CQ_INTERRUPT_VECTORS\n-\n-/* DLB non-CQ interrupts (alarm, mailbox, WDT) */\n-#define DLB2_INT_NON_CQ 0\n+#define PCI_DEVICE_ID_INTEL_DLB2_5_PF 0x2714\n+#define PCI_DEVICE_ID_INTEL_DLB2_5_VF 0x2715\n \n #define DLB2_ALARM_HW_SOURCE_SYS 0\n #define DLB2_ALARM_HW_SOURCE_DLB 1\n@@ -65,18 +42,6 @@\n #define DLB2_ALARM_HW_CHP_AID_ILLEGAL_ENQ\t1\n #define DLB2_ALARM_HW_CHP_AID_EXCESS_TOKEN_POPS 2\n \n-#define DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS 1\n-#define DLB2_VF_NUM_CQ_INTERRUPT_VECTORS 31\n-#define DLB2_VF_BASE_CQ_VECTOR_ID\t 0\n-#define DLB2_VF_LAST_CQ_VECTOR_ID\t 30\n-#define DLB2_VF_MBOX_VECTOR_ID\t\t 31\n-#define DLB2_VF_TOTAL_NUM_INTERRUPT_VECTORS \\\n-\t(DLB2_VF_NUM_NON_CQ_INTERRUPT_VECTORS + \\\n-\t DLB2_VF_NUM_CQ_INTERRUPT_VECTORS)\n-\n-#define DLB2_VDEV_MAX_NUM_INTERRUPT_VECTORS (DLB2_MAX_NUM_LDB_PORTS + \\\n-\t\t\t\t\t DLB2_MAX_NUM_DIR_PORTS + 1)\n-\n /*\n * Hardware-defined base addresses. Those prefixed 'DLB2_DRV' are only used by\n * the PF driver.\n@@ -97,7 +62,8 @@\n #define DLB2_DIR_PP_BASE 0x2000000\n #define DLB2_DIR_PP_STRIDE 0x1000\n #define DLB2_DIR_PP_BOUND (DLB2_DIR_PP_BASE + \\\n-\t\t\t\tDLB2_DIR_PP_STRIDE * DLB2_MAX_NUM_DIR_PORTS)\n+\t\t\t\tDLB2_DIR_PP_STRIDE * \\\n+\t\t\t\tDLB2_MAX_NUM_DIR_PORTS_V2_5)\n #define DLB2_DIR_PP_OFFS(id) (DLB2_DIR_PP_BASE + (id) * DLB2_PP_SIZE)\n \n struct dlb2_resource_id {\n@@ -225,7 +191,7 @@ struct dlb2_sn_group {\n \n static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)\n {\n-\tu32 mask[] = {\n+\tconst u32 mask[] = {\n \t\t0x0000ffff, /* 64 SNs per queue */\n \t\t0x000000ff, /* 128 SNs per queue */\n \t\t0x0000000f, /* 256 SNs per queue */\n@@ -237,7 +203,7 @@ static inline bool dlb2_sn_group_full(struct dlb2_sn_group *group)\n \n static inline int dlb2_sn_group_alloc_slot(struct dlb2_sn_group *group)\n {\n-\tu32 bound[6] = {16, 8, 4, 2, 1};\n+\tconst u32 bound[] = {16, 8, 4, 2, 1};\n \tu32 i;\n \n \tfor (i = 0; i < bound[group->mode]; i++) {\n@@ -327,7 +293,7 @@ struct dlb2_function_resources {\n struct dlb2_hw_resources {\n \tstruct dlb2_ldb_queue ldb_queues[DLB2_MAX_NUM_LDB_QUEUES];\n \tstruct dlb2_ldb_port ldb_ports[DLB2_MAX_NUM_LDB_PORTS];\n-\tstruct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS];\n+\tstruct dlb2_dir_pq_pair dir_pq_pairs[DLB2_MAX_NUM_DIR_PORTS_V2_5];\n \tstruct dlb2_sn_group sn_groups[DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS];\n };\n \n@@ -344,11 +310,13 @@ struct dlb2_sw_mbox {\n };\n \n struct dlb2_hw {\n+\tuint8_t ver;\n+\n \t/* BAR 0 address */\n-\tvoid *csr_kva;\n+\tvoid *csr_kva;\n \tunsigned long csr_phys_addr;\n \t/* BAR 2 address */\n-\tvoid *func_kva;\n+\tvoid *func_kva;\n \tunsigned long func_phys_addr;\n \n \t/* Resource tracking */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_mbox.h b/drivers/event/dlb2/pf/base/dlb2_mbox.h\ndeleted file mode 100644\nindex ce462c089..000000000\n--- a/drivers/event/dlb2/pf/base/dlb2_mbox.h\n+++ /dev/null\n@@ -1,596 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2020 Intel Corporation\n- */\n-\n-#ifndef __DLB2_BASE_DLB2_MBOX_H\n-#define __DLB2_BASE_DLB2_MBOX_H\n-\n-#include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs.h\"\n-\n-#define DLB2_MBOX_INTERFACE_VERSION 1\n-\n-/*\n- * The PF uses its PF->VF mailbox to send responses to VF requests, as well as\n- * to send requests of its own (e.g. notifying a VF of an impending FLR).\n- * To avoid communication race conditions, e.g. the PF sends a response and then\n- * sends a request before the VF reads the response, the PF->VF mailbox is\n- * divided into two sections:\n- * - Bytes 0-47: PF responses\n- * - Bytes 48-63: PF requests\n- *\n- * Partitioning the PF->VF mailbox allows responses and requests to occupy the\n- * mailbox simultaneously.\n- */\n-#define DLB2_PF2VF_RESP_BYTES\t 48\n-#define DLB2_PF2VF_RESP_BASE\t 0\n-#define DLB2_PF2VF_RESP_BASE_WORD (DLB2_PF2VF_RESP_BASE / 4)\n-\n-#define DLB2_PF2VF_REQ_BYTES\t 16\n-#define DLB2_PF2VF_REQ_BASE\t (DLB2_PF2VF_RESP_BASE + DLB2_PF2VF_RESP_BYTES)\n-#define DLB2_PF2VF_REQ_BASE_WORD (DLB2_PF2VF_REQ_BASE / 4)\n-\n-/*\n- * Similarly, the VF->PF mailbox is divided into two sections:\n- * - Bytes 0-239: VF requests\n- * -- (Bytes 0-3 are unused due to a hardware errata)\n- * - Bytes 240-255: VF responses\n- */\n-#define DLB2_VF2PF_REQ_BYTES\t 236\n-#define DLB2_VF2PF_REQ_BASE\t 4\n-#define DLB2_VF2PF_REQ_BASE_WORD (DLB2_VF2PF_REQ_BASE / 4)\n-\n-#define DLB2_VF2PF_RESP_BYTES\t 16\n-#define DLB2_VF2PF_RESP_BASE\t (DLB2_VF2PF_REQ_BASE + DLB2_VF2PF_REQ_BYTES)\n-#define DLB2_VF2PF_RESP_BASE_WORD (DLB2_VF2PF_RESP_BASE / 4)\n-\n-/* VF-initiated commands */\n-enum dlb2_mbox_cmd_type {\n-\tDLB2_MBOX_CMD_REGISTER,\n-\tDLB2_MBOX_CMD_UNREGISTER,\n-\tDLB2_MBOX_CMD_GET_NUM_RESOURCES,\n-\tDLB2_MBOX_CMD_CREATE_SCHED_DOMAIN,\n-\tDLB2_MBOX_CMD_RESET_SCHED_DOMAIN,\n-\tDLB2_MBOX_CMD_CREATE_LDB_QUEUE,\n-\tDLB2_MBOX_CMD_CREATE_DIR_QUEUE,\n-\tDLB2_MBOX_CMD_CREATE_LDB_PORT,\n-\tDLB2_MBOX_CMD_CREATE_DIR_PORT,\n-\tDLB2_MBOX_CMD_ENABLE_LDB_PORT,\n-\tDLB2_MBOX_CMD_DISABLE_LDB_PORT,\n-\tDLB2_MBOX_CMD_ENABLE_DIR_PORT,\n-\tDLB2_MBOX_CMD_DISABLE_DIR_PORT,\n-\tDLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN,\n-\tDLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN,\n-\tDLB2_MBOX_CMD_MAP_QID,\n-\tDLB2_MBOX_CMD_UNMAP_QID,\n-\tDLB2_MBOX_CMD_START_DOMAIN,\n-\tDLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR,\n-\tDLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR,\n-\tDLB2_MBOX_CMD_ARM_CQ_INTR,\n-\tDLB2_MBOX_CMD_GET_NUM_USED_RESOURCES,\n-\tDLB2_MBOX_CMD_GET_SN_ALLOCATION,\n-\tDLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH,\n-\tDLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH,\n-\tDLB2_MBOX_CMD_PENDING_PORT_UNMAPS,\n-\tDLB2_MBOX_CMD_GET_COS_BW,\n-\tDLB2_MBOX_CMD_GET_SN_OCCUPANCY,\n-\tDLB2_MBOX_CMD_QUERY_CQ_POLL_MODE,\n-\n-\t/* NUM_QE_CMD_TYPES must be last */\n-\tNUM_DLB2_MBOX_CMD_TYPES,\n-};\n-\n-static const char dlb2_mbox_cmd_type_strings[][128] = {\n-\t\"DLB2_MBOX_CMD_REGISTER\",\n-\t\"DLB2_MBOX_CMD_UNREGISTER\",\n-\t\"DLB2_MBOX_CMD_GET_NUM_RESOURCES\",\n-\t\"DLB2_MBOX_CMD_CREATE_SCHED_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_RESET_SCHED_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_CREATE_LDB_QUEUE\",\n-\t\"DLB2_MBOX_CMD_CREATE_DIR_QUEUE\",\n-\t\"DLB2_MBOX_CMD_CREATE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_CREATE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_DISABLE_LDB_PORT\",\n-\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_DISABLE_DIR_PORT\",\n-\t\"DLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_MAP_QID\",\n-\t\"DLB2_MBOX_CMD_UNMAP_QID\",\n-\t\"DLB2_MBOX_CMD_START_DOMAIN\",\n-\t\"DLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR\",\n-\t\"DLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR\",\n-\t\"DLB2_MBOX_CMD_ARM_CQ_INTR\",\n-\t\"DLB2_MBOX_CMD_GET_NUM_USED_RESOURCES\",\n-\t\"DLB2_MBOX_CMD_GET_SN_ALLOCATION\",\n-\t\"DLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH\",\n-\t\"DLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH\",\n-\t\"DLB2_MBOX_CMD_PENDING_PORT_UNMAPS\",\n-\t\"DLB2_MBOX_CMD_GET_COS_BW\",\n-\t\"DLB2_MBOX_CMD_GET_SN_OCCUPANCY\",\n-\t\"DLB2_MBOX_CMD_QUERY_CQ_POLL_MODE\",\n-};\n-\n-/* PF-initiated commands */\n-enum dlb2_mbox_vf_cmd_type {\n-\tDLB2_MBOX_VF_CMD_DOMAIN_ALERT,\n-\tDLB2_MBOX_VF_CMD_NOTIFICATION,\n-\tDLB2_MBOX_VF_CMD_IN_USE,\n-\n-\t/* NUM_DLB2_MBOX_VF_CMD_TYPES must be last */\n-\tNUM_DLB2_MBOX_VF_CMD_TYPES,\n-};\n-\n-static const char dlb2_mbox_vf_cmd_type_strings[][128] = {\n-\t\"DLB2_MBOX_VF_CMD_DOMAIN_ALERT\",\n-\t\"DLB2_MBOX_VF_CMD_NOTIFICATION\",\n-\t\"DLB2_MBOX_VF_CMD_IN_USE\",\n-};\n-\n-#define DLB2_MBOX_CMD_TYPE(hdr) \\\n-\t(((struct dlb2_mbox_req_hdr *)hdr)->type)\n-#define DLB2_MBOX_CMD_STRING(hdr) \\\n-\tdlb2_mbox_cmd_type_strings[DLB2_MBOX_CMD_TYPE(hdr)]\n-\n-enum dlb2_mbox_status_type {\n-\tDLB2_MBOX_ST_SUCCESS,\n-\tDLB2_MBOX_ST_INVALID_CMD_TYPE,\n-\tDLB2_MBOX_ST_VERSION_MISMATCH,\n-\tDLB2_MBOX_ST_INVALID_OWNER_VF,\n-};\n-\n-static const char dlb2_mbox_status_type_strings[][128] = {\n-\t\"DLB2_MBOX_ST_SUCCESS\",\n-\t\"DLB2_MBOX_ST_INVALID_CMD_TYPE\",\n-\t\"DLB2_MBOX_ST_VERSION_MISMATCH\",\n-\t\"DLB2_MBOX_ST_INVALID_OWNER_VF\",\n-};\n-\n-#define DLB2_MBOX_ST_TYPE(hdr) \\\n-\t(((struct dlb2_mbox_resp_hdr *)hdr)->status)\n-#define DLB2_MBOX_ST_STRING(hdr) \\\n-\tdlb2_mbox_status_type_strings[DLB2_MBOX_ST_TYPE(hdr)]\n-\n-/* This structure is always the first field in a request structure */\n-struct dlb2_mbox_req_hdr {\n-\tu32 type;\n-};\n-\n-/* This structure is always the first field in a response structure */\n-struct dlb2_mbox_resp_hdr {\n-\tu32 status;\n-};\n-\n-struct dlb2_mbox_register_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 min_interface_version;\n-\tu16 max_interface_version;\n-};\n-\n-struct dlb2_mbox_register_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 interface_version;\n-\tu8 pf_id;\n-\tu8 vf_id;\n-\tu8 is_auxiliary_vf;\n-\tu8 primary_vf_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_unregister_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_unregister_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_num_resources_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_num_resources_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu16 num_sched_domains;\n-\tu16 num_ldb_queues;\n-\tu16 num_ldb_ports;\n-\tu16 num_cos_ldb_ports[4];\n-\tu16 num_dir_ports;\n-\tu32 num_atomic_inflights;\n-\tu32 num_hist_list_entries;\n-\tu32 max_contiguous_hist_list_entries;\n-\tu16 num_ldb_credits;\n-\tu16 num_dir_credits;\n-};\n-\n-struct dlb2_mbox_create_sched_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 num_ldb_queues;\n-\tu32 num_ldb_ports;\n-\tu32 num_cos_ldb_ports[4];\n-\tu32 num_dir_ports;\n-\tu32 num_atomic_inflights;\n-\tu32 num_hist_list_entries;\n-\tu32 num_ldb_credits;\n-\tu32 num_dir_credits;\n-\tu8 cos_strict;\n-\tu8 padding0[3];\n-\tu32 padding1;\n-};\n-\n-struct dlb2_mbox_create_sched_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_reset_sched_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_reset_sched_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-};\n-\n-struct dlb2_mbox_create_ldb_queue_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 num_sequence_numbers;\n-\tu32 num_qid_inflights;\n-\tu32 num_atomic_inflights;\n-\tu32 lock_id_comp_level;\n-\tu32 depth_threshold;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_create_ldb_queue_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_dir_queue_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 depth_threshold;\n-};\n-\n-struct dlb2_mbox_create_dir_queue_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu16 cq_depth;\n-\tu16 cq_history_list_size;\n-\tu8 cos_id;\n-\tu8 cos_strict;\n-\tu16 padding1;\n-\tu64 cq_base_address;\n-};\n-\n-struct dlb2_mbox_create_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_create_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu64 cq_base_address;\n-\tu16 cq_depth;\n-\tu16 padding0;\n-\ts32 queue_id;\n-};\n-\n-struct dlb2_mbox_create_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_ldb_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_ldb_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_dir_port_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_disable_dir_port_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_ldb_port_owned_by_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_ldb_port_owned_by_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\ts32 owned;\n-};\n-\n-struct dlb2_mbox_dir_port_owned_by_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_dir_port_owned_by_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\ts32 owned;\n-};\n-\n-struct dlb2_mbox_map_qid_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 qid;\n-\tu32 priority;\n-\tu32 padding0;\n-};\n-\n-struct dlb2_mbox_map_qid_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 id;\n-};\n-\n-struct dlb2_mbox_unmap_qid_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 qid;\n-};\n-\n-struct dlb2_mbox_unmap_qid_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_start_domain_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-};\n-\n-struct dlb2_mbox_start_domain_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 port_id;\n-\tu16 thresh;\n-\tu16 vector;\n-\tu16 owner_vf;\n-\tu16 reserved[2];\n-};\n-\n-struct dlb2_mbox_enable_ldb_port_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_enable_dir_port_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu16 port_id;\n-\tu16 thresh;\n-\tu16 vector;\n-\tu16 owner_vf;\n-\tu16 reserved[2];\n-};\n-\n-struct dlb2_mbox_enable_dir_port_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_arm_cq_intr_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 is_ldb;\n-};\n-\n-struct dlb2_mbox_arm_cq_intr_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 padding0;\n-};\n-\n-/*\n- * The alert_id and aux_alert_data follows the format of the alerts defined in\n- * dlb2_types.h. The alert id contains an enum dlb2_domain_alert_id value, and\n- * the aux_alert_data value varies depending on the alert.\n- */\n-struct dlb2_mbox_vf_alert_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 alert_id;\n-\tu32 aux_alert_data;\n-};\n-\n-enum dlb2_mbox_vf_notification_type {\n-\tDLB2_MBOX_VF_NOTIFICATION_PRE_RESET,\n-\tDLB2_MBOX_VF_NOTIFICATION_POST_RESET,\n-\n-\t/* NUM_DLB2_MBOX_VF_NOTIFICATION_TYPES must be last */\n-\tNUM_DLB2_MBOX_VF_NOTIFICATION_TYPES,\n-};\n-\n-struct dlb2_mbox_vf_notification_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 notification;\n-};\n-\n-struct dlb2_mbox_vf_in_use_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_vf_in_use_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 in_use;\n-};\n-\n-struct dlb2_mbox_get_sn_allocation_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 group_id;\n-};\n-\n-struct dlb2_mbox_get_sn_allocation_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_ldb_queue_depth_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 queue_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_ldb_queue_depth_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 depth;\n-};\n-\n-struct dlb2_mbox_get_dir_queue_depth_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 queue_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_get_dir_queue_depth_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 depth;\n-};\n-\n-struct dlb2_mbox_pending_port_unmaps_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 domain_id;\n-\tu32 port_id;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_pending_port_unmaps_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_cos_bw_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 cos_id;\n-};\n-\n-struct dlb2_mbox_get_cos_bw_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_get_sn_occupancy_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 group_id;\n-};\n-\n-struct dlb2_mbox_get_sn_occupancy_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 num;\n-};\n-\n-struct dlb2_mbox_query_cq_poll_mode_cmd_req {\n-\tstruct dlb2_mbox_req_hdr hdr;\n-\tu32 padding;\n-};\n-\n-struct dlb2_mbox_query_cq_poll_mode_cmd_resp {\n-\tstruct dlb2_mbox_resp_hdr hdr;\n-\tu32 error_code;\n-\tu32 status;\n-\tu32 mode;\n-};\n-\n-#endif /* __DLB2_BASE_DLB2_MBOX_H */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex ae5ef2fc3..1cb0b9f50 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -5,7 +5,6 @@\n #include \"dlb2_user.h\"\n \n #include \"dlb2_hw_types.h\"\n-#include \"dlb2_mbox.h\"\n #include \"dlb2_osdep.h\"\n #include \"dlb2_osdep_bitmap.h\"\n #include \"dlb2_osdep_types.h\"\n@@ -212,7 +211,7 @@ int dlb2_resource_init(struct dlb2_hw *hw)\n \t\t\t &port->func_list);\n \t}\n \n-\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS;\n+\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS(hw->ver);\n \tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n \t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n \n@@ -220,7 +219,9 @@ int dlb2_resource_init(struct dlb2_hw *hw)\n \t}\n \n \thw->pf.num_avail_qed_entries = DLB2_MAX_NUM_LDB_CREDITS;\n-\thw->pf.num_avail_dqed_entries = DLB2_MAX_NUM_DIR_CREDITS;\n+\thw->pf.num_avail_dqed_entries =\n+\t\tDLB2_MAX_NUM_DIR_CREDITS(hw->ver);\n+\n \thw->pf.num_avail_aqed_entries = DLB2_MAX_NUM_AQED_ENTRIES;\n \n \tret = dlb2_bitmap_alloc(&hw->pf.avail_hist_list_entries,\n@@ -259,7 +260,7 @@ int dlb2_resource_init(struct dlb2_hw *hw)\n \t\thw->rsrcs.ldb_ports[i].id.vdev_owned = false;\n \t}\n \n-\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS; i++) {\n+\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS(hw->ver); i++) {\n \t\thw->rsrcs.dir_pq_pairs[i].id.phys_id = i;\n \t\thw->rsrcs.dir_pq_pairs[i].id.vdev_owned = false;\n \t}\n@@ -2373,7 +2374,7 @@ static void dlb2_domain_disable_dir_vpps(struct dlb2_hw *hw,\n \t\telse\n \t\t\tvirt_id = port->id.phys_id;\n \n-\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;\n+\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) + virt_id;\n \n \t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), r1.val);\n \t}\n@@ -2506,7 +2507,8 @@ static void\n dlb2_domain_disable_dir_queue_write_perms(struct dlb2_hw *hw,\n \t\t\t\t\t struct dlb2_hw_domain *domain)\n {\n-\tint domain_offset = domain->id.phys_id * DLB2_MAX_NUM_DIR_PORTS;\n+\tint domain_offset = domain->id.phys_id *\n+\t\tDLB2_MAX_NUM_DIR_PORTS(hw->ver);\n \tstruct dlb2_list_entry *iter;\n \tstruct dlb2_dir_pq_pair *queue;\n \tRTE_SET_USED(iter);\n@@ -2522,7 +2524,8 @@ dlb2_domain_disable_dir_queue_write_perms(struct dlb2_hw *hw,\n \t\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(idx), r0.val);\n \n \t\tif (queue->id.vdev_owned) {\n-\t\t\tidx = queue->id.vdev_id * DLB2_MAX_NUM_DIR_PORTS +\n+\t\t\tidx = queue->id.vdev_id *\n+\t\t\t\tDLB2_MAX_NUM_DIR_PORTS(hw->ver) +\n \t\t\t\tqueue->id.virt_id;\n \n \t\t\tDLB2_CSR_WR(hw,\n@@ -2961,7 +2964,8 @@ __dlb2_domain_reset_dir_port_registers(struct dlb2_hw *hw,\n \t\telse\n \t\t\tvirt_id = port->id.phys_id;\n \n-\t\toffs = port->id.vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;\n+\t\toffs = port->id.vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver)\n+\t\t\t+ virt_id;\n \n \t\tDLB2_CSR_WR(hw,\n \t\t\t DLB2_SYS_VF_DIR_VPP2PP(offs),\n@@ -4484,7 +4488,8 @@ dlb2_log_create_dir_port_args(struct dlb2_hw *hw,\n }\n \n static struct dlb2_dir_pq_pair *\n-dlb2_get_domain_used_dir_pq(u32 id,\n+dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,\n+\t\t\t u32 id,\n \t\t\t bool vdev_req,\n \t\t\t struct dlb2_hw_domain *domain)\n {\n@@ -4492,7 +4497,7 @@ dlb2_get_domain_used_dir_pq(u32 id,\n \tstruct dlb2_dir_pq_pair *port;\n \tRTE_SET_USED(iter);\n \n-\tif (id >= DLB2_MAX_NUM_DIR_PORTS)\n+\tif (id >= DLB2_MAX_NUM_DIR_PORTS(hw->ver))\n \t\treturn NULL;\n \n \tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter)\n@@ -4538,7 +4543,8 @@ dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,\n \tif (args->queue_id != -1) {\n \t\tstruct dlb2_dir_pq_pair *queue;\n \n-\t\tqueue = dlb2_get_domain_used_dir_pq(args->queue_id,\n+\t\tqueue = dlb2_get_domain_used_dir_pq(hw,\n+\t\t\t\t\t\t args->queue_id,\n \t\t\t\t\t\t vdev_req,\n \t\t\t\t\t\t domain);\n \n@@ -4618,7 +4624,7 @@ static void dlb2_dir_port_configure_pp(struct dlb2_hw *hw,\n \n \t\tr1.field.pp = port->id.phys_id;\n \n-\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;\n+\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) + virt_id;\n \n \t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP2PP(offs), r1.val);\n \n@@ -4857,7 +4863,8 @@ int dlb2_hw_create_dir_port(struct dlb2_hw *hw,\n \tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n \n \tif (args->queue_id != -1)\n-\t\tport = dlb2_get_domain_used_dir_pq(args->queue_id,\n+\t\tport = dlb2_get_domain_used_dir_pq(hw,\n+\t\t\t\t\t\t args->queue_id,\n \t\t\t\t\t\t vdev_req,\n \t\t\t\t\t\t domain);\n \telse\n@@ -4913,7 +4920,7 @@ static void dlb2_configure_dir_queue(struct dlb2_hw *hw,\n \t/* QID write permissions are turned on when the domain is started */\n \tr0.field.vasqid_v = 0;\n \n-\toffs = domain->id.phys_id * DLB2_MAX_NUM_DIR_QUEUES +\n+\toffs = domain->id.phys_id * DLB2_MAX_NUM_DIR_QUEUES(hw->ver) +\n \t\tqueue->id.phys_id;\n \n \tDLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(offs), r0.val);\n@@ -4935,7 +4942,8 @@ static void dlb2_configure_dir_queue(struct dlb2_hw *hw,\n \t\tunion dlb2_sys_vf_dir_vqid_v r3 = { {0} };\n \t\tunion dlb2_sys_vf_dir_vqid2qid r4 = { {0} };\n \n-\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_QUEUES + queue->id.virt_id;\n+\t\toffs = vdev_id * DLB2_MAX_NUM_DIR_QUEUES(hw->ver)\n+\t\t\t+ queue->id.virt_id;\n \n \t\tr3.field.vqid_v = 1;\n \n@@ -5001,7 +5009,8 @@ dlb2_verify_create_dir_queue_args(struct dlb2_hw *hw,\n \tif (args->port_id != -1) {\n \t\tstruct dlb2_dir_pq_pair *port;\n \n-\t\tport = dlb2_get_domain_used_dir_pq(args->port_id,\n+\t\tport = dlb2_get_domain_used_dir_pq(hw,\n+\t\t\t\t\t\t args->port_id,\n \t\t\t\t\t\t vdev_req,\n \t\t\t\t\t\t domain);\n \n@@ -5072,7 +5081,8 @@ int dlb2_hw_create_dir_queue(struct dlb2_hw *hw,\n \t}\n \n \tif (args->port_id != -1)\n-\t\tqueue = dlb2_get_domain_used_dir_pq(args->port_id,\n+\t\tqueue = dlb2_get_domain_used_dir_pq(hw,\n+\t\t\t\t\t\t args->port_id,\n \t\t\t\t\t\t vdev_req,\n \t\t\t\t\t\t domain);\n \telse\n@@ -5920,7 +5930,7 @@ dlb2_hw_start_domain(struct dlb2_hw *hw,\n \n \t\tr0.field.vasqid_v = 1;\n \n-\t\toffs = domain->id.phys_id * DLB2_MAX_NUM_DIR_PORTS +\n+\t\toffs = domain->id.phys_id * DLB2_MAX_NUM_DIR_PORTS(hw->ver) +\n \t\t\tdir_queue->id.phys_id;\n \n \t\tDLB2_CSR_WR(hw, DLB2_SYS_DIR_VASQID_V(offs), r0.val);\n@@ -5972,7 +5982,7 @@ int dlb2_hw_get_dir_queue_depth(struct dlb2_hw *hw,\n \n \tid = args->queue_id;\n \n-\tqueue = dlb2_get_domain_used_dir_pq(id, vdev_req, domain);\n+\tqueue = dlb2_get_domain_used_dir_pq(hw, id, vdev_req, domain);\n \tif (queue == NULL) {\n \t\tresp->status = DLB2_ST_INVALID_QID;\n \t\treturn -EINVAL;\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex cfb22efe8..f57dc1584 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -47,7 +47,7 @@ dlb2_pf_low_level_io_init(void)\n {\n \tint i;\n \t/* Addresses will be initialized at port create */\n-\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++) {\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS(DLB2_HW_V2_5); i++) {\n \t\t/* First directed ports */\n \t\tdlb2_port[i][DLB2_DIR_PORT].pp_addr = NULL;\n \t\tdlb2_port[i][DLB2_DIR_PORT].cq_base = NULL;\n@@ -628,6 +628,7 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n \t\tdlb2 = dlb2_pmd_priv(eventdev); /* rte_zmalloc_socket mem */\n+\t\tdlb2->version = DLB2_HW_DEVICE_FROM_PCI_ID(pci_dev);\n \n \t\t/* Probe the DLB2 PF layer */\n \t\tdlb2->qm_instance.pf_dev = dlb2_probe(pci_dev);\n@@ -643,7 +644,8 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\tif (pci_dev->device.devargs) {\n \t\t\tret = dlb2_parse_params(pci_dev->device.devargs->args,\n \t\t\t\t\t\tpci_dev->device.devargs->name,\n-\t\t\t\t\t\t&dlb2_args);\n+\t\t\t\t\t\t&dlb2_args,\n+\t\t\t\t\t\tdlb2->version);\n \t\t\tif (ret) {\n \t\t\t\tDLB2_LOG_ERR(\"PFPMD failed to parse args ret=%d, errno=%d\\n\",\n \t\t\t\t\t ret, rte_errno);\n@@ -655,6 +657,8 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\t\t\t\t\t event_dlb2_pf_name,\n \t\t\t\t\t\t &dlb2_args);\n \t} else {\n+\t\tdlb2 = dlb2_pmd_priv(eventdev);\n+\t\tdlb2->version = DLB2_HW_DEVICE_FROM_PCI_ID(pci_dev);\n \t\tret = dlb2_secondary_eventdev_probe(eventdev,\n \t\t\t\t\t\t event_dlb2_pf_name);\n \t}\n@@ -684,6 +688,16 @@ static const struct rte_pci_id pci_id_dlb2_map[] = {\n \t},\n };\n \n+static const struct rte_pci_id pci_id_dlb2_5_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(EVENTDEV_INTEL_VENDOR_ID,\n+\t\t\t PCI_DEVICE_ID_INTEL_DLB2_5_PF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n static int\n event_dlb2_pci_probe(struct rte_pci_driver *pci_drv,\n \t\t struct rte_pci_device *pci_dev)\n@@ -718,6 +732,40 @@ event_dlb2_pci_remove(struct rte_pci_device *pci_dev)\n \n }\n \n+static int\n+event_dlb2_5_pci_probe(struct rte_pci_driver *pci_drv,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tint ret;\n+\n+\tret = rte_event_pmd_pci_probe_named(pci_drv, pci_dev,\n+\t\t\t\t\t sizeof(struct dlb2_eventdev),\n+\t\t\t\t\t dlb2_eventdev_pci_init,\n+\t\t\t\t\t event_dlb2_pf_name);\n+\tif (ret) {\n+\t\tDLB2_LOG_INFO(\"rte_event_pmd_pci_probe_named() failed, \"\n+\t\t\t\t\"ret=%d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+event_dlb2_5_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tint ret;\n+\n+\tret = rte_event_pmd_pci_remove(pci_dev, NULL);\n+\n+\tif (ret) {\n+\t\tDLB2_LOG_INFO(\"rte_event_pmd_pci_remove() failed, \"\n+\t\t\t\t\"ret=%d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+\n+}\n+\n static struct rte_pci_driver pci_eventdev_dlb2_pmd = {\n \t.id_table = pci_id_dlb2_map,\n \t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n@@ -725,5 +773,15 @@ static struct rte_pci_driver pci_eventdev_dlb2_pmd = {\n \t.remove = event_dlb2_pci_remove,\n };\n \n+static struct rte_pci_driver pci_eventdev_dlb2_5_pmd = {\n+\t.id_table = pci_id_dlb2_5_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = event_dlb2_5_pci_probe,\n+\t.remove = event_dlb2_5_pci_remove,\n+};\n+\n RTE_PMD_REGISTER_PCI(event_dlb2_pf, pci_eventdev_dlb2_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(event_dlb2_pf, pci_id_dlb2_map);\n+\n+RTE_PMD_REGISTER_PCI(event_dlb2_5_pf, pci_eventdev_dlb2_5_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(event_dlb2_5_pf, pci_id_dlb2_5_map);\n", "prefixes": [ "v3", "01/26" ] }