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GET /api/patches/90495/?format=api
{ "id": 90495, "url": "https://patches.dpdk.org/api/patches/90495/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210402151627.1531623-14-lizh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210402151627.1531623-14-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210402151627.1531623-14-lizh@nvidia.com", "date": "2021-04-02T15:16:27", "name": "[v2,13/13] net/mlx5: allow multiple flow tables on the same level", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9d38ceb94dbca298d6425a1beb289cd35c98c9a4", "submitter": { "id": 1967, "url": "https://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210402151627.1531623-14-lizh@nvidia.com/mbox/", "series": [ { "id": 16087, "url": "https://patches.dpdk.org/api/series/16087/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16087", "date": "2021-04-02T15:16:20", "name": "Add ASO meter support in MLX5 PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/16087/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90495/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/90495/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1EF3CA0548;\n\tFri, 2 Apr 2021 17:18:13 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E26E21410E3;\n\tFri, 2 Apr 2021 17:16:52 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 4206B14109A\n for <dev@dpdk.org>; Fri, 2 Apr 2021 17:16:40 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 2 Apr 2021 18:16:35 +0300", "from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 132FGWda028272;\n Fri, 2 Apr 2021 18:16:35 +0300" ], "From": "Li Zhang <lizh@nvidia.com>", "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com, shahafs@nvidia.com", "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com", "Date": "Fri, 2 Apr 2021 18:16:27 +0300", "Message-Id": "<20210402151627.1531623-14-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20210402151627.1531623-1-lizh@nvidia.com>", "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <20210402151627.1531623-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 13/13] net/mlx5: allow multiple flow tables on\n the same level", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The driver devices support creation of multiple flow tables.\nJump action can be used in order to move the packet steering\nto different flow table.\nTable 0 is always the root table for packet steering.\n\nJumping between tables may cause endless loops in steering mechanism,\nthat's why each table has level attribute,\nthe driver sub-system may not allow jumping to table with\nequal or lower level than the current table.\n\nCurrently, in the driver, the table ID and level are always identical.\n\nAllow multiple flow table creation with the same level attribute.\n\nThis patch adds the table id in flow table data entry, while\nallocates the flow table, if the table level is same but the\ndifferent table id, the new table will be allocated with new\ntable object id. It supports 4M multiple flow tables on the\nsame level.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 9 ++--\n drivers/net/mlx5/mlx5.h | 10 ++--\n drivers/net/mlx5/mlx5_flow.c | 11 +++--\n drivers/net/mlx5/mlx5_flow.h | 10 ++--\n drivers/net/mlx5/mlx5_flow_dv.c | 83 +++++++++++++++++++--------------\n 5 files changed, 71 insertions(+), 52 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex a9f4d75dd2..8841ef0e99 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1246,9 +1246,12 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)\n \t * because DV expect to see them even if they cannot be created by\n \t * RDMA-CORE.\n \t */\n-\tif (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||\n-\t !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||\n-\t !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {\n+\tif (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,\n+\t\tNULL, 0, 1, 0, &error) ||\n+\t !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,\n+\t\tNULL, 0, 1, 0, &error) ||\n+\t !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,\n+\t\tNULL, 0, 1, 0, &error)) {\n \t\terr = ENOMEM;\n \t\tgoto error;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 5c497dfdeb..08efa5d15d 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -779,10 +779,12 @@ struct mlx5_aso_mtr_pools_mng {\n union mlx5_flow_tbl_key {\n \tstruct {\n \t\t/* Table ID should be at the lowest address. */\n-\t\tuint32_t table_id;\t/**< ID of the table. */\n-\t\tuint16_t dummy;\t\t/**< Dummy table for DV API. */\n-\t\tuint8_t domain;\t\t/**< 1 - FDB, 0 - NIC TX/RX. */\n-\t\tuint8_t direction;\t/**< 1 - egress, 0 - ingress. */\n+\t\tuint32_t level;\t/**< Level of the table. */\n+\t\tuint32_t id:22;\t/**< ID of the table. */\n+\t\tuint32_t dummy:1;\t/**< Dummy table for DV API. */\n+\t\tuint32_t is_fdb:1;\t/**< 1 - FDB, 0 - NIC TX/RX. */\n+\t\tuint32_t is_egress:1;\t/**< 1 - egress, 0 - ingress. */\n+\t\tuint32_t reserved:7;\t/**< must be zero for comparison. */\n \t};\n \tuint64_t v64;\t\t\t/**< full 64bits value of key */\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 9922731188..615fe99b69 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -5500,8 +5500,7 @@ flow_create_split_sample(struct rte_eth_dev *dev,\n \t\t\t\t\t\tstruct mlx5_flow_tbl_data_entry,\n \t\t\t\t\t\ttbl);\n \t\t\tsfx_attr.group = sfx_attr.transfer ?\n-\t\t\t\t\t\t(sfx_tbl_data->table_id - 1) :\n-\t\t\t\t\t\tsfx_tbl_data->table_id;\n+\t\t\t(sfx_tbl_data->level - 1) : sfx_tbl_data->level;\n \t\t} else {\n \t\t\tMLX5_ASSERT(attr->transfer);\n \t\t\tsfx_attr.group = jump_table;\n@@ -7754,10 +7753,12 @@ tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark)\n \tunion tunnel_offload_mark mbits = { .val = mark };\n \tunion mlx5_flow_tbl_key table_key = {\n \t\t{\n-\t\t\t.table_id = tunnel_id_to_flow_tbl(mbits.table_id),\n+\t\t\t.level = tunnel_id_to_flow_tbl(mbits.table_id),\n+\t\t\t.id = 0,\n+\t\t\t.reserved = 0,\n \t\t\t.dummy = 0,\n-\t\t\t.domain = !!mbits.transfer,\n-\t\t\t.direction = 0,\n+\t\t\t.is_fdb = !!mbits.transfer,\n+\t\t\t.is_egress = 0,\n \t\t}\n \t};\n \the = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 9e146685c2..59e9ce2c9e 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -565,8 +565,9 @@ struct mlx5_flow_tbl_data_entry {\n \tuint32_t is_egress:1; /**< Egress table. */\n \tuint32_t is_transfer:1; /**< Transfer table. */\n \tuint32_t dummy:1; /**< DR table. */\n-\tuint32_t reserve:27; /**< Reserved to future using. */\n-\tuint32_t table_id; /**< Table ID. */\n+\tuint32_t id:22; /**< Table ID. */\n+\tuint32_t reserve:5; /**< Reserved to future using. */\n+\tuint32_t level; /**< Table level. */\n };\n \n /* Sub rdma-core actions list. */\n@@ -1393,9 +1394,10 @@ int flow_dv_tbl_match_cb(struct mlx5_hlist *list,\n void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,\n \t\t\t struct mlx5_hlist_entry *entry);\n struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n-\t\tuint32_t table_id, uint8_t egress, uint8_t transfer,\n+\t\tuint32_t table_level, uint8_t egress, uint8_t transfer,\n \t\tbool external, const struct mlx5_flow_tunnel *tunnel,\n-\t\tuint32_t group_id, uint8_t dummy, struct rte_flow_error *error);\n+\t\tuint32_t group_id, uint8_t dummy,\n+\t\tuint32_t table_id, struct rte_flow_error *error);\n \n struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,\n \t\t\t\t\t uint64_t key, void *cb_ctx);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 07e381b072..9d15b597d3 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9344,20 +9344,21 @@ flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)\n \ttbl_data->group_id = tt_prm->group_id;\n \ttbl_data->external = !!tt_prm->external;\n \ttbl_data->tunnel_offload = is_tunnel_offload_active(dev);\n-\ttbl_data->is_egress = !!key.direction;\n-\ttbl_data->is_transfer = !!key.domain;\n+\ttbl_data->is_egress = !!key.is_egress;\n+\ttbl_data->is_transfer = !!key.is_fdb;\n \ttbl_data->dummy = !!key.dummy;\n-\ttbl_data->table_id = key.table_id;\n+\ttbl_data->level = key.level;\n+\ttbl_data->id = key.id;\n \ttbl = &tbl_data->tbl;\n \tif (key.dummy)\n \t\treturn &tbl_data->entry;\n-\tif (key.domain)\n+\tif (key.is_fdb)\n \t\tdomain = sh->fdb_domain;\n-\telse if (key.direction)\n+\telse if (key.is_egress)\n \t\tdomain = sh->tx_domain;\n \telse\n \t\tdomain = sh->rx_domain;\n-\tret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);\n+\tret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);\n \tif (ret) {\n \t\trte_flow_error_set(error, ENOMEM,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -9365,7 +9366,7 @@ flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)\n \t\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);\n \t\treturn NULL;\n \t}\n-\tif (key.table_id) {\n+\tif (key.level != 0) {\n \t\tret = mlx5_flow_os_create_flow_action_dest_flow_tbl\n \t\t\t\t\t(tbl->obj, &tbl_data->jump.action);\n \t\tif (ret) {\n@@ -9378,9 +9379,9 @@ flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)\n \t\t\treturn NULL;\n \t\t}\n \t}\n-\tMKSTR(matcher_name, \"%s_%s_%u_matcher_cache\",\n-\t key.domain ? \"FDB\" : \"NIC\", key.direction ? \"egress\" : \"ingress\",\n-\t key.table_id);\n+\tMKSTR(matcher_name, \"%s_%s_%u_%u_matcher_cache\",\n+\t key.is_fdb ? \"FDB\" : \"NIC\", key.is_egress ? \"egress\" : \"ingress\",\n+\t key.level, key.id);\n \tmlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,\n \t\t\t flow_dv_matcher_create_cb,\n \t\t\t flow_dv_matcher_match_cb,\n@@ -9397,10 +9398,11 @@ flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,\n \t\tcontainer_of(entry, struct mlx5_flow_tbl_data_entry, entry);\n \tunion mlx5_flow_tbl_key key = { .v64 = key64 };\n \n-\treturn tbl_data->table_id != key.table_id ||\n+\treturn tbl_data->level != key.level ||\n+\t tbl_data->id != key.id ||\n \t tbl_data->dummy != key.dummy ||\n-\t tbl_data->is_transfer != key.domain ||\n-\t tbl_data->is_egress != key.direction;\n+\t tbl_data->is_transfer != !!key.is_fdb ||\n+\t tbl_data->is_egress != !!key.is_egress;\n }\n \n /**\n@@ -9408,14 +9410,16 @@ flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,\n *\n * @param[in, out] dev\n * Pointer to rte_eth_dev structure.\n- * @param[in] table_id\n- * Table id to use.\n+ * @param[in] table_level\n+ * Table level to use.\n * @param[in] egress\n * Direction of the table.\n * @param[in] transfer\n * E-Switch or NIC flow.\n * @param[in] dummy\n * Dummy entry for dv API.\n+ * @param[in] table_id\n+ * Table id to use.\n * @param[out] error\n * pointer to error structure.\n *\n@@ -9424,20 +9428,23 @@ flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,\n */\n struct mlx5_flow_tbl_resource *\n flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n-\t\t\t uint32_t table_id, uint8_t egress,\n+\t\t\t uint32_t table_level, uint8_t egress,\n \t\t\t uint8_t transfer,\n \t\t\t bool external,\n \t\t\t const struct mlx5_flow_tunnel *tunnel,\n \t\t\t uint32_t group_id, uint8_t dummy,\n+\t\t\t uint32_t table_id,\n \t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunion mlx5_flow_tbl_key table_key = {\n \t\t{\n-\t\t\t.table_id = table_id,\n-\t\t\t.dummy = dummy,\n-\t\t\t.domain = !!transfer,\n-\t\t\t.direction = !!egress,\n+\t\t\t.level = table_level,\n+\t\t\t.id = table_id,\n+\t\t\t.reserved = 0,\n+\t\t\t.dummy = !!dummy,\n+\t\t\t.is_fdb = !!transfer,\n+\t\t\t.is_egress = !!egress,\n \t\t}\n \t};\n \tstruct mlx5_flow_tbl_tunnel_prm tt_prm = {\n@@ -9460,8 +9467,10 @@ flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n \t\t\t\t \"cannot get table\");\n \t\treturn NULL;\n \t}\n-\tDRV_LOG(DEBUG, \"Table_id %u tunnel %u group %u registered.\",\n-\t\ttable_id, tunnel ? tunnel->tunnel_id : 0, group_id);\n+\tDRV_LOG(DEBUG, \"table_level %u table_id %u \"\n+\t\t\"tunnel %u group %u registered.\",\n+\t\ttable_level, table_id,\n+\t\ttunnel ? tunnel->tunnel_id : 0, group_id);\n \ttbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);\n \treturn &tbl_data->tbl;\n }\n@@ -9488,7 +9497,7 @@ flow_dv_tbl_remove_cb(struct mlx5_hlist *list,\n \t\t\t\t\ttbl_data->tunnel->tunnel_id : 0,\n \t\t\t.group = tbl_data->group_id\n \t\t};\n-\t\tuint32_t table_id = tbl_data->table_id;\n+\t\tuint32_t table_level = tbl_data->level;\n \n \t\ttunnel_grp_hash = tbl_data->tunnel ?\n \t\t\t\t\ttbl_data->tunnel->groups :\n@@ -9497,8 +9506,9 @@ flow_dv_tbl_remove_cb(struct mlx5_hlist *list,\n \t\tif (he)\n \t\t\tmlx5_hlist_unregister(tunnel_grp_hash, he);\n \t\tDRV_LOG(DEBUG,\n-\t\t\t\"Table_id %u tunnel %u group %u released.\",\n-\t\t\ttable_id,\n+\t\t\t\"table_level %u id %u tunnel %u group %u released.\",\n+\t\t\ttable_level,\n+\t\t\ttbl_data->id,\n \t\t\ttbl_data->tunnel ?\n \t\t\ttbl_data->tunnel->tunnel_id : 0,\n \t\t\ttbl_data->group_id);\n@@ -9626,10 +9636,10 @@ flow_dv_matcher_register(struct rte_eth_dev *dev,\n \t * tunnel offload API requires this registration for cases when\n \t * tunnel match rule was inserted before tunnel set rule.\n \t */\n-\ttbl = flow_dv_tbl_resource_get(dev, key->table_id,\n-\t\t\t\t key->direction, key->domain,\n+\ttbl = flow_dv_tbl_resource_get(dev, key->level,\n+\t\t\t\t key->is_egress, key->is_fdb,\n \t\t\t\t dev_flow->external, tunnel,\n-\t\t\t\t group_id, 0, error);\n+\t\t\t\t group_id, 0, 0, error);\n \tif (!tbl)\n \t\treturn -rte_errno;\t/* No need to refill the error info */\n \ttbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);\n@@ -10108,7 +10118,7 @@ flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,\n \t\tis_egress = 1;\n \ttbl = flow_dv_tbl_resource_get(dev, next_ft_id,\n \t\t\t\t\tis_egress, is_transfer,\n-\t\t\t\t\ttrue, NULL, 0, 0, error);\n+\t\t\t\t\ttrue, NULL, 0, 0, 0, error);\n \tif (!tbl) {\n \t\trte_flow_error_set(error, ENOMEM,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -11473,7 +11483,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t attr->transfer,\n \t\t\t\t\t\t !!dev_flow->external,\n \t\t\t\t\t\t tunnel, jump_group, 0,\n-\t\t\t\t\t\t error);\n+\t\t\t\t\t\t 0, error);\n \t\t\tif (!tbl)\n \t\t\t\treturn rte_flow_error_set\n \t\t\t\t\t\t(error, errno,\n@@ -12015,9 +12025,9 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \tmatcher.priority = mlx5_get_matcher_priority(dev, attr,\n \t\t\t\t\tmatcher.priority);\n \t/* reserved field no needs to be set to 0 here. */\n-\ttbl_key.domain = attr->transfer;\n-\ttbl_key.direction = attr->egress;\n-\ttbl_key.table_id = dev_flow->dv.group;\n+\ttbl_key.is_fdb = attr->transfer;\n+\ttbl_key.is_egress = attr->egress;\n+\ttbl_key.level = dev_flow->dv.group;\n \tif (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,\n \t\t\t\t tunnel, attr->group, error))\n \t\treturn -rte_errno;\n@@ -13488,7 +13498,7 @@ flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,\n \t/* Create the meter table with METER level. */\n \tdtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,\n \t\t\t\t\t egress, transfer, false, NULL, 0,\n-\t\t\t\t\t 0, &error);\n+\t\t\t\t\t 0, 0, &error);\n \tif (!dtb->tbl) {\n \t\tDRV_LOG(ERR, \"Failed to create meter policer table.\");\n \t\treturn -1;\n@@ -13497,7 +13507,7 @@ flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,\n \tdtb->sfx_tbl = flow_dv_tbl_resource_get(dev,\n \t\t\t\t\t MLX5_FLOW_TABLE_LEVEL_SUFFIX,\n \t\t\t\t\t egress, transfer, false, NULL, 0,\n-\t\t\t\t\t 0, &error);\n+\t\t\t\t\t 0, 0, &error);\n \tif (!dtb->sfx_tbl) {\n \t\tDRV_LOG(ERR, \"Failed to create meter suffix table.\");\n \t\treturn -1;\n@@ -14020,7 +14030,8 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)\n \tvoid *flow = NULL;\n \tint ret = -1;\n \n-\ttbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);\n+\ttbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,\n+\t\t\t\t\t0, 0, 0, NULL);\n \tif (!tbl)\n \t\tgoto err;\n \tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);\n", "prefixes": [ "v2", "13/13" ] }