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{
    "id": 90424,
    "url": "https://patches.dpdk.org/api/patches/90424/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-52-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210401123817.14348-52-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-52-ndabilpuram@marvell.com",
    "date": "2021-04-01T12:38:16",
    "name": "[v3,51/52] common/cnxk: add tim irq support",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "cd97361d05824fca6a59127f6c7656a8a3114259",
    "submitter": {
        "id": 1202,
        "url": "https://patches.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-52-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 16059,
            "url": "https://patches.dpdk.org/api/series/16059/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16059",
            "date": "2021-04-01T12:37:25",
            "name": "Add Marvell CNXK common driver",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/16059/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/90424/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/90424/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        ],
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        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>",
        "Date": "Thu, 1 Apr 2021 18:08:16 +0530",
        "Message-ID": "<20210401123817.14348-52-ndabilpuram@marvell.com>",
        "X-Mailer": "git-send-email 2.8.4",
        "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>",
        "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
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        "Subject": "[dpdk-dev] [PATCH v3 51/52] common/cnxk: add tim irq support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd TIM LF IRQ register and un-register functions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/meson.build    |   1 +\n drivers/common/cnxk/roc_tim.c      |  51 ++++++++++++++++++\n drivers/common/cnxk/roc_tim_irq.c  | 104 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_tim_priv.h |   9 ++++\n 4 files changed, 165 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_tim_irq.c",
    "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 1b02178..4573d13 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -43,5 +43,6 @@ sources = files('roc_dev.c',\n \t\t'roc_sso_debug.c',\n \t\t'roc_sso_irq.c',\n \t\t'roc_tim.c',\n+\t\t'roc_tim_irq.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c\nindex 37faa37..387164b 100644\n--- a/drivers/common/cnxk/roc_tim.c\n+++ b/drivers/common/cnxk/roc_tim.c\n@@ -5,6 +5,25 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+static int\n+tim_fill_msix(struct roc_tim *roc_tim, uint16_t nb_ring)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct tim *tim = roc_tim_to_tim_priv(roc_tim);\n+\tstruct msix_offset_rsp *rsp;\n+\tint i, rc;\n+\n+\tmbox_alloc_msg_msix_offset(dev->mbox);\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < nb_ring; i++)\n+\t\ttim->tim_msix_offsets[i] = rsp->timlf_msixoff[i];\n+\n+\treturn 0;\n+}\n+\n static void\n tim_err_desc(int rc)\n {\n@@ -158,6 +177,8 @@ int\n roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct tim *tim = roc_tim_to_tim_priv(roc_tim);\n+\tstruct tim_ring_req *free_req;\n \tstruct tim_lf_alloc_req *req;\n \tstruct tim_lf_alloc_rsp *rsp;\n \tstruct dev *dev = &sso->dev;\n@@ -179,6 +200,17 @@ roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n \tif (clk)\n \t\t*clk = rsp->tenns_clk;\n \n+\trc = tim_register_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,\n+\t\t\t\t   tim->tim_msix_offsets[ring_id]);\n+\tif (rc < 0) {\n+\t\tplt_tim_dbg(\"Failed to register Ring[%d] IRQ\", ring_id);\n+\t\tfree_req = mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\t\tif (free_req == NULL)\n+\t\t\treturn -ENOSPC;\n+\t\tfree_req->ring = ring_id;\n+\t\tmbox_process(dev->mbox);\n+\t}\n+\n \treturn rc;\n }\n \n@@ -186,10 +218,14 @@ int\n roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)\n {\n \tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct tim *tim = roc_tim_to_tim_priv(roc_tim);\n \tstruct dev *dev = &sso->dev;\n \tstruct tim_ring_req *req;\n \tint rc = -ENOSPC;\n \n+\ttim_unregister_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,\n+\t\t\t\ttim->tim_msix_offsets[ring_id]);\n+\n \treq = mbox_alloc_msg_tim_lf_free(dev->mbox);\n \tif (req == NULL)\n \t\treturn rc;\n@@ -208,6 +244,7 @@ int\n roc_tim_init(struct roc_tim *roc_tim)\n {\n \tstruct rsrc_attach_req *attach_req;\n+\tstruct rsrc_detach_req *detach_req;\n \tstruct free_rsrcs_rsp *free_rsrc;\n \tstruct dev *dev;\n \tuint16_t nb_lfs;\n@@ -245,6 +282,20 @@ roc_tim_init(struct roc_tim *roc_tim)\n \t\treturn 0;\n \t}\n \n+\trc = tim_fill_msix(roc_tim, nb_lfs);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to get TIM MSIX vectors\");\n+\n+\t\tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n+\t\tif (detach_req == NULL)\n+\t\t\treturn -ENOSPC;\n+\t\tdetach_req->partial = true;\n+\t\tdetach_req->timlfs = true;\n+\t\tmbox_process(dev->mbox);\n+\n+\t\treturn 0;\n+\t}\n+\n \treturn nb_lfs;\n }\n \ndiff --git a/drivers/common/cnxk/roc_tim_irq.c b/drivers/common/cnxk/roc_tim_irq.c\nnew file mode 100644\nindex 0000000..7bd3e76\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_tim_irq.c\n@@ -0,0 +1,104 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+tim_lf_irq(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint64_t intr;\n+\tuint8_t ring;\n+\n+\tring = (base >> 12) & 0xFF;\n+\n+\tintr = plt_read64(base + TIM_LF_NRSPERR_INT);\n+\tplt_err(\"TIM RING %d TIM_LF_NRSPERR_INT=0x%\" PRIx64 \"\", ring, intr);\n+\tintr = plt_read64(base + TIM_LF_RAS_INT);\n+\tplt_err(\"TIM RING %d TIM_LF_RAS_INT=0x%\" PRIx64 \"\", ring, intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, base + TIM_LF_NRSPERR_INT);\n+\tplt_write64(intr, base + TIM_LF_RAS_INT);\n+}\n+\n+static int\n+tim_lf_register_irq(uintptr_t base, struct plt_intr_handle *handle,\n+\t\t    uint16_t msix_offset)\n+{\n+\tunsigned int vec;\n+\tint rc;\n+\n+\tvec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_NRSPERR_INT);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);\n+\n+\tvec = msix_offset + TIM_LF_INT_VEC_RAS_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_RAS_INT);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+int\n+tim_register_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,\n+\t\t      uint8_t ring_id, uint16_t msix_offset)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tuintptr_t base;\n+\n+\tif (msix_offset == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid MSIX offset for TIM LF %d\", ring_id);\n+\t\treturn TIM_ERR_PARAM;\n+\t}\n+\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n+\treturn tim_lf_register_irq(base, handle, msix_offset);\n+}\n+\n+static void\n+tim_lf_unregister_irq(uintptr_t base, struct plt_intr_handle *handle,\n+\t\t      uint16_t msix_offset)\n+{\n+\tunsigned int vec;\n+\n+\tvec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);\n+\tdev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);\n+\n+\tvec = msix_offset + TIM_LF_INT_VEC_RAS_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);\n+\tdev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);\n+}\n+\n+void\n+tim_unregister_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,\n+\t\t\tuint8_t ring_id, uint16_t msix_offset)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tuintptr_t base;\n+\n+\tif (msix_offset == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid MSIX offset for TIM LF %d\", ring_id);\n+\t\treturn;\n+\t}\n+\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n+\ttim_lf_unregister_irq(base, handle, msix_offset);\n+}\ndiff --git a/drivers/common/cnxk/roc_tim_priv.h b/drivers/common/cnxk/roc_tim_priv.h\nindex 08697f6..cc083d2 100644\n--- a/drivers/common/cnxk/roc_tim_priv.h\n+++ b/drivers/common/cnxk/roc_tim_priv.h\n@@ -6,6 +6,7 @@\n #define _ROC_TIM_PRIV_H_\n \n struct tim {\n+\tuint16_t tim_msix_offsets[MAX_RVU_BLKLF_CNT];\n };\n \n enum tim_err_status {\n@@ -18,4 +19,12 @@ roc_tim_to_tim_priv(struct roc_tim *roc_tim)\n \treturn (struct tim *)&roc_tim->reserved[0];\n }\n \n+/* TIM IRQ*/\n+int tim_register_irq_priv(struct roc_tim *roc_tim,\n+\t\t\t  struct plt_intr_handle *handle, uint8_t ring_id,\n+\t\t\t  uint16_t msix_offset);\n+void tim_unregister_irq_priv(struct roc_tim *roc_tim,\n+\t\t\t     struct plt_intr_handle *handle, uint8_t ring_id,\n+\t\t\t     uint16_t msix_offset);\n+\n #endif /* _ROC_TIM_PRIV_H_ */\n",
    "prefixes": [
        "v3",
        "51/52"
    ]
}