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GET /api/patches/90387/?format=api
{ "id": 90387, "url": "https://patches.dpdk.org/api/patches/90387/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-15-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-15-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-15-ndabilpuram@marvell.com", "date": "2021-04-01T12:37:39", "name": "[v3,14/52] common/cnxk: add npa performance counter support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "70b7ae321605cc9850be2ffe0d6a9ad22c9d1f03", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-15-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "https://patches.dpdk.org/api/series/16059/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16059/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90387/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90387/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4D0D8A0548;\n\tThu, 1 Apr 2021 14:41:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A026A1411CB;\n\tThu, 1 Apr 2021 14:39:21 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id BD3CB1411FA\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:39:19 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CPLcT019084 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:39:19 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje1p-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:39:19 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:39:17 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:39:17 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B76FA3F7048;\n Thu, 1 Apr 2021 05:39:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=P7LRmI0yLEosk6T8ylKMtUDq+5SWALp6NoShf6yiOVM=;\n b=YuDAmBeftc9vgBggfqAkpvEaz6ubwhlpFtNBvxIA8HXLBotPH1O9FYmdO6riuZsK7600\n a5oMVSM9OT1c+sW+MfNQdRORXSp+8Gp1Ri4QsxgWMwPCROP/ZgLbmwS+grxBs6c7ICVo\n Kglnb/uszl5/CcJ/o4W6lt+vi8zykncXIrkjR2MnZSnDLgNNt3Hmwxh1hUW0hhnVukRy\n 1MxeM44tWIvDJltCwSPG5ptC8RkDiI9sSLeCT3LVBPnFxPeltRU1+EvqJjMVCgNaTbYw\n H3t0cVfW5rzTTMepvr4zAYEfpYe5jNzC8b5y+zmcxbeJZsXvStwQysfikR5MGhDXhmKD pQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 18:07:39 +0530", "Message-ID": "<20210401123817.14348-15-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "XA8vtMcm1NDcYHp-fi1ByKiW0FjS0Jll", "X-Proofpoint-ORIG-GUID": "XA8vtMcm1NDcYHp-fi1ByKiW0FjS0Jll", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 14/52] common/cnxk: add npa performance\n counter support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ashwin Sekhar T K <asekhar@marvell.com>\n\nAdd APIs to read NPA performance counters.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_npa.c | 50 +++++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_npa.h | 37 ++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 3 files changed, 88 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 80f5a78..f1e03b7 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -131,6 +131,56 @@ npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)\n \treturn 0;\n }\n \n+int\n+roc_npa_pool_op_pc_reset(uint64_t aura_handle)\n+{\n+\tstruct npa_lf *lf = idev_npa_obj_get();\n+\tstruct npa_aq_enq_req *pool_req;\n+\tstruct npa_aq_enq_rsp *pool_rsp;\n+\tstruct ndc_sync_op *ndc_req;\n+\tstruct mbox_dev *mdev;\n+\tint rc = -ENOSPC, off;\n+\tstruct mbox *mbox;\n+\n+\tif (lf == NULL)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tmbox = lf->mbox;\n+\tmdev = &mbox->dev[0];\n+\tplt_npa_dbg(\"lf=%p aura_handle=0x%\" PRIx64, lf, aura_handle);\n+\n+\tpool_req = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (pool_req == NULL)\n+\t\treturn rc;\n+\tpool_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n+\tpool_req->ctype = NPA_AQ_CTYPE_POOL;\n+\tpool_req->op = NPA_AQ_INSTOP_WRITE;\n+\tpool_req->pool.op_pc = 0;\n+\tpool_req->pool_mask.op_pc = ~pool_req->pool_mask.op_pc;\n+\n+\trc = mbox_process(mbox);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\toff = mbox->rx_start +\n+\t PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tpool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n+\n+\tif (pool_rsp->hdr.rc != 0)\n+\t\treturn NPA_ERR_AURA_POOL_FINI;\n+\n+\t/* Sync NDC-NPA for LF */\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n+\tif (ndc_req == NULL)\n+\t\treturn -ENOSPC;\n+\tndc_req->npa_lf_sync = 1;\n+\trc = mbox_process(mbox);\n+\tif (rc) {\n+\t\tplt_err(\"Error on NDC-NPA LF sync, rc %d\", rc);\n+\t\treturn NPA_ERR_AURA_POOL_FINI;\n+\t}\n+\treturn 0;\n+}\n static inline char *\n npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)\n {\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex b829b23..7c6f78d 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -146,6 +146,40 @@ roc_npa_aura_op_available(uint64_t aura_handle)\n \t\treturn reg & 0xFFFFFFFFF;\n }\n \n+static inline uint64_t\n+roc_npa_pool_op_performance_counter(uint64_t aura_handle, const int drop)\n+{\n+\tunion {\n+\t\tuint64_t u;\n+\t\tstruct npa_aura_op_wdata_s s;\n+\t} op_wdata;\n+\tint64_t *addr;\n+\tuint64_t reg;\n+\n+\top_wdata.u = 0;\n+\top_wdata.s.aura = roc_npa_aura_handle_to_aura(aura_handle);\n+\tif (drop)\n+\t\top_wdata.s.drop |= BIT_ULL(63); /* DROP */\n+\n+\taddr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +\n+\t\t\t NPA_LF_POOL_OP_PC);\n+\n+\treg = roc_atomic64_add_nosync(op_wdata.u, addr);\n+\t/*\n+\t * NPA_LF_POOL_OP_PC Read Data\n+\t *\n+\t * 63 49 48 48 47 0\n+\t * -----------------------------\n+\t * | Reserved | OP_ERR | OP_PC |\n+\t * -----------------------------\n+\t */\n+\n+\tif (reg & BIT_ULL(48) /* OP_ERR */)\n+\t\treturn 0;\n+\telse\n+\t\treturn reg & 0xFFFFFFFFFFFF;\n+}\n+\n static inline void\n roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf,\n \t\t\t unsigned int num, const int fabs)\n@@ -396,4 +430,7 @@ void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle,\n int __roc_api roc_npa_ctx_dump(void);\n int __roc_api roc_npa_dump(void);\n \n+/* Reset operation performance counter. */\n+int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);\n+\n #endif /* _ROC_NPA_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex e2c0de9..78e9686 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -19,6 +19,7 @@ INTERNAL {\n \troc_npa_dump;\n \troc_npa_pool_create;\n \troc_npa_pool_destroy;\n+\troc_npa_pool_op_pc_reset;\n \troc_npa_pool_range_update_check;\n \troc_plt_init;\n \n", "prefixes": [ "v3", "14/52" ] }