Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/90383/?format=api
{ "id": 90383, "url": "https://patches.dpdk.org/api/patches/90383/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-11-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-11-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-11-ndabilpuram@marvell.com", "date": "2021-04-01T12:37:35", "name": "[v3,10/52] common/cnxk: add npa irq support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "ba75c7fd7aca096848b381ff07a8971a1e57418a", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-11-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "https://patches.dpdk.org/api/series/16059/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16059/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90383/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90383/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7037AA0548;\n\tThu, 1 Apr 2021 14:40:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 265C1141102;\n\tThu, 1 Apr 2021 14:39:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 244E2141088\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:39:08 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CPLXZ019083 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:39:07 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje14-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:39:07 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:39:05 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:39:05 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 08EEA3F7041;\n Thu, 1 Apr 2021 05:39:02 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=4X8D6sJsboTM3z5qMYEZl8aWJzf0dQZkRAPI69HsYnA=;\n b=HpAwxJArE10rADniIcGNQsn7fZI4vbY6fnoAUuqdwAPEzursMQZ/wVJH3Cmn5dml4Pnl\n rCHeXrA2uVyTYfpMPyeC0yk6y2OP5clrbRpUDNvdTIeDMHKtcKkG0oqhCNQ9LrQs3dlA\n 2Su7IT1hkHfb6XGCowBbfyMM4BdX3MK+808DqC5bBjXOb5gYrZKEgMG0jh5KFVIAD8kl\n gVxewflUa+IhvFK+vobJjFP6ftWMVtuSBM/UAIpxg/lU493vrSteWIg8zsfVg3GaJkHs\n eZ9v1ePjn4jqIjEfzRkUuUb2kizsJcMjUGEy4oO3BjF/PBXdlP+Ga3nlUWO24eX/JJku Tg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 18:07:35 +0530", "Message-ID": "<20210401123817.14348-11-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "hANXNU92l5mrVCd_qGSADyv8mPzUJsCp", "X-Proofpoint-ORIG-GUID": "hANXNU92l5mrVCd_qGSADyv8mPzUJsCp", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 10/52] common/cnxk: add npa irq support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ashwin Sekhar T K <asekhar@marvell.com>\n\nAdd support for NPA IRQs.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_npa.c | 7 +\n drivers/common/cnxk/roc_npa_irq.c | 297 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_npa_priv.h | 4 +\n 4 files changed, 309 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_npa_irq.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 2aeed3e..f8b777a 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -16,6 +16,7 @@ sources = files('roc_dev.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n \t\t'roc_npa.c',\n+\t\t'roc_npa_irq.c',\n \t\t'roc_platform.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 2aa726b..0d4a56a 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -242,11 +242,17 @@ npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev)\n \tidev->npa = lf;\n \tplt_wmb();\n \n+\trc = npa_register_irqs(lf);\n+\tif (rc)\n+\t\tgoto npa_fini;\n+\n \tplt_npa_dbg(\"npa=%p max_pools=%d pf_func=0x%x msix=0x%x\", lf,\n \t\t roc_idev_npa_maxpools_get(), lf->pf_func, npa_msixoff);\n \n \treturn 0;\n \n+npa_fini:\n+\tnpa_dev_fini(idev->npa);\n npa_detach:\n \tnpa_detach(dev->mbox);\n fail:\n@@ -268,6 +274,7 @@ npa_lf_fini(void)\n \tif (__atomic_sub_fetch(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST) != 0)\n \t\treturn 0;\n \n+\tnpa_unregister_irqs(idev->npa);\n \trc |= npa_dev_fini(idev->npa);\n \trc |= npa_detach(idev->npa->mbox);\n \tidev_set_defaults(idev);\ndiff --git a/drivers/common/cnxk/roc_npa_irq.c b/drivers/common/cnxk/roc_npa_irq.c\nnew file mode 100644\nindex 0000000..2d1e535\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npa_irq.c\n@@ -0,0 +1,297 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+npa_err_irq(void *param)\n+{\n+\tstruct npa_lf *lf = (struct npa_lf *)param;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(lf->base + NPA_LF_ERR_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Err_intr=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, lf->base + NPA_LF_ERR_INT);\n+}\n+\n+static int\n+npa_register_err_irq(struct npa_lf *lf)\n+{\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n+\t/* Register err interrupt vector */\n+\trc = dev_irq_register(handle, npa_err_irq, lf, vec);\n+\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_unregister_err_irq(struct npa_lf *lf)\n+{\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\tint vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n+\tdev_irq_unregister(handle, npa_err_irq, lf, vec);\n+}\n+\n+static void\n+npa_ras_irq(void *param)\n+{\n+\tstruct npa_lf *lf = (struct npa_lf *)param;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(lf->base + NPA_LF_RAS);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Ras_intr=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, lf->base + NPA_LF_RAS);\n+}\n+\n+static int\n+npa_register_ras_irq(struct npa_lf *lf)\n+{\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, npa_ras_irq, lf, vec);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_unregister_ras_irq(struct npa_lf *lf)\n+{\n+\tint vec;\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n+\tdev_irq_unregister(handle, npa_ras_irq, lf, vec);\n+}\n+\n+static inline uint8_t\n+npa_q_irq_get_and_clear(struct npa_lf *lf, uint32_t q, uint32_t off,\n+\t\t\tuint64_t mask)\n+{\n+\tuint64_t reg, wdata;\n+\tuint8_t qint;\n+\n+\twdata = (uint64_t)q << 44;\n+\treg = roc_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\tplt_err(\"Failed execute irq get off=0x%x\", off);\n+\t\treturn 0;\n+\t}\n+\n+\tqint = reg & 0xff;\n+\twdata &= mask;\n+\tplt_write64(wdata | qint, lf->base + off);\n+\n+\treturn qint;\n+}\n+\n+static inline uint8_t\n+npa_pool_irq_get_and_clear(struct npa_lf *lf, uint32_t p)\n+{\n+\treturn npa_q_irq_get_and_clear(lf, p, NPA_LF_POOL_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+npa_aura_irq_get_and_clear(struct npa_lf *lf, uint32_t a)\n+{\n+\treturn npa_q_irq_get_and_clear(lf, a, NPA_LF_AURA_OP_INT, ~0xff00);\n+}\n+\n+static void\n+npa_q_irq(void *param)\n+{\n+\tstruct npa_qint *qint = (struct npa_qint *)param;\n+\tstruct npa_lf *lf = qint->lf;\n+\tuint8_t irq, qintx = qint->qintx;\n+\tuint32_t q, pool, aura;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(lf->base + NPA_LF_QINTX_INT(qintx));\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"queue_intr=0x%\" PRIx64 \" qintx=%d\", intr, qintx);\n+\n+\t/* Handle pool queue interrupts */\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\t\t/* Skip disabled POOL */\n+\t\tif (plt_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\tpool = q % lf->qints;\n+\t\tirq = npa_pool_irq_get_and_clear(lf, pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS))\n+\t\t\tplt_err(\"Pool=%d NPA_POOL_ERR_INT_OVFLS\", pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE))\n+\t\t\tplt_err(\"Pool=%d NPA_POOL_ERR_INT_RANGE\", pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR))\n+\t\t\tplt_err(\"Pool=%d NPA_POOL_ERR_INT_PERR\", pool);\n+\t}\n+\n+\t/* Handle aura queue interrupts */\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\t\t/* Skip disabled AURA */\n+\t\tif (plt_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\taura = q % lf->qints;\n+\t\tirq = npa_aura_irq_get_and_clear(lf, aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER))\n+\t\t\tplt_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_OVER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER))\n+\t\t\tplt_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_UNDER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER))\n+\t\t\tplt_err(\"Aura=%d NPA_AURA_ERR_INT_FREE_UNDER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS))\n+\t\t\tplt_err(\"Aura=%d NPA_AURA_ERR_POOL_DIS\", aura);\n+\t}\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx));\n+}\n+\n+static int\n+npa_register_queue_irqs(struct npa_lf *lf)\n+{\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\tint vec, q, qs, rc = 0;\n+\n+\t/* Figure out max qintx required */\n+\tqs = PLT_MIN(lf->qints, lf->nr_pools);\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\tplt_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n+\n+\t\tstruct npa_qint *qintmem = lf->npa_qint_mem;\n+\n+\t\tqintmem += q;\n+\n+\t\tqintmem->lf = lf;\n+\t\tqintmem->qintx = q;\n+\n+\t\t/* Sync qints_mem update */\n+\t\tplt_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = dev_irq_register(handle, npa_q_irq, qintmem, vec);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\n+\t\tplt_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n+\t\t/* Enable QINT interrupt */\n+\t\tplt_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1S(q));\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_unregister_queue_irqs(struct npa_lf *lf)\n+{\n+\tstruct plt_intr_handle *handle = lf->intr_handle;\n+\tint vec, q, qs;\n+\n+\t/* Figure out max qintx required */\n+\tqs = PLT_MIN(lf->qints, lf->nr_pools);\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\tplt_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n+\n+\t\tstruct npa_qint *qintmem = lf->npa_qint_mem;\n+\n+\t\tqintmem += q;\n+\n+\t\t/* Unregister queue irq vector */\n+\t\tdev_irq_unregister(handle, npa_q_irq, qintmem, vec);\n+\n+\t\tqintmem->lf = NULL;\n+\t\tqintmem->qintx = 0;\n+\t}\n+}\n+\n+int\n+npa_register_irqs(struct npa_lf *lf)\n+{\n+\tint rc;\n+\n+\tif (lf->npa_msixoff == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid NPALF MSIX vector offset vector: 0x%x\",\n+\t\t\tlf->npa_msixoff);\n+\t\treturn NPA_ERR_PARAM;\n+\t}\n+\n+\t/* Register lf err interrupt */\n+\trc = npa_register_err_irq(lf);\n+\t/* Register RAS interrupt */\n+\trc |= npa_register_ras_irq(lf);\n+\t/* Register queue interrupts */\n+\trc |= npa_register_queue_irqs(lf);\n+\n+\treturn rc;\n+}\n+\n+void\n+npa_unregister_irqs(struct npa_lf *lf)\n+{\n+\tnpa_unregister_err_irq(lf);\n+\tnpa_unregister_ras_irq(lf);\n+\tnpa_unregister_queue_irqs(lf);\n+}\ndiff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h\nindex dd6981f..5a02a61 100644\n--- a/drivers/common/cnxk/roc_npa_priv.h\n+++ b/drivers/common/cnxk/roc_npa_priv.h\n@@ -56,4 +56,8 @@ roc_npa_to_npa_priv(struct roc_npa *roc_npa)\n int npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev);\n int npa_lf_fini(void);\n \n+/* IRQ */\n+int npa_register_irqs(struct npa_lf *lf);\n+void npa_unregister_irqs(struct npa_lf *lf);\n+\n #endif /* _ROC_NPA_PRIV_H_ */\n", "prefixes": [ "v3", "10/52" ] }