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GET /api/patches/90335/?format=api
{ "id": 90335, "url": "https://patches.dpdk.org/api/patches/90335/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-47-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401094739.22714-47-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401094739.22714-47-ndabilpuram@marvell.com", "date": "2021-04-01T09:47:33", "name": "[v2,46/52] common/cnxk: add sso hws interface", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aa0d55c191f0bccf23b67e98b1ae9880c60c9be7", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-47-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16050, "url": "https://patches.dpdk.org/api/series/16050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16050", "date": "2021-04-01T09:46:47", "name": "Add Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/16050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90335/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/90335/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 235C8A0548;\n\tThu, 1 Apr 2021 11:54:13 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4E34114104A;\n\tThu, 1 Apr 2021 11:50:29 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 39F5214104A\n for <dev@dpdk.org>; Thu, 1 Apr 2021 11:50:27 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1319fTu5015004 for <dev@dpdk.org>; Thu, 1 Apr 2021 02:50:26 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 37n28j1x20-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 02:50:26 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 02:50:24 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 02:50:24 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 669783F7050;\n Thu, 1 Apr 2021 02:50:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=6XwI69tg8Eu8RYo/5BF95YMljkLs25xYtBJ8VBmKgJc=;\n b=gUfFWSFaoic+W3ahR9+cbkTfKlnjsrFXSWYQrb1cUgynp3p+MfvyCmD0uosEYYDh2vn5\n 9ZVwf/lea2P96wvyLLFuy61MBrRBMeJo20V5D2OKENTyMNWkvkRY+sGTZkd0WzkTzqCs\n UVLqpEvsKxNh1lUn3N+DHlAIA3QXrlyvFwXdqeqxNgmFpZbuQH6xmOAm1RTAUz1dRDjj\n PM5jJjeC1Y2V0YmLO8yafSSj1pgZfCmA06FKKW9Dy8fyL6hAZl1es5pbhpDrQKJiGp9J\n FsqQEXWFKmaxRWQ4iD47J+firPUXljgu5DEhvb+K2XVUJOb0rifRvZXtrBxi9EcxqDBH /Q==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 15:17:33 +0530", "Message-ID": "<20210401094739.22714-47-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401094739.22714-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401094739.22714-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "fIzuQV3Wy_kq-Ubj8noxcYV4O8vDpku8", "X-Proofpoint-GUID": "fIzuQV3Wy_kq-Ubj8noxcYV4O8vDpku8", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_04:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 46/52] common/cnxk: add sso hws interface", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO HWS interface for setting/unsetting links, retrieving\nbase address and nanoseconds to getwork timeout.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/roc_sso.c | 128 ++++++++++++++++++++++++++++++++++++-\n drivers/common/cnxk/roc_sso.h | 6 ++\n drivers/common/cnxk/roc_sso_priv.h | 3 +\n drivers/common/cnxk/version.map | 4 ++\n 4 files changed, 140 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex 6875b08..ba9dc3b 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -152,6 +152,104 @@ sso_rsrc_get(struct roc_sso *roc_sso)\n \treturn 0;\n }\n \n+static void\n+sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n+\t\t uint16_t hwgrp[], uint16_t n, uint16_t enable)\n+{\n+\tuint64_t reg;\n+\tint i, j, k;\n+\n+\ti = 0;\n+\twhile (n) {\n+\t\tuint64_t mask[4] = {\n+\t\t\t0x8000,\n+\t\t\t0x8000,\n+\t\t\t0x8000,\n+\t\t\t0x8000,\n+\t\t};\n+\n+\t\tk = n % 4;\n+\t\tk = k ? k : 4;\n+\t\tfor (j = 0; j < k; j++) {\n+\t\t\tmask[j] = hwgrp[i + j] | enable << 14;\n+\t\t\tenable ? plt_bitmap_set(bmp, hwgrp[i + j]) :\n+\t\t\t\t plt_bitmap_clear(bmp, hwgrp[i + j]);\n+\t\t\tplt_sso_dbg(\"HWS %d Linked to HWGRP %d\", hws,\n+\t\t\t\t hwgrp[i + j]);\n+\t\t}\n+\n+\t\tn -= j;\n+\t\ti += j;\n+\t\treg = mask[0] | mask[1] << 16 | mask[2] << 32 | mask[3] << 48;\n+\t\tplt_write64(reg, base + SSOW_LF_GWS_GRPMSK_CHG);\n+\t}\n+}\n+\n+/* Public Functions. */\n+uintptr_t\n+roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n+}\n+\n+uint64_t\n+roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tuint64_t current_us, current_ns, new_ns;\n+\tuintptr_t base;\n+\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20);\n+\tcurrent_us = plt_read64(base + SSOW_LF_GWS_NW_TIM);\n+\t/* From HRM, table 14-19:\n+\t * The SSOW_LF_GWS_NW_TIM[NW_TIM] period is specified in n-1 notation.\n+\t */\n+\tcurrent_us += 1;\n+\n+\t/* From HRM, table 14-1:\n+\t * SSOW_LF_GWS_NW_TIM[NW_TIM] specifies the minimum timeout. The SSO\n+\t * hardware times out a GET_WORK request within 2 usec of the minimum\n+\t * timeout specified by SSOW_LF_GWS_NW_TIM[NW_TIM].\n+\t */\n+\tcurrent_us += 2;\n+\tcurrent_ns = current_us * 1E3;\n+\tnew_ns = (ns - PLT_MIN(ns, current_ns));\n+\tnew_ns = !new_ns ? 1 : new_ns;\n+\treturn (new_ns * plt_tsc_hz()) / 1E9;\n+}\n+\n+int\n+roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n+\t\t uint16_t nb_hwgrp)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso;\n+\tuintptr_t base;\n+\n+\tsso = roc_sso_to_sso_priv(roc_sso);\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n+\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, 1);\n+\n+\treturn nb_hwgrp;\n+}\n+\n+int\n+roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n+\t\t uint16_t nb_hwgrp)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso;\n+\tuintptr_t base;\n+\n+\tsso = roc_sso_to_sso_priv(roc_sso);\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n+\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, 0);\n+\n+\treturn nb_hwgrp;\n+}\n+\n int\n roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n {\n@@ -225,8 +323,10 @@ int\n roc_sso_dev_init(struct roc_sso *roc_sso)\n {\n \tstruct plt_pci_device *pci_dev;\n+\tuint32_t link_map_sz;\n \tstruct sso *sso;\n-\tint rc;\n+\tvoid *link_mem;\n+\tint i, rc;\n \n \tif (roc_sso == NULL || roc_sso->pci_dev == NULL)\n \t\treturn SSO_ERR_PARAM;\n@@ -249,12 +349,38 @@ roc_sso_dev_init(struct roc_sso *roc_sso)\n \t}\n \trc = -ENOMEM;\n \n+\tsso->link_map =\n+\t\tplt_zmalloc(sizeof(struct plt_bitmap *) * roc_sso->max_hws, 0);\n+\tif (sso->link_map == NULL) {\n+\t\tplt_err(\"Failed to allocate memory for link_map array\");\n+\t\tgoto rsrc_fail;\n+\t}\n+\n+\tlink_map_sz = plt_bitmap_get_memory_footprint(roc_sso->max_hwgrp);\n+\tsso->link_map_mem = plt_zmalloc(link_map_sz * roc_sso->max_hws, 0);\n+\tif (sso->link_map_mem == NULL) {\n+\t\tplt_err(\"Failed to get link_map memory\");\n+\t\tgoto rsrc_fail;\n+\t}\n+\n+\tlink_mem = sso->link_map_mem;\n+\tfor (i = 0; i < roc_sso->max_hws; i++) {\n+\t\tsso->link_map[i] = plt_bitmap_init(roc_sso->max_hwgrp, link_mem,\n+\t\t\t\t\t\t link_map_sz);\n+\t\tif (sso->link_map[i] == NULL) {\n+\t\t\tplt_err(\"Failed to allocate link map\");\n+\t\t\tgoto link_mem_free;\n+\t\t}\n+\t\tlink_mem = PLT_PTR_ADD(link_mem, link_map_sz);\n+\t}\n \tidev_sso_pffunc_set(sso->dev.pf_func);\n \tsso->pci_dev = pci_dev;\n \tsso->dev.drv_inited = true;\n \troc_sso->lmt_base = sso->dev.lmt_base;\n \n \treturn 0;\n+link_mem_free:\n+\tplt_free(sso->link_map_mem);\n rsrc_fail:\n \trc |= dev_fini(&sso->dev, pci_dev);\n fail:\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex 4f37f14..7236045 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -30,5 +30,11 @@ int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso);\n int __roc_api roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws,\n \t\t\t\tuint16_t nb_hwgrp);\n void __roc_api roc_sso_rsrc_fini(struct roc_sso *roc_sso);\n+uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns);\n+int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws,\n+\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n+int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws,\n+\t\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n+uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws);\n \n #endif /* _ROC_SSOW_H_ */\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex 1ab3f5b..ad35be1 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -13,6 +13,9 @@ struct sso_rsrc {\n struct sso {\n \tstruct plt_pci_device *pci_dev;\n \tstruct dev dev;\n+\t/* SSO link mapping. */\n+\tstruct plt_bitmap **link_map;\n+\tvoid *link_map_mem;\n } __plt_cache_aligned;\n \n enum sso_err_status {\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex aabe344..2656e11 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -176,6 +176,10 @@ INTERNAL {\n \troc_plt_init;\n \troc_sso_dev_fini;\n \troc_sso_dev_init;\n+\troc_sso_hws_base_get;\n+\troc_sso_hws_link;\n+\troc_sso_hws_unlink;\n+\troc_sso_ns_to_gw;\n \troc_sso_rsrc_fini;\n \troc_sso_rsrc_init;\n \n", "prefixes": [ "v2", "46/52" ] }