Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/90316/?format=api
{ "id": 90316, "url": "https://patches.dpdk.org/api/patches/90316/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-28-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401094739.22714-28-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401094739.22714-28-ndabilpuram@marvell.com", "date": "2021-04-01T09:47:14", "name": "[v2,27/52] common/cnxk: add support for nix extended stats", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dd0051c2b4d4ccb3ef6ec114816348a314e8f33f", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-28-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16050, "url": "https://patches.dpdk.org/api/series/16050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16050", "date": "2021-04-01T09:46:47", "name": "Add Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/16050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90316/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/90316/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7F2C3A0548;\n\tThu, 1 Apr 2021 11:51:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 78249140E66;\n\tThu, 1 Apr 2021 11:49:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 00E81140FA4\n for <dev@dpdk.org>; Thu, 1 Apr 2021 11:49:28 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1319fTtr015004 for <dev@dpdk.org>; Thu, 1 Apr 2021 02:49:28 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 37n28j1wxe-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 02:49:28 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 02:49:26 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 02:49:26 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 3BD043F703F;\n Thu, 1 Apr 2021 02:49:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=OW17KLJJpKSbXyElPQA7qvIy2j6vcNmOW+xND8OsbbY=;\n b=B5bpvuJmVsGbOl5g1wj8wxBCdFpuJUPCvDZ9eWilHkUKYjx8QrZFmnvExjNV/JrwvNwb\n jr4RK5r81nsPrVX00J9MfgZNdp9+T88LqXa7Jy+YD0fzyvnLm/pPAG8WDdSEonRBfaX6\n HwA30YUraZfRl18ueYWuuhXsDuj1jY2YPJcgaLBQx00zRWU/0g6CnRySO7hPv3eStQwr\n jkGGYyxiG0ewHcM8EnTC3GRS26oGms8Soc9bEvWZxcv5SMSVXC2/dXAGWLe+wYbR8sCU\n KhC1LPdCvcj/DdSwWN+drAux3AoiL9lpv0poBUfiGvnugtpmpSHYufad8rucFgQxOywr 2g==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 15:17:14 +0530", "Message-ID": "<20210401094739.22714-28-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401094739.22714-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401094739.22714-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "aHnVSMECWNdO1G70jloHwXN8UhdC4vwb", "X-Proofpoint-GUID": "aHnVSMECWNdO1G70jloHwXN8UhdC4vwb", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_04:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 27/52] common/cnxk: add support for nix\n extended stats", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nAdd support for retrieving NIX extended stats that are\nper NIX LF and per LMAC.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 18 ++++\n drivers/common/cnxk/roc_nix_stats.c | 172 +++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_xstats.h | 204 +++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 3 +\n 4 files changed, 397 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_xstats.h", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 45aca83..137889a 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -158,6 +158,18 @@ struct roc_nix_link_info {\n \tuint64_t port : 8;\n };\n \n+/** Maximum name length for extended statistics counters */\n+#define ROC_NIX_XSTATS_NAME_SIZE 64\n+\n+struct roc_nix_xstat {\n+\tuint64_t id;\t/**< The index in xstats name array. */\n+\tuint64_t value; /**< The statistic counter value. */\n+};\n+\n+struct roc_nix_xstat_name {\n+\tchar name[ROC_NIX_XSTATS_NAME_SIZE];\n+};\n+\n struct roc_nix_ipsec_cfg {\n \tuint32_t sa_size;\n \tuint32_t tag_const;\n@@ -289,6 +301,12 @@ int __roc_api roc_nix_stats_queue_get(struct roc_nix *roc_nix, uint16_t qid,\n \t\t\t\t struct roc_nix_stats_queue *qstats);\n int __roc_api roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid,\n \t\t\t\t\tbool is_rx);\n+int __roc_api roc_nix_num_xstats_get(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_xstats_get(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_xstat *xstats, unsigned int n);\n+int __roc_api roc_nix_xstats_names_get(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_xstat_name *xstats_names,\n+\t\t\t\t unsigned int limit);\n \n /* Queue */\n int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\ndiff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c\nindex e0a776a..631677b 100644\n--- a/drivers/common/cnxk/roc_nix_stats.c\n+++ b/drivers/common/cnxk/roc_nix_stats.c\n@@ -5,12 +5,24 @@\n #include <inttypes.h>\n \n #include \"roc_api.h\"\n+#include \"roc_nix_xstats.h\"\n #include \"roc_priv.h\"\n \n #define NIX_RX_STATS(val) plt_read64(nix->base + NIX_LF_RX_STATX(val))\n #define NIX_TX_STATS(val) plt_read64(nix->base + NIX_LF_TX_STATX(val))\n \n int\n+roc_nix_num_xstats_get(struct roc_nix *roc_nix)\n+{\n+\tif (roc_nix_is_vf_or_sdp(roc_nix))\n+\t\treturn CNXK_NIX_NUM_XSTATS_REG;\n+\telse if (roc_model_is_cn9k())\n+\t\treturn CNXK_NIX_NUM_XSTATS_CGX;\n+\n+\treturn CNXK_NIX_NUM_XSTATS_RPM;\n+}\n+\n+int\n roc_nix_stats_get(struct roc_nix *roc_nix, struct roc_nix_stats *stats)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n@@ -237,3 +249,163 @@ roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid, bool is_rx)\n fail:\n \treturn rc;\n }\n+\n+int\n+roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n+\t\t unsigned int n)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct cgx_stats_rsp *cgx_resp;\n+\tstruct rpm_stats_rsp *rpm_resp;\n+\tuint64_t i, count = 0;\n+\tstruct msg_req *req;\n+\tuint32_t xstat_cnt;\n+\tint rc;\n+\n+\txstat_cnt = roc_nix_num_xstats_get(roc_nix);\n+\tif (n < xstat_cnt)\n+\t\treturn xstat_cnt;\n+\n+\tif (xstats == NULL)\n+\t\treturn -EINVAL;\n+\n+\tmemset(xstats, 0, (xstat_cnt * sizeof(*xstats)));\n+\tfor (i = 0; i < CNXK_NIX_NUM_TX_XSTATS; i++) {\n+\t\txstats[count].value = NIX_TX_STATS(nix_tx_xstats[i].offset);\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\tfor (i = 0; i < CNXK_NIX_NUM_RX_XSTATS; i++) {\n+\t\txstats[count].value = NIX_RX_STATS(nix_rx_xstats[i].offset);\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\tfor (i = 0; i < nix->nb_rx_queues; i++)\n+\t\txstats[count].value +=\n+\t\t\tqstat_read(nix, i, nix_q_xstats[0].offset);\n+\n+\txstats[count].id = count;\n+\tcount++;\n+\n+\tif (roc_nix_is_vf_or_sdp(roc_nix))\n+\t\treturn count;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\treq = mbox_alloc_msg_cgx_stats(mbox);\n+\t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&cgx_resp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\tcgx_resp->rx_stats[nix_rx_xstats_cgx[i].offset];\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tfor (i = 0; i < roc_nix_num_tx_xstats(); i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\tcgx_resp->tx_stats[nix_tx_xstats_cgx[i].offset];\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\t} else {\n+\t\treq = mbox_alloc_msg_rpm_stats(mbox);\n+\t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rpm_resp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\trpm_resp->rx_stats[nix_rx_xstats_rpm[i].offset];\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tfor (i = 0; i < roc_nix_num_tx_xstats(); i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\trpm_resp->tx_stats[nix_tx_xstats_rpm[i].offset];\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\treturn count;\n+}\n+\n+int\n+roc_nix_xstats_names_get(struct roc_nix *roc_nix,\n+\t\t\t struct roc_nix_xstat_name *xstats_names,\n+\t\t\t unsigned int limit)\n+{\n+\tunsigned long int i, count = 0;\n+\tunsigned int xstat_cnt;\n+\n+\txstat_cnt = roc_nix_num_xstats_get(roc_nix);\n+\tif (limit < xstat_cnt && xstats_names != NULL)\n+\t\treturn -ENOMEM;\n+\n+\tif (xstats_names) {\n+\t\tfor (i = 0; i < CNXK_NIX_NUM_TX_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t nix_tx_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tfor (i = 0; i < CNXK_NIX_NUM_RX_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t nix_rx_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\t\tfor (i = 0; i < CNXK_NIX_NUM_QUEUE_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t nix_q_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tif (roc_nix_is_vf_or_sdp(roc_nix))\n+\t\t\treturn count;\n+\n+\t\tif (roc_model_is_cn9k()) {\n+\t\t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n+\t\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t\t nix_rx_xstats_cgx[i].name);\n+\t\t\t\tcount++;\n+\t\t\t}\n+\n+\t\t\tfor (i = 0; i < roc_nix_num_tx_xstats(); i++) {\n+\t\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t\t nix_tx_xstats_cgx[i].name);\n+\t\t\t\tcount++;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfor (i = 0; i < roc_nix_num_rx_xstats(); i++) {\n+\t\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t\t nix_rx_xstats_rpm[i].name);\n+\t\t\t\tcount++;\n+\t\t\t}\n+\n+\t\t\tfor (i = 0; i < roc_nix_num_tx_xstats(); i++) {\n+\t\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t\t sizeof(xstats_names[count].name), \"%s\",\n+\t\t\t\t\t nix_tx_xstats_rpm[i].name);\n+\t\t\t\tcount++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn xstat_cnt;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_xstats.h b/drivers/common/cnxk/roc_nix_xstats.h\nnew file mode 100644\nindex 0000000..bde00a6\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_xstats.h\n@@ -0,0 +1,204 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef _ROC_NIX_XSTAT_H_\n+#define _ROC_NIX_XSTAT_H_\n+\n+#include <inttypes.h>\n+\n+struct cnxk_nix_xstats_name {\n+\tchar name[ROC_NIX_XSTATS_NAME_SIZE];\n+\tuint32_t offset;\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_tx_xstats[] = {\n+\t{\"tx_ucast\", NIX_STAT_LF_TX_TX_UCAST},\n+\t{\"tx_bcast\", NIX_STAT_LF_TX_TX_BCAST},\n+\t{\"tx_mcast\", NIX_STAT_LF_TX_TX_MCAST},\n+\t{\"tx_drop\", NIX_STAT_LF_TX_TX_DROP},\n+\t{\"tx_octs\", NIX_STAT_LF_TX_TX_OCTS},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_rx_xstats[] = {\n+\t{\"rx_octs\", NIX_STAT_LF_RX_RX_OCTS},\n+\t{\"rx_ucast\", NIX_STAT_LF_RX_RX_UCAST},\n+\t{\"rx_bcast\", NIX_STAT_LF_RX_RX_BCAST},\n+\t{\"rx_mcast\", NIX_STAT_LF_RX_RX_MCAST},\n+\t{\"rx_drop\", NIX_STAT_LF_RX_RX_DROP},\n+\t{\"rx_drop_octs\", NIX_STAT_LF_RX_RX_DROP_OCTS},\n+\t{\"rx_fcs\", NIX_STAT_LF_RX_RX_FCS},\n+\t{\"rx_err\", NIX_STAT_LF_RX_RX_ERR},\n+\t{\"rx_drp_bcast\", NIX_STAT_LF_RX_RX_DRP_BCAST},\n+\t{\"rx_drp_mcast\", NIX_STAT_LF_RX_RX_DRP_MCAST},\n+\t{\"rx_drp_l3bcast\", NIX_STAT_LF_RX_RX_DRP_L3BCAST},\n+\t{\"rx_drp_l3mcast\", NIX_STAT_LF_RX_RX_DRP_L3MCAST},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_q_xstats[] = {\n+\t{\"rq_op_re_pkts\", NIX_LF_RQ_OP_RE_PKTS},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_rx_xstats_rpm[] = {\n+\t{\"rpm_rx_etherStatsOctets\", RPM_MTI_STAT_RX_OCT_CNT},\n+\t{\"rpm_rx_OctetsReceivedOK\", RPM_MTI_STAT_RX_OCT_RECV_OK},\n+\t{\"rpm_rx_aAlignmentErrors\", RPM_MTI_STAT_RX_ALIG_ERR},\n+\t{\"rpm_rx_aPAUSEMACCtrlFramesReceived\", RPM_MTI_STAT_RX_CTRL_FRM_RECV},\n+\t{\"rpm_rx_aFrameTooLongErrors\", RPM_MTI_STAT_RX_FRM_LONG},\n+\t{\"rpm_rx_aInRangeLengthErrors\", RPM_MTI_STAT_RX_LEN_ERR},\n+\t{\"rpm_rx_aFramesReceivedOK\", RPM_MTI_STAT_RX_FRM_RECV},\n+\t{\"rpm_rx_aFrameCheckSequenceErrors\", RPM_MTI_STAT_RX_FRM_SEQ_ERR},\n+\t{\"rpm_rx_VLANReceivedOK\", RPM_MTI_STAT_RX_VLAN_OK},\n+\t{\"rpm_rx_ifInErrors\", RPM_MTI_STAT_RX_IN_ERR},\n+\t{\"rpm_rx_ifInUcastPkts\", RPM_MTI_STAT_RX_IN_UCAST_PKT},\n+\t{\"rpm_rx_ifInMulticastPkts\", RPM_MTI_STAT_RX_IN_MCAST_PKT},\n+\t{\"rpm_rx_ifInBroadcastPkts\", RPM_MTI_STAT_RX_IN_BCAST_PKT},\n+\t{\"rpm_rx_etherStatsDropEvents\", RPM_MTI_STAT_RX_DRP_EVENTS},\n+\t{\"rpm_rx_etherStatsPkts\", RPM_MTI_STAT_RX_PKT},\n+\t{\"rpm_rx_etherStatsUndersizePkts\", RPM_MTI_STAT_RX_UNDER_SIZE},\n+\t{\"rpm_rx_etherStatsPkts64Octets\", RPM_MTI_STAT_RX_1_64_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts65to127Octets\", RPM_MTI_STAT_RX_65_127_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts128to255Octets\",\n+\t RPM_MTI_STAT_RX_128_255_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts256to511Octets\",\n+\t RPM_MTI_STAT_RX_256_511_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts512to1023Octets\",\n+\t RPM_MTI_STAT_RX_512_1023_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts1024to1518Octets\",\n+\t RPM_MTI_STAT_RX_1024_1518_PKT_CNT},\n+\t{\"rpm_rx_etherStatsPkts1519toMaxOctets\",\n+\t RPM_MTI_STAT_RX_1519_MAX_PKT_CNT},\n+\t{\"rpm_rx_etherStatsOversizePkts\", RPM_MTI_STAT_RX_OVER_SIZE},\n+\t{\"rpm_rx_etherStatsJabbers\", RPM_MTI_STAT_RX_JABBER},\n+\t{\"rpm_rx_etherStatsFragments\", RPM_MTI_STAT_RX_ETH_FRAGS},\n+\t{\"rpm_rx_CBFC_pause_frames_class_0\", RPM_MTI_STAT_RX_CBFC_CLASS_0},\n+\t{\"rpm_rx_CBFC_pause_frames_class_1\", RPM_MTI_STAT_RX_CBFC_CLASS_1},\n+\t{\"rpm_rx_CBFC_pause_frames_class_2\", RPM_MTI_STAT_RX_CBFC_CLASS_2},\n+\t{\"rpm_rx_CBFC_pause_frames_class_3\", RPM_MTI_STAT_RX_CBFC_CLASS_3},\n+\t{\"rpm_rx_CBFC_pause_frames_class_4\", RPM_MTI_STAT_RX_CBFC_CLASS_4},\n+\t{\"rpm_rx_CBFC_pause_frames_class_5\", RPM_MTI_STAT_RX_CBFC_CLASS_5},\n+\t{\"rpm_rx_CBFC_pause_frames_class_6\", RPM_MTI_STAT_RX_CBFC_CLASS_6},\n+\t{\"rpm_rx_CBFC_pause_frames_class_7\", RPM_MTI_STAT_RX_CBFC_CLASS_7},\n+\t{\"rpm_rx_CBFC_pause_frames_class_8\", RPM_MTI_STAT_RX_CBFC_CLASS_8},\n+\t{\"rpm_rx_CBFC_pause_frames_class_9\", RPM_MTI_STAT_RX_CBFC_CLASS_9},\n+\t{\"rpm_rx_CBFC_pause_frames_class_10\", RPM_MTI_STAT_RX_CBFC_CLASS_10},\n+\t{\"rpm_rx_CBFC_pause_frames_class_11\", RPM_MTI_STAT_RX_CBFC_CLASS_11},\n+\t{\"rpm_rx_CBFC_pause_frames_class_12\", RPM_MTI_STAT_RX_CBFC_CLASS_12},\n+\t{\"rpm_rx_CBFC_pause_frames_class_13\", RPM_MTI_STAT_RX_CBFC_CLASS_13},\n+\t{\"rpm_rx_CBFC_pause_frames_class_14\", RPM_MTI_STAT_RX_CBFC_CLASS_14},\n+\t{\"rpm_rx_CBFC_pause_frames_class_15\", RPM_MTI_STAT_RX_CBFC_CLASS_15},\n+\t{\"rpm_rx_aMACControlFramesReceived\", RPM_MTI_STAT_RX_MAC_CONTROL},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_tx_xstats_rpm[] = {\n+\t{\"rpm_tx_etherStatsOctets\", RPM_MTI_STAT_TX_OCT_CNT},\n+\t{\"rpm_tx_OctetsTransmittedOK\", RPM_MTI_STAT_TX_OCT_TX_OK},\n+\t{\"rpm_tx_aPAUSEMACCtrlFramesTransmitted\",\n+\t RPM_MTI_STAT_TX_PAUSE_MAC_CTRL},\n+\t{\"rpm_tx_aFramesTransmittedOK\", RPM_MTI_STAT_TX_FRAMES_OK},\n+\t{\"rpm_tx_VLANTransmittedOK\", RPM_MTI_STAT_TX_VLAN_OK},\n+\t{\"rpm_tx_ifOutErrors\", RPM_MTI_STAT_TX_OUT_ERR},\n+\t{\"rpm_tx_ifOutUcastPkts\", RPM_MTI_STAT_TX_UCAST_PKT_CNT},\n+\t{\"rpm_tx_ifOutMulticastPkts\", RPM_MTI_STAT_TX_MCAST_PKT_CNT},\n+\t{\"rpm_tx_ifOutBroadcastPkts\", RPM_MTI_STAT_TX_BCAST_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts64Octets\", RPM_MTI_STAT_TX_1_64_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts65to127Octets\", RPM_MTI_STAT_TX_65_127_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts128to255Octets\",\n+\t RPM_MTI_STAT_TX_128_255_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts256to511Octets\",\n+\t RPM_MTI_STAT_TX_256_511_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts512to1023Octets\",\n+\t RPM_MTI_STAT_TX_512_1023_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts1024to1518Octets\",\n+\t RPM_MTI_STAT_TX_1024_1518_PKT_CNT},\n+\t{\"rpm_tx_etherStatsPkts1519toMaxOctets\",\n+\t RPM_MTI_STAT_TX_1519_MAX_PKT_CNT},\n+\t{\"rpm_tx_CBFC_pause_frames_class_0\", RPM_MTI_STAT_TX_CBFC_CLASS_0},\n+\t{\"rpm_tx_CBFC_pause_frames_class_1\", RPM_MTI_STAT_TX_CBFC_CLASS_1},\n+\t{\"rpm_tx_CBFC_pause_frames_class_2\", RPM_MTI_STAT_TX_CBFC_CLASS_2},\n+\t{\"rpm_tx_CBFC_pause_frames_class_3\", RPM_MTI_STAT_TX_CBFC_CLASS_3},\n+\t{\"rpm_tx_CBFC_pause_frames_class_4\", RPM_MTI_STAT_TX_CBFC_CLASS_4},\n+\t{\"rpm_tx_CBFC_pause_frames_class_5\", RPM_MTI_STAT_TX_CBFC_CLASS_5},\n+\t{\"rpm_tx_CBFC_pause_frames_class_6\", RPM_MTI_STAT_TX_CBFC_CLASS_6},\n+\t{\"rpm_tx_CBFC_pause_frames_class_7\", RPM_MTI_STAT_TX_CBFC_CLASS_7},\n+\t{\"rpm_tx_CBFC_pause_frames_class_8\", RPM_MTI_STAT_TX_CBFC_CLASS_8},\n+\t{\"rpm_tx_CBFC_pause_frames_class_9\", RPM_MTI_STAT_TX_CBFC_CLASS_9},\n+\t{\"rpm_tx_CBFC_pause_frames_class_10\", RPM_MTI_STAT_TX_CBFC_CLASS_10},\n+\t{\"rpm_tx_CBFC_pause_frames_class_11\", RPM_MTI_STAT_TX_CBFC_CLASS_11},\n+\t{\"rpm_tx_CBFC_pause_frames_class_12\", RPM_MTI_STAT_TX_CBFC_CLASS_12},\n+\t{\"rpm_tx_CBFC_pause_frames_class_13\", RPM_MTI_STAT_TX_CBFC_CLASS_13},\n+\t{\"rpm_tx_CBFC_pause_frames_class_14\", RPM_MTI_STAT_TX_CBFC_CLASS_14},\n+\t{\"rpm_tx_CBFC_pause_frames_class_15\", RPM_MTI_STAT_TX_CBFC_CLASS_15},\n+\t{\"rpm_tx_aMACControlFramesTransmitted\",\n+\t RPM_MTI_STAT_TX_MAC_CONTROL_FRAMES},\n+\t{\"rpm_tx_etherStatsPkts\", RPM_MTI_STAT_TX_PKT_CNT},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_rx_xstats_cgx[] = {\n+\t{\"cgx_rx_pkts\", CGX_RX_PKT_CNT},\n+\t{\"cgx_rx_octs\", CGX_RX_OCT_CNT},\n+\t{\"cgx_rx_pause_pkts\", CGX_RX_PAUSE_PKT_CNT},\n+\t{\"cgx_rx_pause_octs\", CGX_RX_PAUSE_OCT_CNT},\n+\t{\"cgx_rx_dmac_filt_pkts\", CGX_RX_DMAC_FILT_PKT_CNT},\n+\t{\"cgx_rx_dmac_filt_octs\", CGX_RX_DMAC_FILT_OCT_CNT},\n+\t{\"cgx_rx_fifo_drop_pkts\", CGX_RX_FIFO_DROP_PKT_CNT},\n+\t{\"cgx_rx_fifo_drop_octs\", CGX_RX_FIFO_DROP_OCT_CNT},\n+\t{\"cgx_rx_errors\", CGX_RX_ERR_CNT},\n+};\n+\n+static const struct cnxk_nix_xstats_name nix_tx_xstats_cgx[] = {\n+\t{\"cgx_tx_collision_drop\", CGX_TX_COLLISION_DROP},\n+\t{\"cgx_tx_frame_deferred_cnt\", CGX_TX_FRAME_DEFER_CNT},\n+\t{\"cgx_tx_multiple_collision\", CGX_TX_MULTIPLE_COLLISION},\n+\t{\"cgx_tx_single_collision\", CGX_TX_SINGLE_COLLISION},\n+\t{\"cgx_tx_octs\", CGX_TX_OCT_CNT},\n+\t{\"cgx_tx_pkts\", CGX_TX_PKT_CNT},\n+\t{\"cgx_tx_1_to_63_oct_frames\", CGX_TX_1_63_PKT_CNT},\n+\t{\"cgx_tx_64_oct_frames\", CGX_TX_64_PKT_CNT},\n+\t{\"cgx_tx_65_to_127_oct_frames\", CGX_TX_65_127_PKT_CNT},\n+\t{\"cgx_tx_128_to_255_oct_frames\", CGX_TX_128_255_PKT_CNT},\n+\t{\"cgx_tx_256_to_511_oct_frames\", CGX_TX_256_511_PKT_CNT},\n+\t{\"cgx_tx_512_to_1023_oct_frames\", CGX_TX_512_1023_PKT_CNT},\n+\t{\"cgx_tx_1024_to_1518_oct_frames\", CGX_TX_1024_1518_PKT_CNT},\n+\t{\"cgx_tx_1519_to_max_oct_frames\", CGX_TX_1519_MAX_PKT_CNT},\n+\t{\"cgx_tx_broadcast_packets\", CGX_TX_BCAST_PKTS},\n+\t{\"cgx_tx_multicast_packets\", CGX_TX_MCAST_PKTS},\n+\t{\"cgx_tx_underflow_packets\", CGX_TX_UFLOW_PKTS},\n+\t{\"cgx_tx_pause_packets\", CGX_TX_PAUSE_PKTS},\n+};\n+\n+#define CNXK_NIX_NUM_RX_XSTATS\t PLT_DIM(nix_rx_xstats)\n+#define CNXK_NIX_NUM_TX_XSTATS\t PLT_DIM(nix_tx_xstats)\n+#define CNXK_NIX_NUM_QUEUE_XSTATS PLT_DIM(nix_q_xstats)\n+#define CNXK_NIX_NUM_RX_XSTATS_CGX PLT_DIM(nix_rx_xstats_cgx)\n+#define CNXK_NIX_NUM_TX_XSTATS_CGX PLT_DIM(nix_tx_xstats_cgx)\n+#define CNXK_NIX_NUM_RX_XSTATS_RPM PLT_DIM(nix_rx_xstats_rpm)\n+#define CNXK_NIX_NUM_TX_XSTATS_RPM PLT_DIM(nix_tx_xstats_rpm)\n+\n+#define CNXK_NIX_NUM_XSTATS_REG \\\n+\t(CNXK_NIX_NUM_RX_XSTATS + CNXK_NIX_NUM_TX_XSTATS + \\\n+\t CNXK_NIX_NUM_QUEUE_XSTATS)\n+#define CNXK_NIX_NUM_XSTATS_CGX \\\n+\t(CNXK_NIX_NUM_XSTATS_REG + CNXK_NIX_NUM_RX_XSTATS_CGX + \\\n+\t CNXK_NIX_NUM_TX_XSTATS_CGX)\n+#define CNXK_NIX_NUM_XSTATS_RPM \\\n+\t(CNXK_NIX_NUM_XSTATS_REG + CNXK_NIX_NUM_RX_XSTATS_RPM + \\\n+\t CNXK_NIX_NUM_TX_XSTATS_RPM)\n+\n+static inline unsigned long int\n+roc_nix_num_rx_xstats(void)\n+{\n+\tif (roc_model_is_cn9k())\n+\t\treturn CNXK_NIX_NUM_RX_XSTATS_CGX;\n+\n+\treturn CNXK_NIX_NUM_RX_XSTATS_RPM;\n+}\n+\n+static inline unsigned long int\n+roc_nix_num_tx_xstats(void)\n+{\n+\tif (roc_model_is_cn9k())\n+\t\treturn CNXK_NIX_NUM_TX_XSTATS_CGX;\n+\n+\treturn CNXK_NIX_NUM_TX_XSTATS_RPM;\n+}\n+#endif /* _ROC_NIX_XSTAT_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex aa79da6..85b8393 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -83,6 +83,9 @@ INTERNAL {\n \troc_nix_stats_queue_get;\n \troc_nix_stats_queue_reset;\n \troc_nix_stats_reset;\n+\troc_nix_num_xstats_get;\n+\troc_nix_xstats_get;\n+\troc_nix_xstats_names_get;\n \troc_nix_unregister_cq_irqs;\n \troc_nix_unregister_queue_irqs;\n \troc_npa_aura_limit_modify;\n", "prefixes": [ "v2", "27/52" ] }