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GET /api/patches/90313/?format=api
{ "id": 90313, "url": "https://patches.dpdk.org/api/patches/90313/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-25-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401094739.22714-25-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401094739.22714-25-ndabilpuram@marvell.com", "date": "2021-04-01T09:47:11", "name": "[v2,24/52] common/cnxk: add nix RSS support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c4ef8f41c102187af159586245845a0ded30f536", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-25-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16050, "url": "https://patches.dpdk.org/api/series/16050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16050", "date": "2021-04-01T09:46:47", "name": "Add Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/16050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90313/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90313/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 87614A0548;\n\tThu, 1 Apr 2021 11:51:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6496F140ED9;\n\tThu, 1 Apr 2021 11:49:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 6E820140F95\n for <dev@dpdk.org>; Thu, 1 Apr 2021 11:49:20 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1319f5PS014877 for <dev@dpdk.org>; Thu, 1 Apr 2021 02:49:19 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 37n28j1wwx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 02:49:19 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 02:49:18 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 02:49:17 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 6D79B3F7045;\n Thu, 1 Apr 2021 02:49:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=96d6W3KEGelycTDj7sqwBeJa+8yl+iCYoijCj/qZ0qs=;\n b=HnMaGg7cPS5UKuzMcKR+ETOL5ArSDXCEBBN6AQ+ixqIVlk8xVR7AOlz3gKz9LRgbJJyO\n GWstj531TEXkLhkbVNxbXLRGguMPKdg1vpyJ2sqClDV6TZf4ergH619j52WmpFpXuSpA\n 9NWarFJz7lbgeekPyNDipgizShBFpBgKrsO+b4Hbi72UlBq4rmBiOuO/Ocn+AiVO5Ir2\n 9G4aImUFRJwivb1eev8fnugjDYy/1jVhv6U6Mhnzz659N1AISMFqX5pyHDdeXd+pGZQ2\n VMN9c89RfdmTw+ip0CMbzBQfVoWM36CNBSVcR2wtBtANLC6kEH35gGT1aQrYb1I2WSrI hA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 15:17:11 +0530", "Message-ID": "<20210401094739.22714-25-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401094739.22714-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401094739.22714-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "DFC951MJdlA2ctFYFv8Povmtin2XKJk3", "X-Proofpoint-GUID": "DFC951MJdlA2ctFYFv8Povmtin2XKJk3", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_04:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 24/52] common/cnxk: add nix RSS support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd API's for default/non-default reta table setup,\nkey set/get, and flow algo setup for CN9K and CN10K.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 17 +++\n drivers/common/cnxk/roc_nix_rss.c | 220 ++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 7 ++\n 4 files changed, 245 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_rss.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex eafa0ac..b4cdf00 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -27,6 +27,7 @@ sources = files('roc_dev.c',\n \t\t'roc_nix_mcast.c',\n \t\t'roc_nix_npc.c',\n \t\t'roc_nix_queue.c',\n+\t\t'roc_nix_rss.c',\n \t\t'roc_npa.c',\n \t\t'roc_npa_debug.c',\n \t\t'roc_npa_irq.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 1c097cb..83388ce 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -215,6 +215,23 @@ int __roc_api roc_nix_npc_rx_ena_dis(struct roc_nix *roc_nix, bool enable);\n int __roc_api roc_nix_npc_mcast_config(struct roc_nix *roc_nix,\n \t\t\t\t bool mcast_enable, bool prom_enable);\n \n+/* RSS */\n+void __roc_api roc_nix_rss_key_default_fill(struct roc_nix *roc_nix,\n+\t\t\t\t\t uint8_t key[ROC_NIX_RSS_KEY_LEN]);\n+void __roc_api roc_nix_rss_key_set(struct roc_nix *roc_nix,\n+\t\t\t\t const uint8_t key[ROC_NIX_RSS_KEY_LEN]);\n+void __roc_api roc_nix_rss_key_get(struct roc_nix *roc_nix,\n+\t\t\t\t uint8_t key[ROC_NIX_RSS_KEY_LEN]);\n+int __roc_api roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group,\n+\t\t\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX]);\n+int __roc_api roc_nix_rss_reta_get(struct roc_nix *roc_nix, uint8_t group,\n+\t\t\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX]);\n+int __roc_api roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx,\n+\t\t\t\t uint32_t flowkey, uint8_t group,\n+\t\t\t\t int mcam_index);\n+int __roc_api roc_nix_rss_default_setup(struct roc_nix *roc_nix,\n+\t\t\t\t\tuint32_t flowkey);\n+\n /* Queue */\n int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n \t\t\t bool ena);\ndiff --git a/drivers/common/cnxk/roc_nix_rss.c b/drivers/common/cnxk/roc_nix_rss.c\nnew file mode 100644\nindex 0000000..2d7b84a\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_rss.c\n@@ -0,0 +1,220 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+void\n+roc_nix_rss_key_default_fill(struct roc_nix *roc_nix,\n+\t\t\t uint8_t key[ROC_NIX_RSS_KEY_LEN])\n+{\n+\tPLT_SET_USED(roc_nix);\n+\tconst uint8_t default_key[ROC_NIX_RSS_KEY_LEN] = {\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED,\n+\t\t0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED,\n+\t\t0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD};\n+\n+\tmemcpy(key, default_key, ROC_NIX_RSS_KEY_LEN);\n+}\n+\n+void\n+roc_nix_rss_key_set(struct roc_nix *roc_nix,\n+\t\t const uint8_t key[ROC_NIX_RSS_KEY_LEN])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tconst uint64_t *keyptr;\n+\tuint64_t val;\n+\tuint32_t idx;\n+\n+\tkeyptr = (const uint64_t *)key;\n+\tfor (idx = 0; idx < (ROC_NIX_RSS_KEY_LEN >> 3); idx++) {\n+\t\tval = plt_cpu_to_be_64(keyptr[idx]);\n+\t\tplt_write64(val, nix->base + NIX_LF_RX_SECRETX(idx));\n+\t}\n+}\n+\n+void\n+roc_nix_rss_key_get(struct roc_nix *roc_nix, uint8_t key[ROC_NIX_RSS_KEY_LEN])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint64_t *keyptr = (uint64_t *)key;\n+\tuint64_t val;\n+\tuint32_t idx;\n+\n+\tfor (idx = 0; idx < (ROC_NIX_RSS_KEY_LEN >> 3); idx++) {\n+\t\tval = plt_read64(nix->base + NIX_LF_RX_SECRETX(idx));\n+\t\tkeyptr[idx] = plt_be_to_cpu_64(val);\n+\t}\n+}\n+\n+static int\n+nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_aq_enq_req *req;\n+\tuint16_t idx;\n+\tint rc;\n+\n+\tfor (idx = 0; idx < nix->reta_sz; idx++) {\n+\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!req) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * Flush it and retry\n+\t\t\t */\n+\t\t\trc = mbox_process(mbox);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\t\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\t\tif (!req)\n+\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t}\n+\t\treq->rss.rq = reta[idx];\n+\t\t/* Fill AQ info */\n+\t\treq->qidx = (group * nix->reta_sz) + idx;\n+\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n+\t\treq->op = NIX_AQ_INSTOP_INIT;\n+\t}\n+\n+\trc = mbox_process(mbox);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_rss_reta_set(struct nix *nix, uint8_t group,\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_cn10k_aq_enq_req *req;\n+\tuint16_t idx;\n+\tint rc;\n+\n+\tfor (idx = 0; idx < nix->reta_sz; idx++) {\n+\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!req) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * Flush it and retry\n+\t\t\t */\n+\t\t\trc = mbox_process(mbox);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\t\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\t\tif (!req)\n+\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t}\n+\t\treq->rss.rq = reta[idx];\n+\t\t/* Fill AQ info */\n+\t\treq->qidx = (group * nix->reta_sz) + idx;\n+\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n+\t\treq->op = NIX_AQ_INSTOP_INIT;\n+\t}\n+\n+\trc = mbox_process(mbox);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group,\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc;\n+\n+\tif (group >= ROC_NIX_RSS_GRPS)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (roc_model_is_cn9k())\n+\t\trc = nix_cn9k_rss_reta_set(nix, group, reta);\n+\telse\n+\t\trc = nix_rss_reta_set(nix, group, reta);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tmemcpy(&nix->reta[group], reta, ROC_NIX_RSS_RETA_MAX);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_rss_reta_get(struct roc_nix *roc_nix, uint8_t group,\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (group >= ROC_NIX_RSS_GRPS)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tmemcpy(reta, &nix->reta[group], ROC_NIX_RSS_RETA_MAX);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx,\n+\t\t\tuint32_t flowkey, uint8_t group, int mcam_index)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_rss_flowkey_cfg_rsp *rss_rsp;\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_rss_flowkey_cfg *cfg;\n+\tint rc = -ENOSPC;\n+\n+\tif (group >= ROC_NIX_RSS_GRPS)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tcfg = mbox_alloc_msg_nix_rss_flowkey_cfg(mbox);\n+\tif (cfg == NULL)\n+\t\treturn rc;\n+\tcfg->flowkey_cfg = flowkey;\n+\tcfg->mcam_index = mcam_index; /* -1 indicates default group */\n+\tcfg->group = group;\t /* 0 is default group */\n+\trc = mbox_process_msg(mbox, (void *)&rss_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\tif (alg_idx)\n+\t\t*alg_idx = rss_rsp->alg_idx;\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_rss_default_setup(struct roc_nix *roc_nix, uint32_t flowkey)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint16_t idx, qcnt = nix->nb_rx_queues;\n+\tuint16_t reta[ROC_NIX_RSS_RETA_MAX];\n+\tuint8_t key[ROC_NIX_RSS_KEY_LEN];\n+\tuint8_t alg_idx;\n+\tint rc;\n+\n+\troc_nix_rss_key_default_fill(roc_nix, key);\n+\troc_nix_rss_key_set(roc_nix, key);\n+\n+\t/* Update default RSS RETA */\n+\tfor (idx = 0; idx < nix->reta_sz; idx++)\n+\t\treta[idx] = idx % qcnt;\n+\trc = roc_nix_rss_reta_set(roc_nix, 0, reta);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to set RSS reta table rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Update the default flowkey */\n+\trc = roc_nix_rss_flowkey_set(roc_nix, &alg_idx, flowkey,\n+\t\t\t\t ROC_NIX_RSS_GROUP_DEFAULT, -1);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to set RSS flowkey rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\tnix->rss_alg_idx = alg_idx;\n+fail:\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex fdb1aee..14601a8 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -62,6 +62,13 @@ INTERNAL {\n \troc_nix_rq_fini;\n \troc_nix_rq_init;\n \troc_nix_rq_modify;\n+\troc_nix_rss_default_setup;\n+\troc_nix_rss_flowkey_set;\n+\troc_nix_rss_key_default_fill;\n+\troc_nix_rss_key_get;\n+\troc_nix_rss_key_set;\n+\troc_nix_rss_reta_get;\n+\troc_nix_rss_reta_set;\n \troc_nix_rx_queue_intr_disable;\n \troc_nix_rx_queue_intr_enable;\n \troc_nix_sq_fini;\n", "prefixes": [ "v2", "24/52" ] }