Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/89463/?format=api
{ "id": 89463, "url": "https://patches.dpdk.org/api/patches/89463/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1616058798-303292-1-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1616058798-303292-1-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1616058798-303292-1-git-send-email-matan@nvidia.com", "date": "2021-03-18T09:13:18", "name": "vdpa/mlx5: improve interrupt management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a7a341267e93f252b62b0c2d5bd25774c75fde39", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1616058798-303292-1-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 15761, "url": "https://patches.dpdk.org/api/series/15761/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15761", "date": "2021-03-18T09:13:18", "name": "vdpa/mlx5: improve interrupt management", "version": 1, "mbox": "https://patches.dpdk.org/series/15761/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/89463/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/89463/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D383BA0561;\n\tThu, 18 Mar 2021 10:13:27 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CD3E4140F0B;\n\tThu, 18 Mar 2021 10:13:23 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 6E767140F03\n for <dev@dpdk.org>; Thu, 18 Mar 2021 10:13:22 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 18 Mar 2021 11:13:21 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12I9DLFU028889;\n Thu, 18 Mar 2021 11:13:21 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>", "Date": "Thu, 18 Mar 2021 09:13:18 +0000", "Message-Id": "<1616058798-303292-1-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH] vdpa/mlx5: improve interrupt management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The driver should notify the guest for each traffic burst detected by CQ\npolling.\n\nThe CQ polling trigger is defined by `event_mode` device argument,\neither by busy polling on all the CQs or by blocked call to HW\ncompletion event using DevX channel.\n\nAlso, the polling event modes can move to blocked call when the\ntraffic rate is low.\n\nThe current blocked call uses the EAL interrupt API suffering a lot\nof overhead in the API management and serve all the drivers and\nlibraries using only single thread.\n\nUse blocking FD of the DevX channel in order to do blocked call\ndirectly by the DevX channel FD mechanism.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Xueming Li <xuemingl@nvidia.com>\n---\n doc/guides/vdpadevs/mlx5.rst | 8 +-\n drivers/vdpa/mlx5/mlx5_vdpa.c | 8 +-\n drivers/vdpa/mlx5/mlx5_vdpa.h | 8 +-\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 308 +++++++++++++++---------------------\n 4 files changed, 134 insertions(+), 198 deletions(-)", "diff": "diff --git a/doc/guides/vdpadevs/mlx5.rst b/doc/guides/vdpadevs/mlx5.rst\nindex 1f2ae6f..9b2f9f1 100644\n--- a/doc/guides/vdpadevs/mlx5.rst\n+++ b/doc/guides/vdpadevs/mlx5.rst\n@@ -129,10 +129,10 @@ Driver options\n \n - ``no_traffic_time`` parameter [int]\n \n- A nonzero value defines the traffic off time, in seconds, that moves the\n- driver to no-traffic mode. In this mode the timer events are stopped and\n- interrupts are configured to the device in order to notify traffic for the\n- driver. Default value is 2s.\n+ A nonzero value defines the traffic off time, in polling cycle time units,\n+ that moves the driver to no-traffic mode. In this mode the polling is stopped\n+ and interrupts are configured to the device in order to notify traffic for the\n+ driver. Default value is 16.\n \n - ``event_core`` parameter [int]\n \ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex 4c2d886..5d70880 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -44,7 +44,7 @@\n \n #define MLX5_VDPA_MAX_RETRIES 20\n #define MLX5_VDPA_USEC 1000\n-#define MLX5_VDPA_DEFAULT_NO_TRAFFIC_TIME_S 2LLU\n+#define MLX5_VDPA_DEFAULT_NO_TRAFFIC_MAX 16LLU\n \n TAILQ_HEAD(mlx5_vdpa_privs, mlx5_vdpa_priv) priv_list =\n \t\t\t\t\t TAILQ_HEAD_INITIALIZER(priv_list);\n@@ -632,7 +632,7 @@\n \t} else if (strcmp(key, \"event_us\") == 0) {\n \t\tpriv->event_us = (uint32_t)tmp;\n \t} else if (strcmp(key, \"no_traffic_time\") == 0) {\n-\t\tpriv->no_traffic_time_s = (uint32_t)tmp;\n+\t\tpriv->no_traffic_max = (uint32_t)tmp;\n \t} else if (strcmp(key, \"event_core\") == 0) {\n \t\tif (tmp >= (unsigned long)n_cores)\n \t\t\tDRV_LOG(WARNING, \"Invalid event_core %s.\", val);\n@@ -658,7 +658,7 @@\n \tpriv->event_mode = MLX5_VDPA_EVENT_MODE_FIXED_TIMER;\n \tpriv->event_us = 0;\n \tpriv->event_core = -1;\n-\tpriv->no_traffic_time_s = MLX5_VDPA_DEFAULT_NO_TRAFFIC_TIME_S;\n+\tpriv->no_traffic_max = MLX5_VDPA_DEFAULT_NO_TRAFFIC_MAX;\n \tif (devargs == NULL)\n \t\treturn;\n \tkvlist = rte_kvargs_parse(devargs->args, NULL);\n@@ -671,7 +671,7 @@\n \t\tpriv->event_us = MLX5_VDPA_DEFAULT_TIMER_STEP_US;\n \tDRV_LOG(DEBUG, \"event mode is %d.\", priv->event_mode);\n \tDRV_LOG(DEBUG, \"event_us is %u us.\", priv->event_us);\n-\tDRV_LOG(DEBUG, \"no traffic time is %u s.\", priv->no_traffic_time_s);\n+\tDRV_LOG(DEBUG, \"no traffic max is %u.\", priv->no_traffic_max);\n }\n \n /**\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex 98c71aa..e4c8575 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -120,16 +120,13 @@ struct mlx5_vdpa_priv {\n \tTAILQ_ENTRY(mlx5_vdpa_priv) next;\n \tuint8_t configured;\n \tpthread_mutex_t vq_config_lock;\n-\tuint64_t last_traffic_tic;\n+\tuint64_t no_traffic_counter;\n \tpthread_t timer_tid;\n-\tpthread_mutex_t timer_lock;\n-\tpthread_cond_t timer_cond;\n-\tvolatile uint8_t timer_on;\n \tint event_mode;\n \tint event_core; /* Event thread cpu affinity core. */\n \tuint32_t event_us;\n \tuint32_t timer_delay_us;\n-\tuint32_t no_traffic_time_s;\n+\tuint32_t no_traffic_max;\n \tuint8_t hw_latency_mode; /* Hardware CQ moderation mode. */\n \tuint16_t hw_max_latency_us; /* Hardware CQ moderation period in usec. */\n \tuint16_t hw_max_pending_comp; /* Hardware CQ moderation counter. */\n@@ -146,7 +143,6 @@ struct mlx5_vdpa_priv {\n \tstruct mlx5dv_devx_event_channel *eventc;\n \tstruct mlx5dv_devx_event_channel *err_chnl;\n \tstruct mlx5dv_devx_uar *uar;\n-\tstruct rte_intr_handle intr_handle;\n \tstruct rte_intr_handle err_intr_handle;\n \tstruct mlx5_devx_obj *td;\n \tstruct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 86adc86..64a1753 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -35,17 +35,6 @@\n \t}\n #ifdef HAVE_IBV_DEVX_EVENT\n \tif (priv->eventc) {\n-\t\tunion {\n-\t\t\tstruct mlx5dv_devx_async_event_hdr event_resp;\n-\t\t\tuint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)\n-\t\t\t\t\t\t\t\t\t + 128];\n-\t\t} out;\n-\n-\t\t/* Clean all pending events. */\n-\t\twhile (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,\n-\t\t sizeof(out.buf)) >=\n-\t\t (ssize_t)sizeof(out.event_resp.cookie))\n-\t\t\t;\n \t\tmlx5_os_devx_destroy_event_channel(priv->eventc);\n \t\tpriv->eventc = NULL;\n \t}\n@@ -56,8 +45,6 @@\n static int\n mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)\n {\n-\tint flags, ret;\n-\n \tif (priv->eventc)\n \t\treturn 0;\n \tpriv->eventc = mlx5_os_devx_create_event_channel(priv->ctx,\n@@ -68,12 +55,6 @@\n \t\t\trte_errno);\n \t\tgoto error;\n \t}\n-\tflags = fcntl(priv->eventc->fd, F_GETFL);\n-\tret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Failed to change event channel FD.\");\n-\t\tgoto error;\n-\t}\n \t/*\n \t * This PMD always claims the write memory barrier on UAR\n \t * registers writings, it is safe to allocate UAR with any\n@@ -237,122 +218,112 @@\n \t\tpthread_yield();\n }\n \n-static void *\n-mlx5_vdpa_poll_handle(void *arg)\n+/* Notify virtio device for specific virtq new traffic. */\n+static uint32_t\n+mlx5_vdpa_queue_complete(struct mlx5_vdpa_cq *cq)\n {\n-\tstruct mlx5_vdpa_priv *priv = arg;\n-\tint i;\n-\tstruct mlx5_vdpa_cq *cq;\n-\tuint32_t max;\n-\tuint64_t current_tic;\n-\n-\tpthread_mutex_lock(&priv->timer_lock);\n-\twhile (!priv->timer_on)\n-\t\tpthread_cond_wait(&priv->timer_cond, &priv->timer_lock);\n-\tpthread_mutex_unlock(&priv->timer_lock);\n-\tpriv->timer_delay_us = priv->event_mode ==\n-\t\t\t\t\t MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?\n-\t\t\t\t\t MLX5_VDPA_DEFAULT_TIMER_DELAY_US :\n-\t\t\t\t\t\t\t\t priv->event_us;\n-\twhile (1) {\n-\t\tmax = 0;\n-\t\tpthread_mutex_lock(&priv->vq_config_lock);\n-\t\tfor (i = 0; i < priv->nr_virtqs; i++) {\n-\t\t\tcq = &priv->virtqs[i].eqp.cq;\n-\t\t\tif (cq->cq_obj.cq && !cq->armed) {\n-\t\t\t\tuint32_t comp = mlx5_vdpa_cq_poll(cq);\n-\n-\t\t\t\tif (comp) {\n-\t\t\t\t\t/* Notify guest for descs consuming. */\n-\t\t\t\t\tif (cq->callfd != -1)\n-\t\t\t\t\t\teventfd_write(cq->callfd,\n-\t\t\t\t\t\t\t (eventfd_t)1);\n-\t\t\t\t\tif (comp > max)\n-\t\t\t\t\t\tmax = comp;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t\tcurrent_tic = rte_rdtsc();\n-\t\tif (!max) {\n-\t\t\t/* No traffic ? stop timer and load interrupts. */\n-\t\t\tif (current_tic - priv->last_traffic_tic >=\n-\t\t\t rte_get_timer_hz() * priv->no_traffic_time_s) {\n-\t\t\t\tDRV_LOG(DEBUG, \"Device %s traffic was stopped.\",\n-\t\t\t\t\tpriv->vdev->device->name);\n-\t\t\t\tmlx5_vdpa_arm_all_cqs(priv);\n-\t\t\t\tpthread_mutex_unlock(&priv->vq_config_lock);\n-\t\t\t\tpthread_mutex_lock(&priv->timer_lock);\n-\t\t\t\tpriv->timer_on = 0;\n-\t\t\t\twhile (!priv->timer_on)\n-\t\t\t\t\tpthread_cond_wait(&priv->timer_cond,\n-\t\t\t\t\t\t\t &priv->timer_lock);\n-\t\t\t\tpthread_mutex_unlock(&priv->timer_lock);\n-\t\t\t\tpriv->timer_delay_us = priv->event_mode ==\n-\t\t\t\t\t MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?\n-\t\t\t\t\t MLX5_VDPA_DEFAULT_TIMER_DELAY_US :\n-\t\t\t\t\t\t\t\t priv->event_us;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tpriv->last_traffic_tic = current_tic;\n+\tuint32_t comp = 0;\n+\n+\tif (cq->cq_obj.cq) {\n+\t\tcomp = mlx5_vdpa_cq_poll(cq);\n+\t\tif (comp) {\n+\t\t\tif (cq->callfd != -1)\n+\t\t\t\teventfd_write(cq->callfd, (eventfd_t)1);\n+\t\t\tcq->armed = 0;\n \t\t}\n-\t\tpthread_mutex_unlock(&priv->vq_config_lock);\n-\t\tmlx5_vdpa_timer_sleep(priv, max);\n \t}\n-\treturn NULL;\n+\treturn comp;\n }\n \n-static void\n-mlx5_vdpa_interrupt_handler(void *cb_arg)\n+/* Notify virtio device for any virtq new traffic. */\n+static uint32_t\n+mlx5_vdpa_queues_complete(struct mlx5_vdpa_priv *priv)\n+{\n+\tint i;\n+\tuint32_t max = 0;\n+\n+\tfor (i = 0; i < priv->nr_virtqs; i++) {\n+\t\tstruct mlx5_vdpa_cq *cq = &priv->virtqs[i].eqp.cq;\n+\t\tuint32_t comp = mlx5_vdpa_queue_complete(cq);\n+\n+\t\tif (comp > max)\n+\t\t\tmax = comp;\n+\t}\n+\treturn max;\n+}\n+\n+/* Wait on all CQs channel for completion event. */\n+static struct mlx5_vdpa_cq *\n+mlx5_vdpa_event_wait(struct mlx5_vdpa_priv *priv __rte_unused)\n {\n-\tstruct mlx5_vdpa_priv *priv = cb_arg;\n #ifdef HAVE_IBV_DEVX_EVENT\n \tunion {\n \t\tstruct mlx5dv_devx_async_event_hdr event_resp;\n \t\tuint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];\n \t} out;\n+\tint ret = mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,\n+\t\t\t\t\t sizeof(out.buf));\n \n-\tpthread_mutex_lock(&priv->vq_config_lock);\n-\twhile (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,\n-\t\t\t\t\t sizeof(out.buf)) >=\n-\t\t\t\t (ssize_t)sizeof(out.event_resp.cookie)) {\n-\t\tstruct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)\n-\t\t\t\t\t (uintptr_t)out.event_resp.cookie;\n-\t\tstruct mlx5_vdpa_event_qp *eqp = container_of(cq,\n-\t\t\t\t\t\t struct mlx5_vdpa_event_qp, cq);\n-\t\tstruct mlx5_vdpa_virtq *virtq = container_of(eqp,\n-\t\t\t\t\t\t struct mlx5_vdpa_virtq, eqp);\n-\n-\t\tif (!virtq->enable)\n-\t\t\tcontinue;\n-\t\tmlx5_vdpa_cq_poll(cq);\n-\t\t/* Notify guest for descs consuming. */\n-\t\tif (cq->callfd != -1)\n-\t\t\teventfd_write(cq->callfd, (eventfd_t)1);\n-\t\tif (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {\n-\t\t\tmlx5_vdpa_cq_arm(priv, cq);\n-\t\t\tpthread_mutex_unlock(&priv->vq_config_lock);\n-\t\t\treturn;\n-\t\t}\n-\t\t/* Don't arm again - timer will take control. */\n-\t\tDRV_LOG(DEBUG, \"Device %s virtq %d cq %d event was captured.\"\n-\t\t\t\" Timer is %s, cq ci is %u.\\n\",\n-\t\t\tpriv->vdev->device->name,\n-\t\t\t(int)virtq->index, cq->cq_obj.cq->id,\n-\t\t\tpriv->timer_on ? \"on\" : \"off\", cq->cq_ci);\n-\t\tcq->armed = 0;\n-\t}\n+\tif (ret >= 0)\n+\t\treturn (struct mlx5_vdpa_cq *)(uintptr_t)out.event_resp.cookie;\n+\tDRV_LOG(INFO, \"Got error in devx_get_event, ret = %d, errno = %d.\",\n+\t\tret, errno);\n #endif\n+\treturn NULL;\n+}\n \n-\t/* Traffic detected: make sure timer is on. */\n-\tpriv->last_traffic_tic = rte_rdtsc();\n-\tpthread_mutex_lock(&priv->timer_lock);\n-\tif (!priv->timer_on) {\n-\t\tpriv->timer_on = 1;\n-\t\tpthread_cond_signal(&priv->timer_cond);\n+static void *\n+mlx5_vdpa_event_handle(void *arg)\n+{\n+\tstruct mlx5_vdpa_priv *priv = arg;\n+\tstruct mlx5_vdpa_cq *cq;\n+\tuint32_t max;\n+\n+\tswitch (priv->event_mode) {\n+\tcase MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER:\n+\tcase MLX5_VDPA_EVENT_MODE_FIXED_TIMER:\n+\t\tpriv->timer_delay_us = priv->event_us;\n+\t\twhile (1) {\n+\t\t\tpthread_mutex_lock(&priv->vq_config_lock);\n+\t\t\tmax = mlx5_vdpa_queues_complete(priv);\n+\t\t\tif (max == 0 && priv->no_traffic_counter++ >=\n+\t\t\t priv->no_traffic_max) {\n+\t\t\t\tDRV_LOG(DEBUG, \"Device %s traffic was stopped.\",\n+\t\t\t\t\tpriv->vdev->device->name);\n+\t\t\t\tmlx5_vdpa_arm_all_cqs(priv);\n+\t\t\t\tdo {\n+\t\t\t\t\tpthread_mutex_unlock\n+\t\t\t\t\t\t\t(&priv->vq_config_lock);\n+\t\t\t\t\tcq = mlx5_vdpa_event_wait(priv);\n+\t\t\t\t\tpthread_mutex_lock\n+\t\t\t\t\t\t\t(&priv->vq_config_lock);\n+\t\t\t\t\tif (cq == NULL ||\n+\t\t\t\t\t mlx5_vdpa_queue_complete(cq) > 0)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t} while (1);\n+\t\t\t\tpriv->timer_delay_us = priv->event_us;\n+\t\t\t\tpriv->no_traffic_counter = 0;\n+\t\t\t} else if (max != 0) {\n+\t\t\t\tpriv->no_traffic_counter = 0;\n+\t\t\t}\n+\t\t\tpthread_mutex_unlock(&priv->vq_config_lock);\n+\t\t\tmlx5_vdpa_timer_sleep(priv, max);\n+\t\t}\n+\t\treturn NULL;\n+\tcase MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT:\n+\t\tdo {\n+\t\t\tcq = mlx5_vdpa_event_wait(priv);\n+\t\t\tif (cq != NULL) {\n+\t\t\t\tpthread_mutex_lock(&priv->vq_config_lock);\n+\t\t\t\tif (mlx5_vdpa_queue_complete(cq) > 0)\n+\t\t\t\t\tmlx5_vdpa_cq_arm(priv, cq);\n+\t\t\t\tpthread_mutex_unlock(&priv->vq_config_lock);\n+\t\t\t}\n+\t\t} while (1);\n+\t\treturn NULL;\n+\tdefault:\n+\t\treturn NULL;\n \t}\n-\tpthread_mutex_unlock(&priv->timer_lock);\n-\tpthread_mutex_unlock(&priv->vq_config_lock);\n }\n \n static void\n@@ -510,80 +481,49 @@\n \tif (!priv->eventc)\n \t\t/* All virtqs are in poll mode. */\n \t\treturn 0;\n-\tif (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {\n-\t\tpthread_mutex_init(&priv->timer_lock, NULL);\n-\t\tpthread_cond_init(&priv->timer_cond, NULL);\n-\t\tpriv->timer_on = 0;\n-\t\tpthread_attr_init(&attr);\n-\t\tCPU_ZERO(&cpuset);\n-\t\tif (priv->event_core != -1)\n-\t\t\tCPU_SET(priv->event_core, &cpuset);\n-\t\telse\n-\t\t\tcpuset = rte_lcore_cpuset(rte_get_main_lcore());\n-\t\tret = pthread_attr_setaffinity_np(&attr, sizeof(cpuset),\n-\t\t\t\t\t\t &cpuset);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Failed to set thread affinity.\");\n-\t\t\treturn -1;\n-\t\t}\n-\t\tret = pthread_attr_setschedpolicy(&attr, SCHED_RR);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Failed to set thread sched policy = RR.\");\n-\t\t\treturn -1;\n-\t\t}\n-\t\tret = pthread_attr_setschedparam(&attr, &sp);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Failed to set thread priority.\");\n-\t\t\treturn -1;\n-\t\t}\n-\t\tret = pthread_create(&priv->timer_tid, &attr,\n-\t\t\t\t mlx5_vdpa_poll_handle, (void *)priv);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Failed to create timer thread.\");\n-\t\t\treturn -1;\n-\t\t}\n-\t\tsnprintf(name, sizeof(name), \"vDPA-mlx5-%d\", priv->vid);\n-\t\tret = pthread_setname_np(priv->timer_tid, name);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Failed to set timer thread name.\");\n-\t\t\treturn -1;\n-\t\t}\n+\tpthread_attr_init(&attr);\n+\tCPU_ZERO(&cpuset);\n+\tif (priv->event_core != -1)\n+\t\tCPU_SET(priv->event_core, &cpuset);\n+\telse\n+\t\tcpuset = rte_lcore_cpuset(rte_get_main_lcore());\n+\tret = pthread_attr_setaffinity_np(&attr, sizeof(cpuset),\n+\t\t\t\t\t &cpuset);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to set thread affinity.\");\n+\t\treturn -1;\n \t}\n-\tpriv->intr_handle.fd = priv->eventc->fd;\n-\tpriv->intr_handle.type = RTE_INTR_HANDLE_EXT;\n-\tif (rte_intr_callback_register(&priv->intr_handle,\n-\t\t\t\t mlx5_vdpa_interrupt_handler, priv)) {\n-\t\tpriv->intr_handle.fd = 0;\n-\t\tDRV_LOG(ERR, \"Failed to register CQE interrupt %d.\", rte_errno);\n-\t\tgoto error;\n+\tret = pthread_attr_setschedpolicy(&attr, SCHED_RR);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to set thread sched policy = RR.\");\n+\t\treturn -1;\n \t}\n+\tret = pthread_attr_setschedparam(&attr, &sp);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to set thread priority.\");\n+\t\treturn -1;\n+\t}\n+\tret = pthread_create(&priv->timer_tid, &attr,\n+\t\t\t mlx5_vdpa_event_handle, (void *)priv);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to create timer thread.\");\n+\t\treturn -1;\n+\t}\n+\tsnprintf(name, sizeof(name), \"vDPA-mlx5-%d\", priv->vid);\n+\tret = pthread_setname_np(priv->timer_tid, name);\n+\tif (ret)\n+\t\tDRV_LOG(ERR, \"Failed to set timer thread name.\");\n+\telse\n+\t\tDRV_LOG(DEBUG, \"Device %s thread name: %s.\",\n+\t\t\tpriv->vdev->device->name, name);\n \treturn 0;\n-error:\n-\tmlx5_vdpa_cqe_event_unset(priv);\n-\treturn -1;\n }\n \n void\n mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)\n {\n-\tint retries = MLX5_VDPA_INTR_RETRIES;\n-\tint ret = -EAGAIN;\n \tvoid *status;\n \n-\tif (priv->intr_handle.fd) {\n-\t\twhile (retries-- && ret == -EAGAIN) {\n-\t\t\tret = rte_intr_callback_unregister(&priv->intr_handle,\n-\t\t\t\t\t\t mlx5_vdpa_interrupt_handler,\n-\t\t\t\t\t\t priv);\n-\t\t\tif (ret == -EAGAIN) {\n-\t\t\t\tDRV_LOG(DEBUG, \"Try again to unregister fd %d \"\n-\t\t\t\t\t\"of CQ interrupt, retries = %d.\",\n-\t\t\t\t\tpriv->intr_handle.fd, retries);\n-\t\t\t\trte_pause();\n-\t\t\t}\n-\t\t}\n-\t\tmemset(&priv->intr_handle, 0, sizeof(priv->intr_handle));\n-\t}\n \tif (priv->timer_tid) {\n \t\tpthread_cancel(priv->timer_tid);\n \t\tpthread_join(priv->timer_tid, &status);\n", "prefixes": [] }