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GET /api/patches/89223/?format=api
{ "id": 89223, "url": "https://patches.dpdk.org/api/patches/89223/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210316105149.110904-8-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210316105149.110904-8-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210316105149.110904-8-jiawenwu@trustnetic.com", "date": "2021-03-16T10:51:49", "name": "[v2,7/7] net/txgbe: add FFE parameters for user debugging", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5fb48d404317adbf308e700f2e5033a64b28a7f1", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210316105149.110904-8-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 15691, "url": "https://patches.dpdk.org/api/series/15691/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15691", "date": "2021-03-16T10:51:42", "name": "txgbe backplane AN training", "version": 2, "mbox": "https://patches.dpdk.org/series/15691/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/89223/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/89223/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 222C7A054F;\n\tTue, 16 Mar 2021 11:52:46 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E5012428AF;\n\tTue, 16 Mar 2021 11:52:07 +0100 (CET)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by mails.dpdk.org (Postfix) with ESMTP id 2CBFE242806\n for <dev@dpdk.org>; Tue, 16 Mar 2021 11:52:02 +0100 (CET)", "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Tue, 16 Mar 2021 18:51:57 +0800 (CST)" ], "X-QQ-mid": "bizesmtp11t1615891918t77ixqvy", "X-QQ-SSF": "01400000002000C0E000B00A0000000", "X-QQ-FEAT": "x/IOQElPckInTUDUMl80k8awLF9DUe81qc5tqj5WVkg4xOs4xNnyEr6BrFZOG\n hJqbUKp4owWGcJnyhyLIWx8rj9+m2OSLQIT1vC32SdyPLrOGGvKgQjhc71TcSc3Hzt6PVli\n pTsyK8HifoRLF6hmS9gaEeaWWPhH8JD85oVvFg6B4aP5T7jx6OV+HmAj2PqUIP89VewKr+p\n aG9FYFbQ8KJyFeMtlOCEZUlJzHsEvP8ICUGo/13EBeYg6n0fXUH0xsDtRlE0eWZU/vcjOv6\n O3saXhYhKuo81H3DFHUW4wr5+XhySe787CWQhs7W4sLs3WHtbbU8FPPISHc7Fh4E672ANJ/\n UefuSOTBeIdmQDUmHIplIuNM6Ptv9NtPLOEwfhM", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Tue, 16 Mar 2021 18:51:49 +0800", "Message-Id": "<20210316105149.110904-8-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210316105149.110904-1-jiawenwu@trustnetic.com>", "References": "<20210316105149.110904-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 7/7] net/txgbe: add FFE parameters for user\n debugging", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support to set PHY link mode by user defined.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_hw.c | 11 ++++\n drivers/net/txgbe/base/txgbe_phy.c | 98 +++++++++++++++++++++++++++++-\n drivers/net/txgbe/base/txgbe_phy.h | 10 +++\n 3 files changed, 116 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex 917bd947f..3e7f2f9a3 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -2951,6 +2951,9 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)\n \n \tDEBUGFUNC(\"txgbe_get_media_type_raptor\");\n \n+\tif (hw->phy.ffe_set)\n+\t\ttxgbe_bp_mode_set(hw);\n+\n \t/* Detect if there is a copper PHY attached. */\n \tswitch (hw->phy.type) {\n \tcase txgbe_phy_cu_unknown:\n@@ -3544,6 +3547,14 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)\n \t\thw->mac.orig_autoc = autoc;\n \t}\n \n+\tif (hw->phy.ffe_set) {\n+\t\t/* Make sure phy power is up */\n+\t\tmsec_delay(50);\n+\n+\t\t/* A temporary solution to set phy */\n+\t\ttxgbe_set_phy_temp(hw);\n+\t}\n+\n \t/* Store the permanent mac address */\n \thw->mac.get_mac_addr(hw, hw->mac.perm_addr);\n \ndiff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c\nindex 5402a064f..dabc346f5 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.c\n+++ b/drivers/net/txgbe/base/txgbe_phy.c\n@@ -1513,6 +1513,15 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)\n \t} else {\n \t\twr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);\n \t}\n+\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_KR) {\n+\t\tvalue = (0x1804 & ~0x3F3F);\n+\t\tvalue |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t}\n out:\n \treturn err;\n }\n@@ -1710,7 +1719,14 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)\n \t\tgoto out;\n \t}\n \n-\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_KX4) {\n+\t\tvalue = (0x1804 & ~0x3F3F);\n+\t\tvalue |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n \t\tvalue = (0x1804 & ~0x3F3F);\n \t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n \n@@ -1917,7 +1933,15 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,\n \t\tgoto out;\n \t}\n \n-\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_KX) {\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;\n+\t\tvalue |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;\n+\t\tvalue |= hw->phy.ffe_post | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n \t\tvalue = (0x1804 & ~0x3F3F) | (24 << 8) | 4;\n \t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n \n@@ -2144,7 +2168,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n \t\tgoto out;\n \t}\n \n-\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_SFI) {\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;\n+\t\tvalue |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;\n+\t\tvalue |= hw->phy.ffe_post | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n \t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n \t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n \t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n@@ -2318,6 +2350,66 @@ void txgbe_bp_down_event(struct txgbe_hw *hw)\n \ttxgbe_set_link_to_kr(hw, 0);\n }\n \n+void txgbe_bp_mode_set(struct txgbe_hw *hw)\n+{\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_SFI)\n+\t\thw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP;\n+\telse if (hw->phy.ffe_set == TXGBE_BP_M_KR)\n+\t\thw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4;\n+\telse if (hw->phy.ffe_set == TXGBE_BP_M_KX4)\n+\t\thw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI;\n+\telse if (hw->phy.ffe_set == TXGBE_BP_M_KX)\n+\t\thw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII;\n+}\n+\n+void txgbe_set_phy_temp(struct txgbe_hw *hw)\n+{\n+\tu32 value;\n+\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_SFI) {\n+\t\tBP_LOG(\"Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\\n\",\n+\t\t\thw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n+\t\tvalue = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |\n+\t\t\thw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\tvalue = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t}\n+\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_KR) {\n+\t\tBP_LOG(\"Set KR TX_EQ MAIN:%d PRE:%d POST:%d\\n\",\n+\t\t\thw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);\n+\t\tvalue = (0x1804 & ~0x3F3F);\n+\t\tvalue |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t\twr32_epcs(hw, 0x18035, 0x00FF);\n+\t\twr32_epcs(hw, 0x18055, 0x00FF);\n+\t}\n+\n+\tif (hw->phy.ffe_set == TXGBE_BP_M_KX) {\n+\t\tBP_LOG(\"Set KX TX_EQ MAIN:%d PRE:%d POST:%d\\n\",\n+\t\t\thw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n+\t\tvalue = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |\n+\t\t\thw->phy.ffe_pre;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\tvalue = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\n+\t\twr32_epcs(hw, 0x18035, 0x00FF);\n+\t\twr32_epcs(hw, 0x18055, 0x00FF);\n+\t}\n+}\n+\n /**\n * txgbe_kr_handle - Handle the interrupt of auto-negotiation\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h\nindex d2f2b2f8e..56531c4f8 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.h\n+++ b/drivers/net/txgbe/base/txgbe_phy.h\n@@ -396,6 +396,14 @@\n #define TXGBE_MD_PORT_CTRL 0xF001\n #define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1)\n \n+#define TXGBE_BP_M_NULL 0\n+#define TXGBE_BP_M_SFI 1\n+#define TXGBE_BP_M_KR 2\n+#define TXGBE_BP_M_KX4 3\n+#define TXGBE_BP_M_KX 4\n+#define TXGBE_BP_M_NAUTO 0\n+#define TXGBE_BP_M_AUTO 1\n+\n #ifndef CL72_KRTR_PRBS_MODE_EN\n #define CL72_KRTR_PRBS_MODE_EN\t0xFFFF\t/* open kr prbs check */\n #endif\n@@ -454,6 +462,8 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 eeprom_data);\n u64 txgbe_autoc_read(struct txgbe_hw *hw);\n void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);\n+void txgbe_bp_mode_set(struct txgbe_hw *hw);\n+void txgbe_set_phy_temp(struct txgbe_hw *hw);\n void txgbe_bp_down_event(struct txgbe_hw *hw);\n s32 txgbe_kr_handle(struct txgbe_hw *hw);\n \n", "prefixes": [ "v2", "7/7" ] }