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GET /api/patches/88779/?format=api
{ "id": 88779, "url": "https://patches.dpdk.org/api/patches/88779/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210309235732.3952418-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210309235732.3952418-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210309235732.3952418-2-suanmingm@nvidia.com", "date": "2021-03-09T23:57:30", "name": "[1/3] common/mlx5: add user memory registration bits", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c402f75365addc155763a7ade2123b210f52c92d", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210309235732.3952418-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 15557, "url": "https://patches.dpdk.org/api/series/15557/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15557", "date": "2021-03-09T23:57:29", "name": "regex/mlx5: support scattered mbuf", "version": 1, "mbox": "https://patches.dpdk.org/series/15557/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/88779/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/88779/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75B6FA0567;\n\tWed, 10 Mar 2021 00:57:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2BC2322A59F;\n\tWed, 10 Mar 2021 00:57:43 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id DA95F22A2B5\n for <dev@dpdk.org>; Wed, 10 Mar 2021 00:57:40 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 10 Mar 2021 01:57:39 +0200", "from nvidia.com (mtbc-r640-03.mtbc.labs.mlnx [10.75.70.8])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 129NvZhp030478;\n Wed, 10 Mar 2021 01:57:37 +0200" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com", "Cc": "rasland@nvidia.com, dev@dpdk.org", "Date": "Wed, 10 Mar 2021 01:57:30 +0200", "Message-Id": "<20210309235732.3952418-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210309235732.3952418-1-suanmingm@nvidia.com>", "References": "<20210309235732.3952418-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 1/3] common/mlx5: add user memory registration\n bits", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds the UMR capability bits.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++\n 3 files changed, 10 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 220de35420..5d6a861689 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -186,6 +186,8 @@ has_sym_args = [\n \t'mlx5dv_dr_action_create_aso' ],\n \t[ 'HAVE_INFINIBAND_VERBS_H', 'infiniband/verbs.h',\n \t'INFINIBAND_VERBS_H' ],\n+ [ 'HAVE_MLX5_UMR_IMKEY', 'infiniband/mlx5dv.h',\n+ 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ],\n ]\n config = configuration_data()\n foreach arg:has_sym_args\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 0060c37fc0..b4b7a76db0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -266,6 +266,7 @@ mlx5_devx_cmd_mkey_create(void *ctx,\n \tMLX5_SET(mkc, mkc, qpn, 0xffffff);\n \tMLX5_SET(mkc, mkc, pd, attr->pd);\n \tMLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);\n+\tMLX5_SET(mkc, mkc, umr_en, attr->umr_en);\n \tMLX5_SET(mkc, mkc, translations_octword_size, translation_size);\n \tMLX5_SET(mkc, mkc, relaxed_ordering_write,\n \t\t attr->relaxed_ordering_write);\n@@ -749,6 +750,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t\t\tmini_cqe_resp_flow_tag);\n \tattr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t mini_cqe_resp_l3_l4_tag);\n+\tattr->umr_indirect_mkey_disabled =\n+\t\tMLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);\n+\tattr->umr_modify_entity_size_disabled =\n+\t\tMLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex bc66d28e83..e300c307e1 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -31,6 +31,7 @@ struct mlx5_devx_mkey_attr {\n \tuint32_t pg_access:1;\n \tuint32_t relaxed_ordering_write:1;\n \tuint32_t relaxed_ordering_read:1;\n+\tuint32_t umr_en:1;\n \tstruct mlx5_klm *klm_array;\n \tint klm_num;\n };\n@@ -147,6 +148,8 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_mmo_dma:5;\n \tuint32_t log_max_mmo_compress:5;\n \tuint32_t log_max_mmo_decompress:5;\n+\tuint32_t umr_modify_entity_size_disabled:1;\n+\tuint32_t umr_indirect_mkey_disabled:1;\n };\n \n struct mlx5_devx_wq_attr {\n", "prefixes": [ "1/3" ] }