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GET /api/patches/87367/?format=api
{ "id": 87367, "url": "https://patches.dpdk.org/api/patches/87367/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-9-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-9-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-9-pnalla@marvell.com", "date": "2021-01-26T21:30:49", "name": "[v3,09/11] net/octeontx_ep: Added dev start and stop", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "57cd46c491e6032e1b9164dd0ec883c9ffd9a412", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-9-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87367/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DE1B6A052A;\n\tTue, 26 Jan 2021 22:33:02 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A560F140D75;\n\tTue, 26 Jan 2021 22:32:03 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id EE8BC140D12\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:49 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QL0J6F025557 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:49 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 368m6uhds1-4\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:48 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:46 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:46 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id 9B8B53F703F;\n Tue, 26 Jan 2021 13:31:45 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=jR4Fl8H3gXvokndxQ2ImO9yxMybtJvRPYqjNRWQXDtM=;\n b=B0wVCa9kILuj/phWu5QL6fSKMtt17T9zi92Mgnfl0VL/lpxnhPYkBB7ZIE6+TRRPVL9c\n iLaAzmKw58amP8wqzK/ekrWx2q15NxtkfUBaW71kJa2c0BS+c7wqKn6dDBuWQAgWEVAJ\n brHP581hLCsHRT1JEUghgDHI6iqQGLcyN54GAppEJP7J6jCoLb1MAf7ZFRbWzjIbHkjj\n BUA5+A2LwOu7aoaneiqmz2HLajqiQPu/d4Vng8UJV3Y6D32P9jC629EbCS8+19QDgZtT\n kdwZPWh/VYRMF/w71QIbIjLdHqCajQByey2pIcMScdRb7fqi3zeGLxHYxuy1801MxrNk 1w==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:49 -0800", "Message-ID": "<20210126213051.57281-9-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 09/11] net/octeontx_ep: Added dev start and\n stop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Dev start and stop operations are added. To accomplish this internal\nfunctions to enable or disable io queues are incorporated.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx2_ep_vf.c | 107 ++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_common.h | 10 ++\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 48 +++++++++\n drivers/net/octeontx_ep/otx_ep_vf.c | 128 ++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.h | 4 +\n 5 files changed, 297 insertions(+)", "diff": "diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c\nindex 9349e66c0..9703ad023 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c\n@@ -190,6 +190,104 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\t rte_read32(droq->pkts_sent_reg));\n }\n \n+static int\n+otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* Resetting doorbells during IQ enabling also to handle abrupt\n+\t * guest reboot. IQ reset does not clear the doorbells.\n+\t */\n+\totx2_write64(0xFFFFFFFF, otx_ep->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile (((otx2_read64(otx_ep->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {\n+\t\trte_delay_ms(1);\n+\t}\n+\n+\tif (!loop) {\n+\t\totx_ep_err(\"INSTR DBELL not coming back to 0\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\n+\totx2_info(\"IQ[%d] enable done\", q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+\totx2_info(\"OQ[%d] enable done\", q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_vf_enable_io_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\tint ret;\n+\n+\tfor (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {\n+\t\tret = otx2_vf_enable_iq(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tfor (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++)\n+\t\totx2_vf_enable_oq(otx_ep, q_no);\n+\n+\treturn 0;\n+}\n+\n+static void\n+otx2_vf_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* Reset the doorbell register for this Input Queue. */\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+}\n+\n+static void\n+otx2_vf_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+}\n+\n+static void\n+otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {\n+\t\totx2_vf_disable_iq(otx_ep, q_no);\n+\t\totx2_vf_disable_oq(otx_ep, q_no);\n+\t}\n+}\n+\n static const struct otx_ep_config default_otx2_ep_conf = {\n \t/* IQ attributes */\n \t.iq = {\n@@ -249,5 +347,14 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;\n \n+\totx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues;\n+\totx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues;\n+\n+\totx_ep->fn_list.enable_iq = otx2_vf_enable_iq;\n+\totx_ep->fn_list.disable_iq = otx2_vf_disable_iq;\n+\n+\totx_ep->fn_list.enable_oq = otx2_vf_enable_oq;\n+\totx_ep->fn_list.disable_oq = otx2_vf_disable_oq;\n+\n \treturn 0;\n }\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 85fb946b3..51a6750c6 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -19,6 +19,7 @@\n #define OTX_EP_PCI_RING_ALIGN 65536\n #define SDP_PKIND 40\n #define SDP_OTX2_PKIND 57\n+#define OTX_EP_BUSY_LOOP_COUNT (10000)\n #define OTX_EP_MAX_IOQS_PER_VF 8\n \n #define otx_ep_info(fmt, args...)\t\t\t\t\\\n@@ -362,7 +363,14 @@ struct otx_ep_fn_list {\n \n \tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n \n+\tint (*enable_io_queues)(struct otx_ep_device *otx_ep);\n \tvoid (*disable_io_queues)(struct otx_ep_device *otx_ep);\n+\n+\tint (*enable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\tvoid (*disable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\n+\tint (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\tvoid (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n };\n \n /* SRIOV information */\n@@ -417,6 +425,8 @@ struct otx_ep_device {\n \t/* Device configuration */\n \tconst struct otx_ep_config *conf;\n \n+\tint started;\n+\n \tint port_configured;\n \n \tuint64_t rx_offloads;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex 33ddc1aed..5fa315e71 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -61,6 +61,50 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n \treturn 0;\n }\n \n+static int\n+otx_ep_dev_start(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf;\n+\tunsigned int q;\n+\tint ret;\n+\n+\totx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);\n+\t/* Enable IQ/OQ for this device */\n+\tret = otx_epvf->fn_list.enable_io_queues(otx_epvf);\n+\tif (ret) {\n+\t\totx_ep_err(\"IOQ enable failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tfor (q = 0; q < otx_epvf->nb_rx_queues; q++) {\n+\t\trte_write32(otx_epvf->droq[q]->nb_desc,\n+\t\t\t otx_epvf->droq[q]->pkts_credit_reg);\n+\n+\t\trte_wmb();\n+\t\totx_ep_info(\"OQ[%d] dbells [%d]\\n\", q,\n+\t\trte_read32(otx_epvf->droq[q]->pkts_credit_reg));\n+\t}\n+\n+\totx_epvf->started = 1;\n+\n+\trte_wmb();\n+\totx_ep_info(\"dev started\\n\");\n+\n+\treturn 0;\n+}\n+\n+/* Stop device and disable input/output functions */\n+static int\n+otx_ep_dev_stop(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\n+\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n+\totx_epvf->started = 0;\n+\n+\treturn 0;\n+}\n+\n static int\n otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n {\n@@ -308,6 +352,8 @@ otx_ep_tx_queue_release(void *txq)\n /* Define our ethernet definitions */\n static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.dev_configure\t\t= otx_ep_dev_configure,\n+\t.dev_start\t\t= otx_ep_dev_start,\n+\t.dev_stop\t\t= otx_ep_dev_stop,\n \t.rx_queue_setup\t = otx_ep_rx_queue_setup,\n \t.rx_queue_release\t= otx_ep_rx_queue_release,\n \t.tx_queue_setup\t = otx_ep_tx_queue_setup,\n@@ -327,6 +373,8 @@ otx_epdev_exit(struct rte_eth_dev *eth_dev)\n \n \totx_epvf = OTX_EP_DEV(eth_dev);\n \n+\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n+\n \tnum_queues = otx_epvf->nb_rx_queues;\n \tfor (q = 0; q < num_queues; q++) {\n \t\tif (otx_ep_delete_oqs(otx_epvf, q)) {\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c\nindex e5a747577..326187fa9 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.c\n@@ -205,6 +205,124 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t}\n }\n \n+static int\n+otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* Resetting doorbells during IQ enabling also to handle abrupt\n+\t * guest reboot. IQ reset does not clear the doorbells.\n+\t */\n+\totx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,\n+\t\t OTX_EP_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile (((rte_read64(otx_ep->hw_addr +\n+\t\t OTX_EP_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {\n+\t\trte_delay_ms(1);\n+\t}\n+\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"dbell reset failed\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));\n+\n+\totx_ep_info(\"IQ[%d] enable done\\n\", q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t reg_val = 0ull;\n+\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\n+\t/* Resetting doorbells during IQ enabling also to handle abrupt\n+\t * guest reboot. IQ reset does not clear the doorbells.\n+\t */\n+\totx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,\n+\t\t OTX_EP_R_OUT_SLIST_DBELL(q_no));\n+\twhile (((rte_read64(otx_ep->hw_addr +\n+\t\t OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {\n+\t\trte_delay_ms(1);\n+\t}\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"dbell reset failed\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));\n+\n+\totx_ep_info(\"OQ[%d] enable done\\n\", q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_enable_io_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\tint ret;\n+\n+\tfor (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {\n+\t\tret = otx_ep_enable_iq(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tfor (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) {\n+\t\tret = otx_ep_enable_oq(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+otx_ep_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* Reset the doorbell register for this Input Queue. */\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));\n+}\n+\n+static void\n+otx_ep_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));\n+}\n+\n+static void\n+otx_ep_disable_io_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {\n+\t\totx_ep_disable_iq(otx_ep, q_no);\n+\t\totx_ep_disable_oq(otx_ep, q_no);\n+\t}\n+}\n+\n /* OTX_EP default configuration */\n static const struct otx_ep_config default_otx_ep_conf = {\n \t/* IQ attributes */\n@@ -267,5 +385,15 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;\n \n+\totx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues;\n+\totx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues;\n+\n+\totx_ep->fn_list.enable_iq = otx_ep_enable_iq;\n+\totx_ep->fn_list.disable_iq = otx_ep_disable_iq;\n+\n+\totx_ep->fn_list.enable_oq = otx_ep_enable_oq;\n+\totx_ep->fn_list.disable_oq = otx_ep_disable_oq;\n+\n+\n \treturn 0;\n }\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h\nindex acc16753b..64e4df451 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.h\n@@ -12,6 +12,7 @@\n \n /* OTX_EP VF IQ Registers */\n #define OTX_EP_R_IN_CONTROL_START (0x10000)\n+#define OTX_EP_R_IN_ENABLE_START (0x10010)\n #define OTX_EP_R_IN_INSTR_BADDR_START (0x10020)\n #define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030)\n #define OTX_EP_R_IN_INSTR_DBELL_START (0x10040)\n@@ -21,6 +22,9 @@\n #define OTX_EP_R_IN_CONTROL(ring) \\\n \t(OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))\n \n+#define OTX_EP_R_IN_ENABLE(ring) \\\n+\t(OTX_EP_R_IN_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n #define OTX_EP_R_IN_INSTR_BADDR(ring) \\\n \t(OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))\n \n", "prefixes": [ "v3", "09/11" ] }