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GET /api/patches/87366/?format=api
{ "id": 87366, "url": "https://patches.dpdk.org/api/patches/87366/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-6-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-6-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-6-pnalla@marvell.com", "date": "2021-01-26T21:30:46", "name": "[v3,06/11] net/octeontx_ep: Added rxq setup and release", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f4769479d7dd9d5851feebddbecdbf62fe5eaf72", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-6-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87366/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87366/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3E172A052A;\n\tTue, 26 Jan 2021 22:32:54 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 39D79140D6C;\n\tTue, 26 Jan 2021 22:32:01 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5BA3D140D04\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:49 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QL0J6E025557 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:48 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 368m6uhds1-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:48 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:46 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:44 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id E86C53F7041;\n Tue, 26 Jan 2021 13:31:44 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=5Lk19iN445ljVikwWL34+s2vU+IEObD/PZMP6/QBPMs=;\n b=cdcDML6us6gy0TMzCJNjkRoggInP1VdYrWSTAXgpBh7C6jllFVddJ87QZRzQEhN6L9lo\n BBT81tc6uj+IT3IqkN4vfWb/2yQ4AizO3e6zAgaGs/FwEiX7uKsDA7n3292ahJmd6iRN\n mpFAJ3zsRTVzsHwivJZel1CfDb3yXQYaefNPMYClW9WAx1+5Dq9GjZTg0q6reibkRphk\n WcymU6RKZqJyh7WeFxFoIEIoXuvdowXvQRbkzNe0pq1YkH7BGpBu5DO6GEPUNrFEwOH/\n ZMwSdk0sh4ebWAutgkovP4UgKOekbX11lPsu4AI2cC2mWWwwl8VO4Uz3WLDssv2Uaof2 JQ==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:46 -0800", "Message-ID": "<20210126213051.57281-6-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 06/11] net/octeontx_ep: Added rxq setup and\n release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Receive queue setup involves allocating memory for the queue,\ninitializing data structure representing the queue and filling queue\nwith receive buffers of rx descriptor count. Receive queues are referred\nas droq. Hardware fills the receive buffers in queue with the packet.\n\nIn receive queue release, receive buffers are freed along with the\nreceive queue.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/meson.build | 1 +\n drivers/net/octeontx_ep/otx_ep_common.h | 160 ++++++++++++++++-\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 132 ++++++++++++++\n drivers/net/octeontx_ep/otx_ep_rxtx.c | 222 ++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.h | 6 +\n 5 files changed, 516 insertions(+), 5 deletions(-)\n create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.c", "diff": "diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build\nindex 8cd2e76d1..a8436f35f 100644\n--- a/drivers/net/octeontx_ep/meson.build\n+++ b/drivers/net/octeontx_ep/meson.build\n@@ -7,6 +7,7 @@ sources = files(\n 'otx_ep_ethdev.c',\n 'otx_ep_vf.c',\n 'otx2_ep_vf.c',\n+ 'otx_ep_rxtx.c',\n )\n \n includes += include_directories('../../common/octeontx2')\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 7f3c913f3..6be5c5a76 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -16,6 +16,10 @@\n \n #define OTX_EP_OQ_INFOPTR_MODE (0)\n #define OTX_EP_OQ_REFIL_THRESHOLD (16)\n+#define OTX_EP_PCI_RING_ALIGN 65536\n+#define SDP_PKIND 40\n+#define SDP_OTX2_PKIND 57\n+#define OTX_EP_MAX_IOQS_PER_VF 8\n \n #define otx_ep_info(fmt, args...)\t\t\t\t\\\n \tRTE_LOG(INFO, PMD, fmt \"\\n\", ## args)\n@@ -52,6 +56,65 @@ struct otx_ep_iq_config {\n \tuint32_t pending_list_size;\n };\n \n+/** Descriptor format.\n+ * The descriptor ring is made of descriptors which have 2 64-bit values:\n+ * -# Physical (bus) address of the data buffer.\n+ * -# Physical (bus) address of a otx_ep_droq_info structure.\n+ * The device DMA's incoming packets and its information at the address\n+ * given by these descriptor fields.\n+ */\n+struct otx_ep_droq_desc {\n+\t/* The buffer pointer */\n+\tuint64_t buffer_ptr;\n+\n+\t/* The Info pointer */\n+\tuint64_t info_ptr;\n+};\n+#define OTX_EP_DROQ_DESC_SIZE\t(sizeof(struct otx_ep_droq_desc))\n+\n+/* Receive Header */\n+union otx_ep_rh {\n+\tuint64_t rh64;\n+};\n+#define OTX_EP_RH_SIZE (sizeof(union otx_ep_rh))\n+\n+/** Information about packet DMA'ed by OCTEON TX2.\n+ * The format of the information available at Info Pointer after OCTEON TX2\n+ * has posted a packet. Not all descriptors have valid information. Only\n+ * the Info field of the first descriptor for a packet has information\n+ * about the packet.\n+ */\n+struct otx_ep_droq_info {\n+\t/* The Length of the packet. */\n+\tuint64_t length;\n+\n+\t/* The Output Receive Header. */\n+\tunion otx_ep_rh rh;\n+};\n+#define OTX_EP_DROQ_INFO_SIZE\t(sizeof(struct otx_ep_droq_info))\n+\n+\n+/* DROQ statistics. Each output queue has four stats fields. */\n+struct otx_ep_droq_stats {\n+\t/* Number of packets received in this queue. */\n+\tuint64_t pkts_received;\n+\n+\t/* Bytes received by this queue. */\n+\tuint64_t bytes_received;\n+\n+\t/* Num of failures of rte_pktmbuf_alloc() */\n+\tuint64_t rx_alloc_failure;\n+\n+\t/* Rx error */\n+\tuint64_t rx_err;\n+\n+\t/* packets with data got ready after interrupt arrived */\n+\tuint64_t pkts_delayed_data;\n+\n+\t/* packets dropped due to zero length */\n+\tuint64_t dropped_zlp;\n+};\n+\n /* Structure to define the configuration attributes for each Output queue. */\n struct otx_ep_oq_config {\n \t/* Max number of OQs available */\n@@ -67,6 +130,74 @@ struct otx_ep_oq_config {\n \tuint32_t refill_threshold;\n };\n \n+/* The Descriptor Ring Output Queue(DROQ) structure. */\n+struct otx_ep_droq {\n+\tstruct otx_ep_device *otx_ep_dev;\n+\t/* The 8B aligned descriptor ring starts at this address. */\n+\tstruct otx_ep_droq_desc *desc_ring;\n+\n+\tuint32_t q_no;\n+\tuint64_t last_pkt_count;\n+\n+\tstruct rte_mempool *mpool;\n+\n+\t/* Driver should read the next packet at this index */\n+\tuint32_t read_idx;\n+\n+\t/* OCTEON TX2 will write the next packet at this index */\n+\tuint32_t write_idx;\n+\n+\t/* At this index, the driver will refill the descriptor's buffer */\n+\tuint32_t refill_idx;\n+\n+\t/* Packets pending to be processed */\n+\tuint64_t pkts_pending;\n+\n+\t/* Number of descriptors in this ring. */\n+\tuint32_t nb_desc;\n+\n+\t/* The number of descriptors pending to refill. */\n+\tuint32_t refill_count;\n+\n+\tuint32_t refill_threshold;\n+\n+\t/* The 8B aligned info ptrs begin from this address. */\n+\tstruct otx_ep_droq_info *info_list;\n+\n+\t/* receive buffer list contains mbuf ptr list */\n+\tstruct rte_mbuf **recv_buf_list;\n+\n+\t/* The size of each buffer pointed by the buffer pointer. */\n+\tuint32_t buffer_size;\n+\n+\t/* Statistics for this DROQ. */\n+\tstruct otx_ep_droq_stats stats;\n+\n+\t/* DMA mapped address of the DROQ descriptor ring. */\n+\tsize_t desc_ring_dma;\n+\n+\t/* Info_ptr list is allocated at this virtual address. */\n+\tsize_t info_base_addr;\n+\n+\t/* DMA mapped address of the info list */\n+\tsize_t info_list_dma;\n+\n+\t/* Allocated size of info list. */\n+\tuint32_t info_alloc_size;\n+\n+\t/* Memory zone **/\n+\tconst struct rte_memzone *desc_ring_mz;\n+\tconst struct rte_memzone *info_mz;\n+};\n+#define OTX_EP_DROQ_SIZE\t\t(sizeof(struct otx_ep_droq))\n+\n+/* IQ/OQ mask */\n+struct otx_ep_io_enable {\n+\tuint64_t iq;\n+\tuint64_t oq;\n+\tuint64_t iq64B;\n+};\n+\n /* Structure to define the configuration. */\n struct otx_ep_config {\n \t/* Input Queue attributes. */\n@@ -85,6 +216,15 @@ struct otx_ep_config {\n \tuint32_t oqdef_buf_size;\n };\n \n+/* Required functions for each VF device */\n+struct otx_ep_fn_list {\n+\tvoid (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\n+\tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n+\n+\tvoid (*disable_io_queues)(struct otx_ep_device *otx_ep);\n+};\n+\n /* SRIOV information */\n struct otx_ep_sriov_info {\n \t/* Number of rings assigned to VF */\n@@ -94,11 +234,6 @@ struct otx_ep_sriov_info {\n \tuint32_t num_vfs;\n };\n \n-/* Required functions for each VF device */\n-struct otx_ep_fn_list {\n-\tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n-};\n-\n /* OTX_EP EP VF device data structure */\n struct otx_ep_device {\n \t/* PCI device pointer */\n@@ -106,6 +241,8 @@ struct otx_ep_device {\n \n \tuint16_t chip_id;\n \n+\tuint32_t pkind;\n+\n \tstruct rte_eth_dev *eth_dev;\n \n \tint port_id;\n@@ -119,6 +256,15 @@ struct otx_ep_device {\n \n \tuint32_t max_rx_queues;\n \n+\t/* Num OQs */\n+\tuint32_t nb_rx_queues;\n+\n+\t/* The DROQ output queues */\n+\tstruct otx_ep_droq *droq[OTX_EP_MAX_IOQS_PER_VF];\n+\n+\t/* IOQ mask */\n+\tstruct otx_ep_io_enable io_qmask;\n+\n \t/* SR-IOV info */\n \tstruct otx_ep_sriov_info sriov_info;\n \n@@ -132,6 +278,10 @@ struct otx_ep_device {\n \tuint64_t tx_offloads;\n };\n \n+int otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs,\n+\t\t int desc_size, struct rte_mempool *mpool,\n+\t\t unsigned int socket_id);\n+int otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no);\n #define OTX_EP_MAX_PKT_SZ 64000U\n \n #define OTX_EP_MAX_MAC_ADDRS 1\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex 4b6800fae..3e2df4035 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -72,11 +72,13 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \tcase PCI_DEVID_OCTEONTX_EP_VF:\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = otx_ep_vf_setup_device(otx_epvf);\n+\t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n \t\tbreak;\n \tcase PCI_DEVID_OCTEONTX2_EP_NET_VF:\n \tcase PCI_DEVID_CN98XX_EP_NET_VF:\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = otx2_ep_vf_setup_device(otx_epvf);\n+\t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n \t\tbreak;\n \tdefault:\n \t\totx_ep_err(\"Unsupported device\\n\");\n@@ -93,6 +95,8 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n static int\n otx_epdev_init(struct otx_ep_device *otx_epvf)\n {\n+\tuint32_t ethdev_queues;\n+\n \tif (otx_ep_chip_specific_setup(otx_epvf)) {\n \t\totx_ep_err(\"Chip specific setup failed\\n\");\n \t\tgoto setup_fail;\n@@ -103,6 +107,10 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \t\tgoto setup_fail;\n \t}\n \n+\tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n+\totx_epvf->max_rx_queues = ethdev_queues;\n+\totx_epvf->max_tx_queues = ethdev_queues;\n+\n \totx_ep_info(\"OTX_EP Device is Ready\\n\");\n \n \treturn 0;\n@@ -140,12 +148,125 @@ otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+/**\n+ * Setup our receive queue/ringbuffer. This is the\n+ * queue the Octeon uses to send us packets and\n+ * responses. We are given a memory pool for our\n+ * packet buffers that are used to populate the receive\n+ * queue.\n+ *\n+ * @param eth_dev\n+ * Pointer to the structure rte_eth_dev\n+ * @param q_no\n+ * Queue number\n+ * @param num_rx_descs\n+ * Number of entries in the queue\n+ * @param socket_id\n+ * Where to allocate memory\n+ * @param rx_conf\n+ * Pointer to the struction rte_eth_rxconf\n+ * @param mp\n+ * Pointer to the packet pool\n+ *\n+ * @return\n+ * - On success, return 0\n+ * - On failure, return -1\n+ */\n+static int\n+otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,\n+\t\t uint16_t num_rx_descs, unsigned int socket_id,\n+\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n+\t\t struct rte_mempool *mp)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\tstruct rte_pktmbuf_pool_private *mbp_priv;\n+\tuint16_t buf_size;\n+\n+\tif (q_no >= otx_epvf->max_rx_queues) {\n+\t\totx_ep_err(\"Invalid rx queue number %u\\n\", q_no);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (num_rx_descs & (num_rx_descs - 1)) {\n+\t\totx_ep_err(\"Invalid rx desc number should be pow 2 %u\\n\",\n+\t\t\t num_rx_descs);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (num_rx_descs < (SDP_GBL_WMARK * 8)) {\n+\t\totx_ep_err(\"Invalid rx desc number should at least be greater than 8xwmark %u\\n\",\n+\t\t\t num_rx_descs);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\totx_ep_dbg(\"setting up rx queue %u\\n\", q_no);\n+\n+\tmbp_priv = rte_mempool_get_priv(mp);\n+\tbuf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;\n+\n+\tif (otx_ep_setup_oqs(otx_epvf, q_no, num_rx_descs, buf_size, mp,\n+\t\t\t socket_id)) {\n+\t\totx_ep_err(\"droq allocation failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\teth_dev->data->rx_queues[q_no] = otx_epvf->droq[q_no];\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Release the receive queue/ringbuffer. Called by\n+ * the upper layers.\n+ *\n+ * @param rxq\n+ * Opaque pointer to the receive queue to release\n+ *\n+ * @return\n+ * - nothing\n+ */\n+static void\n+otx_ep_rx_queue_release(void *rxq)\n+{\n+\tstruct otx_ep_droq *rq = (struct otx_ep_droq *)rxq;\n+\tstruct otx_ep_device *otx_epvf = rq->otx_ep_dev;\n+\tint q_id = rq->q_no;\n+\n+\tif (otx_ep_delete_oqs(otx_epvf, q_id))\n+\t\totx_ep_err(\"Failed to delete OQ:%d\\n\", q_id);\n+}\n+\n /* Define our ethernet definitions */\n static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.dev_configure\t\t= otx_ep_dev_configure,\n+\t.rx_queue_setup\t = otx_ep_rx_queue_setup,\n+\t.rx_queue_release\t= otx_ep_rx_queue_release,\n \t.dev_infos_get\t\t= otx_ep_dev_info_get,\n };\n \n+\n+\n+static int\n+otx_epdev_exit(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf;\n+\tuint32_t num_queues, q;\n+\n+\totx_ep_info(\"%s:\\n\", __func__);\n+\n+\totx_epvf = OTX_EP_DEV(eth_dev);\n+\n+\tnum_queues = otx_epvf->nb_rx_queues;\n+\tfor (q = 0; q < num_queues; q++) {\n+\t\tif (otx_ep_delete_oqs(otx_epvf, q)) {\n+\t\t\totx_ep_err(\"Failed to delete OQ:%d\\n\", q);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\totx_ep_info(\"Num OQs:%d freed\\n\", otx_epvf->nb_rx_queues);\n+\n+\treturn 0;\n+}\n+\n static int\n otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n {\n@@ -153,11 +274,15 @@ otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n+\totx_epdev_exit(eth_dev);\n+\n \totx_epvf->port_configured = 0;\n \n \tif (eth_dev->data->mac_addrs != NULL)\n \t\trte_free(eth_dev->data->mac_addrs);\n \n+\teth_dev->dev_ops = NULL;\n+\n \treturn 0;\n }\n \n@@ -187,6 +312,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \teth_dev->data->mac_addrs = rte_zmalloc(\"otx_ep\", RTE_ETHER_ADDR_LEN, 0);\n \tif (eth_dev->data->mac_addrs == NULL) {\n \t\totx_ep_err(\"MAC addresses memory allocation failed\\n\");\n+\t\teth_dev->dev_ops = NULL;\n \t\treturn -ENOMEM;\n \t}\n \trte_eth_random_addr(vf_mac_addr);\n@@ -195,6 +321,12 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \totx_epvf->pdev = pdev;\n \n \totx_epdev_init(otx_epvf);\n+\tif (pdev->id.device_id == PCI_DEVID_OCTEONTX2_EP_NET_VF)\n+\t\totx_epvf->pkind = SDP_OTX2_PKIND;\n+\telse\n+\t\totx_epvf->pkind = SDP_PKIND;\n+\totx_ep_info(\"using pkind %d\\n\", otx_epvf->pkind);\n+\n \totx_epvf->port_configured = 0;\n \n \treturn 0;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.c b/drivers/net/octeontx_ep/otx_ep_rxtx.c\nnew file mode 100644\nindex 000000000..e5b228f26\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.c\n@@ -0,0 +1,222 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <unistd.h>\n+\n+#include <rte_eal.h>\n+#include <rte_mempool.h>\n+#include <rte_mbuf.h>\n+#include <rte_ethdev_pci.h>\n+\n+#include \"otx_ep_common.h\"\n+#include \"otx_ep_vf.h\"\n+#include \"otx2_ep_vf.h\"\n+#include \"otx_ep_rxtx.h\"\n+\n+static void\n+otx_ep_dmazone_free(const struct rte_memzone *mz)\n+{\n+\tconst struct rte_memzone *mz_tmp;\n+\tint ret = 0;\n+\n+\tif (mz == NULL) {\n+\t\totx_ep_err(\"Memzone %s : NULL\\n\", mz->name);\n+\t\treturn;\n+\t}\n+\n+\tmz_tmp = rte_memzone_lookup(mz->name);\n+\tif (mz_tmp == NULL) {\n+\t\totx_ep_err(\"Memzone %s Not Found\\n\", mz->name);\n+\t\treturn;\n+\t}\n+\n+\tret = rte_memzone_free(mz);\n+\tif (ret)\n+\t\totx_ep_err(\"Memzone free failed : ret = %d\\n\", ret);\n+}\n+\n+static void\n+otx_ep_droq_reset_indices(struct otx_ep_droq *droq)\n+{\n+\tdroq->read_idx = 0;\n+\tdroq->write_idx = 0;\n+\tdroq->refill_idx = 0;\n+\tdroq->refill_count = 0;\n+\tdroq->last_pkt_count = 0;\n+\tdroq->pkts_pending = 0;\n+}\n+\n+static void\n+otx_ep_droq_destroy_ring_buffers(struct otx_ep_droq *droq)\n+{\n+\tuint32_t idx;\n+\n+\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n+\t\tif (droq->recv_buf_list[idx]) {\n+\t\t\trte_pktmbuf_free(droq->recv_buf_list[idx]);\n+\t\t\tdroq->recv_buf_list[idx] = NULL;\n+\t\t}\n+\t}\n+\n+\totx_ep_droq_reset_indices(droq);\n+}\n+\n+/* Free OQs resources */\n+int\n+otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n+{\n+\tstruct otx_ep_droq *droq;\n+\n+\tdroq = otx_ep->droq[oq_no];\n+\tif (droq == NULL) {\n+\t\totx_ep_err(\"Invalid droq[%d]\\n\", oq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\totx_ep_droq_destroy_ring_buffers(droq);\n+\trte_free(droq->recv_buf_list);\n+\tdroq->recv_buf_list = NULL;\n+\n+\tif (droq->desc_ring_mz) {\n+\t\totx_ep_dmazone_free(droq->desc_ring_mz);\n+\t\tdroq->desc_ring_mz = NULL;\n+\t}\n+\n+\tmemset(droq, 0, OTX_EP_DROQ_SIZE);\n+\n+\trte_free(otx_ep->droq[oq_no]);\n+\totx_ep->droq[oq_no] = NULL;\n+\n+\totx_ep->nb_rx_queues--;\n+\n+\totx_ep_info(\"OQ[%d] is deleted\\n\", oq_no);\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq)\n+{\n+\tstruct otx_ep_droq_desc *desc_ring = droq->desc_ring;\n+\tstruct otx_ep_droq_info *info;\n+\tstruct rte_mbuf *buf;\n+\tuint32_t idx;\n+\n+\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n+\t\tbuf = rte_pktmbuf_alloc(droq->mpool);\n+\t\tif (buf == NULL) {\n+\t\t\totx_ep_err(\"OQ buffer alloc failed\\n\");\n+\t\t\tdroq->stats.rx_alloc_failure++;\n+\t\t\t/* otx_ep_droq_destroy_ring_buffers(droq);*/\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tdroq->recv_buf_list[idx] = buf;\n+\t\tinfo = rte_pktmbuf_mtod(buf, struct otx_ep_droq_info *);\n+\t\tmemset(info, 0, sizeof(*info));\n+\t\tdesc_ring[idx].buffer_ptr = rte_mbuf_data_iova_default(buf);\n+\t}\n+\n+\totx_ep_droq_reset_indices(droq);\n+\n+\treturn 0;\n+}\n+\n+/* OQ initialization */\n+static int\n+otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n+\t uint32_t num_descs, uint32_t desc_size,\n+\t struct rte_mempool *mpool, unsigned int socket_id)\n+{\n+\tconst struct otx_ep_config *conf = otx_ep->conf;\n+\tuint32_t c_refill_threshold;\n+\tstruct otx_ep_droq *droq;\n+\tuint32_t desc_ring_size;\n+\n+\totx_ep_info(\"OQ[%d] Init start\\n\", q_no);\n+\n+\tdroq = otx_ep->droq[q_no];\n+\tdroq->otx_ep_dev = otx_ep;\n+\tdroq->q_no = q_no;\n+\tdroq->mpool = mpool;\n+\n+\tdroq->nb_desc = num_descs;\n+\tdroq->buffer_size = desc_size;\n+\tc_refill_threshold = RTE_MAX(conf->oq.refill_threshold,\n+\t\t\t\t droq->nb_desc / 2);\n+\n+\t/* OQ desc_ring set up */\n+\tdesc_ring_size = droq->nb_desc * OTX_EP_DROQ_DESC_SIZE;\n+\tdroq->desc_ring_mz = rte_eth_dma_zone_reserve(otx_ep->eth_dev, \"droq\",\n+\t\t\t\t\t\t q_no, desc_ring_size,\n+\t\t\t\t\t\t OTX_EP_PCI_RING_ALIGN,\n+\t\t\t\t\t\t socket_id);\n+\n+\tif (droq->desc_ring_mz == NULL) {\n+\t\totx_ep_err(\"OQ:%d desc_ring allocation failed\\n\", q_no);\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+\tdroq->desc_ring_dma = droq->desc_ring_mz->iova;\n+\tdroq->desc_ring = (struct otx_ep_droq_desc *)droq->desc_ring_mz->addr;\n+\n+\totx_ep_dbg(\"OQ[%d]: desc_ring: virt: 0x%p, dma: %lx\\n\",\n+\t\t q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);\n+\totx_ep_dbg(\"OQ[%d]: num_desc: %d\\n\", q_no, droq->nb_desc);\n+\n+\t/* OQ buf_list set up */\n+\tdroq->recv_buf_list = rte_zmalloc_socket(\"recv_buf_list\",\n+\t\t\t\t(droq->nb_desc * sizeof(struct rte_mbuf *)),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (droq->recv_buf_list == NULL) {\n+\t\totx_ep_err(\"OQ recv_buf_list alloc failed\\n\");\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+\tif (otx_ep_droq_setup_ring_buffers(droq))\n+\t\tgoto init_droq_fail;\n+\n+\tdroq->refill_threshold = c_refill_threshold;\n+\n+\t/* Set up OQ registers */\n+\totx_ep->fn_list.setup_oq_regs(otx_ep, q_no);\n+\n+\totx_ep->io_qmask.oq |= (1ull << q_no);\n+\n+\treturn 0;\n+\n+init_droq_fail:\n+\treturn -ENOMEM;\n+}\n+\n+/* OQ configuration and setup */\n+int\n+otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs,\n+\t int desc_size, struct rte_mempool *mpool, unsigned int socket_id)\n+{\n+\tstruct otx_ep_droq *droq;\n+\n+\t/* Allocate new droq. */\n+\tdroq = (struct otx_ep_droq *)rte_zmalloc(\"otx_ep_OQ\",\n+\t\t\t\tsizeof(*droq), RTE_CACHE_LINE_SIZE);\n+\tif (droq == NULL) {\n+\t\totx_ep_err(\"Droq[%d] Creation Failed\\n\", oq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\totx_ep->droq[oq_no] = droq;\n+\n+\tif (otx_ep_init_droq(otx_ep, oq_no, num_descs, desc_size, mpool,\n+\t\t\t socket_id)) {\n+\t\totx_ep_err(\"Droq[%d] Initialization failed\\n\", oq_no);\n+\t\tgoto delete_OQ;\n+\t}\n+\totx_ep_info(\"OQ[%d] is created.\\n\", oq_no);\n+\n+\totx_ep->nb_rx_queues++;\n+\n+\treturn 0;\n+\n+delete_OQ:\n+\totx_ep_delete_oqs(otx_ep, oq_no);\n+\treturn -ENOMEM;\n+}\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h\nindex c5741a3f1..d17c87909 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.h\n@@ -37,6 +37,12 @@\n \n #define PCI_DEVID_OCTEONTX_EP_VF 0xa303\n \n+/* this is a static value set by SLI PF driver in octeon\n+ * No handshake is available\n+ * Change this if changing the value in SLI PF driver\n+ */\n+#define SDP_GBL_WMARK 0x100\n+\n int\n otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);\n #endif /*_OTX_EP_VF_H_ */\n", "prefixes": [ "v3", "06/11" ] }