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GET /api/patches/87362/?format=api
{ "id": 87362, "url": "https://patches.dpdk.org/api/patches/87362/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-8-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-8-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-8-pnalla@marvell.com", "date": "2021-01-26T21:30:48", "name": "[v3,08/11] net/octeontx_ep: Setting up iq and oq registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eded82a67e1eb4606d092230b449aca616916938", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-8-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87362/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87362/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 52567A052A;\n\tTue, 26 Jan 2021 22:32:21 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AE17A140D48;\n\tTue, 26 Jan 2021 22:31:55 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 39403140D0E\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:48 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QKxVBa013577 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:47 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 368j1u9psy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:47 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:45 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id 620153F7040;\n Tue, 26 Jan 2021 13:31:45 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=+S3DYdsAL8zAcGNbr0zyU/MKY8dcp8Q1MCiT6oZYKFQ=;\n b=TmZCFJHEW5UMonyNiqxfCT5lfcgC3+bfnWjcjTi01XxZqt8ZqwE7hUZyE9P+MfUupfwq\n QBmS8loeDLKsKodIB4mimw6uSbtthN5UxKr/lbC5RY0XtCeH4zRqlbTKR6CrIiyNzppq\n d9Vg973qy3LPQR5WzqGcZDNFRUF0MJ5P6xOvxyqbgE62dNbCATvsn7j2D5Ns2cuEpym8\n ykY8h9u4TrL8ko5WwSx15jCOnVt11WwXwTC3JAEhBgZUnNyQRPMXhj6JZ+iNDmAWj2an\n KxnGYtN1OfGPjZQM+zKbuvQSab7BG/zRLwJ7wvjdurTZkS3NFYWX7Tgjb442eBY/X6G9 VA==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:48 -0800", "Message-ID": "<20210126213051.57281-8-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 08/11] net/octeontx_ep: Setting up iq and oq\n registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Configuring hardware registers with command queue(iq) and droq(oq)\nparameters.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx2_ep_vf.c | 120 +++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_common.h | 65 +++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.c | 121 ++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.h | 53 +++++++++++\n 4 files changed, 359 insertions(+)", "diff": "diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c\nindex e793c04fb..9349e66c0 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c\n@@ -73,6 +73,123 @@ otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)\n \treturn 0;\n }\n \n+static void\n+otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n+{\n+\tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));\n+\n+\t/* Wait till IDLE to set to 1, not supposed to configure BADDR\n+\t * as long as IDLE is 0\n+\t */\n+\tif (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {\n+\t\tdo {\n+\t\t\treg_val = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t\t SDP_VF_R_IN_CONTROL(iq_no));\n+\t\t} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));\n+\t}\n+\n+\t/* Write the start of the input queue's ring and its size */\n+\totx2_write64(iq->base_addr_dma, otx_ep->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_BADDR(iq_no));\n+\totx2_write64(iq->nb_desc, otx_ep->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_RSIZE(iq_no));\n+\n+\t/* Remember the doorbell & instruction count register addr\n+\t * for this queue\n+\t */\n+\tiq->doorbell_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t SDP_VF_R_IN_INSTR_DBELL(iq_no);\n+\tiq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t SDP_VF_R_IN_CNTS(iq_no);\n+\n+\totx_ep_dbg(\"InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\",\n+\t\t iq_no, iq->doorbell_reg, iq->inst_cnt_reg);\n+\n+\tdo {\n+\t\treg_val = rte_read32(iq->inst_cnt_reg);\n+\t\trte_write32(reg_val, iq->inst_cnt_reg);\n+\t} while (reg_val != 0);\n+\n+\t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n+\t * to raise\n+\t */\n+\totx2_write64(0x3FFFFFFFFFFFFFUL,\n+\t\t otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n+}\n+\n+static void\n+otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t oq_ctl = 0ull;\n+\tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n+\n+\t/* Wait on IDLE to set to 1, supposed to configure BADDR\n+\t * as log as IDLE is 0\n+\t */\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\twhile (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {\n+\t\treg_val = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t SDP_VF_R_OUT_CONTROL(oq_no));\n+\t}\n+\n+\totx2_write64(droq->desc_ring_dma, otx_ep->hw_addr +\n+\t\t SDP_VF_R_OUT_SLIST_BADDR(oq_no));\n+\totx2_write64(droq->nb_desc, otx_ep->hw_addr +\n+\t\t SDP_VF_R_OUT_SLIST_RSIZE(oq_no));\n+\n+\toq_ctl = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\t/* Clear the ISIZE and BSIZE (22-0) */\n+\toq_ctl &= ~(0x7fffffull);\n+\n+\t/* Populate the BSIZE (15-0) */\n+\toq_ctl |= (droq->buffer_size & 0xffff);\n+\n+\totx2_write64(oq_ctl, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\t/* Mapped address of the pkt_sent and pkts_credit regs */\n+\tdroq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t SDP_VF_R_OUT_CNTS(oq_no);\n+\tdroq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_SLIST_DBELL(oq_no);\n+\n+\trte_write64(0x3FFFFFFFFFFFFFUL,\n+\t\t otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));\n+\n+\t/* Clear PKT_CNT register */\n+\trte_write64(0xFFFFFFFFF, (uint8_t *)otx_ep->hw_addr +\n+\t\t SDP_VF_R_OUT_PKT_CNT(oq_no));\n+\n+\t/* Clear the OQ doorbell */\n+\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull)) {\n+\t\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+\totx_ep_dbg(\"SDP_R[%d]_credit:%x\", oq_no,\n+\t\t rte_read32(droq->pkts_credit_reg));\n+\n+\t/* Clear the OQ_OUT_CNTS doorbell */\n+\treg_val = rte_read32(droq->pkts_sent_reg);\n+\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\n+\totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no,\n+\t\t rte_read32(droq->pkts_sent_reg));\n+\n+\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n+\t\treg_val = rte_read32(droq->pkts_sent_reg);\n+\t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+\totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no,\n+\t\t rte_read32(droq->pkts_sent_reg));\n+}\n+\n static const struct otx_ep_config default_otx2_ep_conf = {\n \t/* IQ attributes */\n \t.iq = {\n@@ -127,6 +244,9 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx2_info(\"SDP RPVF: %d\", otx_ep->sriov_info.rings_per_vf);\n \n+\totx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs;\n+\totx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs;\n+\n \totx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;\n \n \treturn 0;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex e1b4ff270..85fb946b3 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -33,6 +33,33 @@\n \t\t\"%s():%u \" fmt \"\\n\",\t\t\t\t\\\n \t\t__func__, __LINE__, ##args)\n \n+/* Input Request Header format */\n+union otx_ep_instr_irh {\n+\tuint64_t u64;\n+\tstruct {\n+\t\t/* Request ID */\n+\t\tuint64_t rid:16;\n+\n+\t\t/* PCIe port to use for response */\n+\t\tuint64_t pcie_port:3;\n+\n+\t\t/* Scatter indicator 1=scatter */\n+\t\tuint64_t scatter:1;\n+\n+\t\t/* Size of Expected result OR no. of entries in scatter list */\n+\t\tuint64_t rlenssz:14;\n+\n+\t\t/* Desired destination port for result */\n+\t\tuint64_t dport:6;\n+\n+\t\t/* Opcode Specific parameters */\n+\t\tuint64_t param:8;\n+\n+\t\t/* Opcode for the return packet */\n+\t\tuint64_t opcode:16;\n+\t} s;\n+};\n+\n #define otx_ep_write64(value, base_addr, reg_off) \\\n \t{\\\n \ttypeof(value) val = (value); \\\n@@ -42,6 +69,33 @@\n \trte_write64(val, ((base_addr) + off)); \\\n \t}\n \n+/* Instruction Header - for OCTEON-TX models */\n+typedef union otx_ep_instr_ih {\n+\tuint64_t u64;\n+\tstruct {\n+\t /** Data Len */\n+\t\tuint64_t tlen:16;\n+\n+\t /** Reserved */\n+\t\tuint64_t rsvd:20;\n+\n+\t /** PKIND for OTX_EP */\n+\t\tuint64_t pkind:6;\n+\n+\t /** Front Data size */\n+\t\tuint64_t fsz:6;\n+\n+\t /** No. of entries in gather list */\n+\t\tuint64_t gsz:14;\n+\n+\t /** Gather indicator 1=gather*/\n+\t\tuint64_t gather:1;\n+\n+\t /** Reserved3 */\n+\t\tuint64_t reserved3:1;\n+\t} s;\n+} otx_ep_instr_ih_t;\n+\n /* OTX_EP IQ request list */\n struct otx_ep_instr_list {\n \tvoid *buf;\n@@ -244,6 +298,16 @@ struct otx_ep_droq {\n \t/* The size of each buffer pointed by the buffer pointer. */\n \tuint32_t buffer_size;\n \n+\t/** Pointer to the mapped packet credit register.\n+\t * Host writes number of info/buffer ptrs available to this register\n+\t */\n+\tvoid *pkts_credit_reg;\n+\n+\t/** Pointer to the mapped packet sent register. OCTEON TX2 writes the\n+\t * number of packets DMA'ed to host memory in this register.\n+\t */\n+\tvoid *pkts_sent_reg;\n+\n \t/* Statistics for this DROQ. */\n \tstruct otx_ep_droq_stats stats;\n \n@@ -259,6 +323,7 @@ struct otx_ep_droq {\n \t/* Allocated size of info list. */\n \tuint32_t info_alloc_size;\n \n+\n \t/* Memory zone **/\n \tconst struct rte_memzone *desc_ring_mz;\n \tconst struct rte_memzone *info_mz;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c\nindex 0bf8e5bed..e5a747577 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.c\n@@ -87,6 +87,124 @@ otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)\n \treturn 0;\n }\n \n+static void\n+otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n+{\n+\tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));\n+\n+\t/* Wait till IDLE to set to 1, not supposed to configure BADDR\n+\t * as long as IDLE is 0\n+\t */\n+\tif (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {\n+\t\tdo {\n+\t\t\treg_val = rte_read64(otx_ep->hw_addr +\n+\t\t\t\t\t OTX_EP_R_IN_CONTROL(iq_no));\n+\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));\n+\t}\n+\n+\t/* Write the start of the input queue's ring and its size */\n+\totx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr,\n+\t\t OTX_EP_R_IN_INSTR_BADDR(iq_no));\n+\totx_ep_write64(iq->nb_desc, otx_ep->hw_addr,\n+\t\t OTX_EP_R_IN_INSTR_RSIZE(iq_no));\n+\n+\t/* Remember the doorbell & instruction count register addr\n+\t * for this queue\n+\t */\n+\tiq->doorbell_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t OTX_EP_R_IN_INSTR_DBELL(iq_no);\n+\tiq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t OTX_EP_R_IN_CNTS(iq_no);\n+\n+\totx_ep_dbg(\"InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\\n\",\n+\t\t iq_no, iq->doorbell_reg, iq->inst_cnt_reg);\n+\n+\tdo {\n+\t\treg_val = rte_read32(iq->inst_cnt_reg);\n+\t\trte_write32(reg_val, iq->inst_cnt_reg);\n+\t} while (reg_val != 0);\n+\n+\t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n+\t * to raise\n+\t */\n+\t/* reg_val = rte_read64(otx_ep->hw_addr +\n+\t * OTX_EP_R_IN_INT_LEVELS(iq_no));\n+\t */\n+\treg_val = 0xffffffff;\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_INT_LEVELS(iq_no));\n+}\n+\n+static void\n+otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t oq_ctl = 0ull;\n+\n+\tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n+\n+\t/* Wait on IDLE to set to 1, supposed to configure BADDR\n+\t * as log as IDLE is 0\n+\t */\n+\totx_ep_write64(0ULL, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(oq_no));\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));\n+\n+\twhile (!(reg_val & OTX_EP_R_OUT_CTL_IDLE)) {\n+\t\treg_val = rte_read64(otx_ep->hw_addr +\n+\t\t\t\t OTX_EP_R_OUT_CONTROL(oq_no));\n+\t}\n+\n+\totx_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr,\n+\t\t OTX_EP_R_OUT_SLIST_BADDR(oq_no));\n+\totx_ep_write64(droq->nb_desc, otx_ep->hw_addr,\n+\t\t OTX_EP_R_OUT_SLIST_RSIZE(oq_no));\n+\n+\toq_ctl = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));\n+\n+\t/* Clear the ISIZE and BSIZE (22-0) */\n+\toq_ctl &= ~(0x7fffffull);\n+\n+\t/* Populate the BSIZE (15-0) */\n+\toq_ctl |= (droq->buffer_size & 0xffff);\n+\n+\totx_ep_write64(oq_ctl, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(oq_no));\n+\n+\t/* Mapped address of the pkt_sent and pkts_credit regs */\n+\tdroq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t OTX_EP_R_OUT_CNTS(oq_no);\n+\tdroq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +\n+\t\t\t\tOTX_EP_R_OUT_SLIST_DBELL(oq_no);\n+\n+\totx_ep_write64(0x3fffffffffffffULL, otx_ep->hw_addr,\n+\t\t OTX_EP_R_OUT_INT_LEVELS(oq_no));\n+\n+\t/* Clear the OQ doorbell */\n+\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull)) {\n+\t\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+\totx_ep_dbg(\"OTX_EP_R[%d]_credit:%x\\n\", oq_no,\n+\t\t rte_read32(droq->pkts_credit_reg));\n+\n+\t/* Clear the OQ_OUT_CNTS doorbell */\n+\treg_val = rte_read32(droq->pkts_sent_reg);\n+\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\n+\totx_ep_dbg(\"OTX_EP_R[%d]_sent: %x\\n\", oq_no,\n+\t\t rte_read32(droq->pkts_sent_reg));\n+\n+\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n+\t\treg_val = rte_read32(droq->pkts_sent_reg);\n+\t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+}\n+\n /* OTX_EP default configuration */\n static const struct otx_ep_config default_otx_ep_conf = {\n \t/* IQ attributes */\n@@ -144,6 +262,9 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx_ep_info(\"OTX_EP RPVF: %d\\n\", otx_ep->sriov_info.rings_per_vf);\n \n+\totx_ep->fn_list.setup_iq_regs = otx_ep_setup_iq_regs;\n+\totx_ep->fn_list.setup_oq_regs = otx_ep_setup_oq_regs;\n+\n \totx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;\n \n \treturn 0;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h\nindex d17c87909..acc16753b 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.h\n@@ -4,13 +4,38 @@\n #ifndef _OTX_EP_VF_H_\n #define _OTX_EP_VF_H_\n \n+\n+\n+\n+\n #define OTX_EP_RING_OFFSET (0x1ull << 17)\n \n /* OTX_EP VF IQ Registers */\n #define OTX_EP_R_IN_CONTROL_START (0x10000)\n+#define OTX_EP_R_IN_INSTR_BADDR_START (0x10020)\n+#define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030)\n+#define OTX_EP_R_IN_INSTR_DBELL_START (0x10040)\n+#define OTX_EP_R_IN_CNTS_START (0x10050)\n+#define OTX_EP_R_IN_INT_LEVELS_START (0x10060)\n+\n #define OTX_EP_R_IN_CONTROL(ring) \\\n \t(OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))\n \n+#define OTX_EP_R_IN_INSTR_BADDR(ring) \\\n+\t(OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_IN_INSTR_RSIZE(ring) \\\n+\t(OTX_EP_R_IN_INSTR_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_IN_INSTR_DBELL(ring) \\\n+\t(OTX_EP_R_IN_INSTR_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_IN_CNTS(ring) \\\n+\t(OTX_EP_R_IN_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_IN_INT_LEVELS(ring) \\\n+\t(OTX_EP_R_IN_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n /* OTX_EP VF IQ Masks */\n #define OTX_EP_R_IN_CTL_RPVF_MASK (0xF)\n #define\tOTX_EP_R_IN_CTL_RPVF_POS (48)\n@@ -20,10 +45,38 @@\n #define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24)\n #define OTX_EP_R_IN_CTL_ESR (0x1ull << 1)\n /* OTX_EP VF OQ Registers */\n+#define OTX_EP_R_OUT_CNTS_START (0x10100)\n+#define OTX_EP_R_OUT_INT_LEVELS_START (0x10110)\n+#define OTX_EP_R_OUT_SLIST_BADDR_START (0x10120)\n+#define OTX_EP_R_OUT_SLIST_RSIZE_START (0x10130)\n+#define OTX_EP_R_OUT_SLIST_DBELL_START (0x10140)\n #define OTX_EP_R_OUT_CONTROL_START (0x10150)\n+#define OTX_EP_R_OUT_ENABLE_START (0x10160)\n+\n #define OTX_EP_R_OUT_CONTROL(ring) \\\n \t(OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_ENABLE(ring) \\\n+\t(OTX_EP_R_OUT_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_SLIST_BADDR(ring) \\\n+\t(OTX_EP_R_OUT_SLIST_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_SLIST_RSIZE(ring) \\\n+\t(OTX_EP_R_OUT_SLIST_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_SLIST_DBELL(ring) \\\n+\t(OTX_EP_R_OUT_SLIST_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_CNTS(ring) \\\n+\t(OTX_EP_R_OUT_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+#define OTX_EP_R_OUT_INT_LEVELS(ring) \\\n+\t(OTX_EP_R_OUT_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n /* OTX_EP VF OQ Masks */\n+\n+#define OTX_EP_R_OUT_CTL_IDLE (1ull << 36)\n #define OTX_EP_R_OUT_CTL_ES_I (1ull << 34)\n #define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33)\n #define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32)\n", "prefixes": [ "v3", "08/11" ] }