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GET /api/patches/87360/?format=api
{ "id": 87360, "url": "https://patches.dpdk.org/api/patches/87360/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-4-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-4-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-4-pnalla@marvell.com", "date": "2021-01-26T21:30:44", "name": "[v3,04/11] net/octeontx_ep: Added basic device setup.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f0621901155df20f9da097becca06d2fee41f983", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-4-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87360/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87360/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7D2E5A052A;\n\tTue, 26 Jan 2021 22:32:04 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DE43F140D22;\n\tTue, 26 Jan 2021 22:31:51 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 676D9140D0B\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:47 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QKxVBZ013577 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:46 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 368j1u9psv-4\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:46 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:44 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:44 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id 75FE73F7043;\n Tue, 26 Jan 2021 13:31:44 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=Qwwb2bRMHCCWZpMaarLgwXM2xo/c8IQ2D+s/jSxVW/4=;\n b=iCiW6oOWwSGk264yLpF2BNEJsnI3VBjyNZJww5LtdyTo41lkFZEJ6IGSxgRmDOUScUCL\n Mh2Ph5/QAw13ZZv7WCsRi4WXovYVoA4C+Q724UiS8TG9GChlmAzhyYm9Xyl5GkGy2sLM\n tNpPWgdhB5rhRS+aMeYBqRKpkiF4lCTjGJe1IeybM2i1C/mTl/zPM45asnQk3SDm2lZC\n 57wNos8i3FezuXI03V6s1R6qX0dtMBEx+/j9WmGtSWV79NDKqnIe8BNjB4QgNomX4Oio\n tN0lOuIUahzeKxcKG8B4k8t0ZzIQvon/OKKAhC/9izZESndFkGPEN2YoMg0F7BUI95rc Kg==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:44 -0800", "Message-ID": "<20210126213051.57281-4-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 04/11] net/octeontx_ep: Added basic device\n setup.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Functions to setup device, basic IQ and OQ registers are added.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/meson.build | 2 +\n drivers/net/octeontx_ep/otx2_ep_vf.c | 133 +++++++++++++++++++++\n drivers/net/octeontx_ep/otx2_ep_vf.h | 11 ++\n drivers/net/octeontx_ep/otx_ep_common.h | 97 ++++++++++++++-\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 11 ++\n drivers/net/octeontx_ep/otx_ep_vf.c | 150 ++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.h | 33 ++++++\n 7 files changed, 434 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.c\n create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.h\n create mode 100644 drivers/net/octeontx_ep/otx_ep_vf.c", "diff": "diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build\nindex 73e04b0be..8cd2e76d1 100644\n--- a/drivers/net/octeontx_ep/meson.build\n+++ b/drivers/net/octeontx_ep/meson.build\n@@ -5,6 +5,8 @@\n deps += ['common_octeontx2']\n sources = files(\n 'otx_ep_ethdev.c',\n+ 'otx_ep_vf.c',\n+ 'otx2_ep_vf.c',\n )\n \n includes += include_directories('../../common/octeontx2')\ndiff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c\nnew file mode 100644\nindex 000000000..e793c04fb\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c\n@@ -0,0 +1,133 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"otx2_common.h\"\n+#include \"otx_ep_common.h\"\n+#include \"otx2_ep_vf.h\"\n+\n+static void\n+otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\t/* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs\n+\t * IS_64B is by default enabled.\n+\t */\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n+\n+\treg_val |= SDP_VF_R_IN_CTL_RDSIZE;\n+\treg_val |= SDP_VF_R_IN_CTL_IS_64B;\n+\treg_val |= SDP_VF_R_IN_CTL_ESR;\n+\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n+}\n+\n+static void\n+otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n+\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_IMODE);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);\n+\n+\t/* INFO/DATA ptr swap is required */\n+\treg_val |= (SDP_VF_R_OUT_CTL_ES_P);\n+\n+\totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n+}\n+\n+static void\n+otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n+\t\totx2_vf_setup_global_iq_reg(otx_ep, q_no);\n+}\n+\n+static void\n+otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no;\n+\n+\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n+\t\totx2_vf_setup_global_oq_reg(otx_ep, q_no);\n+}\n+\n+static int\n+otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)\n+{\n+\totx2_vf_setup_global_input_regs(otx_ep);\n+\totx2_vf_setup_global_output_regs(otx_ep);\n+\n+\treturn 0;\n+}\n+\n+static const struct otx_ep_config default_otx2_ep_conf = {\n+\t/* IQ attributes */\n+\t.iq = {\n+\t\t.max_iqs = OTX_EP_CFG_IO_QUEUES,\n+\t\t.instr_type = OTX_EP_64BYTE_INSTR,\n+\t\t.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *\n+\t\t\t\t OTX_EP_CFG_IO_QUEUES),\n+\t},\n+\n+\t/* OQ attributes */\n+\t.oq = {\n+\t\t.max_oqs = OTX_EP_CFG_IO_QUEUES,\n+\t\t.info_ptr = OTX_EP_OQ_INFOPTR_MODE,\n+\t\t.refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,\n+\t},\n+\n+\t.num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,\n+\t.num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,\n+\t.oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,\n+};\n+\n+static const struct otx_ep_config*\n+otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)\n+{\n+\tconst struct otx_ep_config *default_conf = NULL;\n+\n+\tdefault_conf = &default_otx2_ep_conf;\n+\n+\treturn default_conf;\n+}\n+\n+int\n+otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* If application doesn't provide its conf, use driver default conf */\n+\tif (otx_ep->conf == NULL) {\n+\t\totx_ep->conf = otx2_ep_get_defconf(otx_ep);\n+\t\tif (otx_ep->conf == NULL) {\n+\t\t\totx2_err(\"SDP VF default config not found\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\totx2_info(\"Default config is used\");\n+\t}\n+\n+\t/* Get IOQs (RPVF] count */\n+\treg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(0));\n+\n+\totx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)\n+\t\t\t\t\t & SDP_VF_R_IN_CTL_RPVF_MASK);\n+\n+\totx2_info(\"SDP RPVF: %d\", otx_ep->sriov_info.rings_per_vf);\n+\n+\totx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h\nnew file mode 100644\nindex 000000000..191fee426\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef _OTX2_EP_VF_H_\n+#define _OTX2_EP_VF_H_\n+\n+int\n+otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);\n+\n+#endif /*_OTX2_EP_VF_H_ */\n+\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex f84ab88db..74f9e10b1 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -4,9 +4,15 @@\n #ifndef _OTX_EP_COMMON_H_\n #define _OTX_EP_COMMON_H_\n \n-#define otx_ep_printf(level, fmt, args...)\t\t\t\\\n-\trte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD,\t\t\\\n-\t\t fmt, ##args)\n+#define OTX_EP_MAX_RINGS_PER_VF (8)\n+#define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF\n+#define OTX_EP_64BYTE_INSTR (64)\n+#define OTX_EP_MAX_IQ_DESCRIPTORS (8192)\n+#define OTX_EP_MAX_OQ_DESCRIPTORS (8192)\n+#define OTX_EP_OQ_BUF_SIZE (2048)\n+\n+#define OTX_EP_OQ_INFOPTR_MODE (0)\n+#define OTX_EP_OQ_REFIL_THRESHOLD (16)\n \n #define otx_ep_info(fmt, args...)\t\t\t\t\\\n \tRTE_LOG(INFO, PMD, fmt \"\\n\", ## args)\n@@ -20,15 +26,100 @@\n \t\t\"%s():%u \" fmt \"\\n\",\t\t\t\t\\\n \t\t__func__, __LINE__, ##args)\n \n+#define otx_ep_write64(value, base_addr, reg_off) \\\n+\t{\\\n+\ttypeof(value) val = (value); \\\n+\ttypeof(reg_off) off = (reg_off); \\\n+\totx_ep_dbg(\"octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\\n\", \\\n+\t\t (unsigned long)off, (unsigned long long)val); \\\n+\trte_write64(val, ((base_addr) + off)); \\\n+\t}\n+\n+struct otx_ep_device;\n+\n+/* Structure to define the configuration attributes for each Input queue. */\n+struct otx_ep_iq_config {\n+\t/* Max number of IQs available */\n+\tuint16_t max_iqs;\n+\n+\t/* Command size - 32 or 64 bytes */\n+\tuint16_t instr_type;\n+\n+\t/* Pending list size, usually set to the sum of the size of all IQs */\n+\tuint32_t pending_list_size;\n+};\n+\n+/* Structure to define the configuration attributes for each Output queue. */\n+struct otx_ep_oq_config {\n+\t/* Max number of OQs available */\n+\tuint16_t max_oqs;\n+\n+\t/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */\n+\tuint16_t info_ptr;\n+\n+\t/** The number of buffers that were consumed during packet processing by\n+\t * the driver on this Output queue before the driver attempts to\n+\t * replenish the descriptor ring with new buffers.\n+\t */\n+\tuint32_t refill_threshold;\n+};\n+\n+/* Structure to define the configuration. */\n+struct otx_ep_config {\n+\t/* Input Queue attributes. */\n+\tstruct otx_ep_iq_config iq;\n+\n+\t/* Output Queue attributes. */\n+\tstruct otx_ep_oq_config oq;\n+\n+\t/* Num of desc for IQ rings */\n+\tuint32_t num_iqdef_descs;\n+\n+\t/* Num of desc for OQ rings */\n+\tuint32_t num_oqdef_descs;\n+\n+\t/* OQ buffer size */\n+\tuint32_t oqdef_buf_size;\n+};\n+\n+/* SRIOV information */\n+struct otx_ep_sriov_info {\n+\t/* Number of rings assigned to VF */\n+\tuint32_t rings_per_vf;\n+\n+\t/* Number of VF devices enabled */\n+\tuint32_t num_vfs;\n+};\n+\n+/* Required functions for each VF device */\n+struct otx_ep_fn_list {\n+\tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n+};\n+\n /* OTX_EP EP VF device data structure */\n struct otx_ep_device {\n \t/* PCI device pointer */\n \tstruct rte_pci_device *pdev;\n+\n \tuint16_t chip_id;\n+\n \tstruct rte_eth_dev *eth_dev;\n+\n \tint port_id;\n+\n \t/* Memory mapped h/w address */\n \tuint8_t *hw_addr;\n+\n+\tstruct otx_ep_fn_list fn_list;\n+\n+\t/* SR-IOV info */\n+\tstruct otx_ep_sriov_info sriov_info;\n+\n+\t/* Device configuration */\n+\tconst struct otx_ep_config *conf;\n+\n \tint port_configured;\n };\n+\n+extern int otx_net_ep_logtype;\n #endif /* _OTX_EP_COMMON_H_ */\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex adb3ec2ee..c90ef13c0 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -9,6 +9,7 @@\n #include \"otx2_common.h\"\n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n+#include \"otx2_ep_vf.h\"\n \n #define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)\n static int\n@@ -21,10 +22,12 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \tswitch (dev_id) {\n \tcase PCI_DEVID_OCTEONTX_EP_VF:\n \t\totx_epvf->chip_id = dev_id;\n+\t\tret = otx_ep_vf_setup_device(otx_epvf);\n \t\tbreak;\n \tcase PCI_DEVID_OCTEONTX2_EP_NET_VF:\n \tcase PCI_DEVID_CN98XX_EP_NET_VF:\n \t\totx_epvf->chip_id = dev_id;\n+\t\tret = otx2_ep_vf_setup_device(otx_epvf);\n \t\tbreak;\n \tdefault:\n \t\totx_ep_err(\"Unsupported device\\n\");\n@@ -46,6 +49,13 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \t\tgoto setup_fail;\n \t}\n \n+\tif (otx_epvf->fn_list.setup_device_regs(otx_epvf)) {\n+\t\totx_ep_err(\"Failed to configure device registers\\n\");\n+\t\tgoto setup_fail;\n+\t}\n+\n+\totx_ep_info(\"OTX_EP Device is Ready\\n\");\n+\n \treturn 0;\n \n setup_fail:\n@@ -141,3 +151,4 @@ static struct rte_pci_driver rte_otx_ep_pmd = {\n RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);\n RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, \"* igb_uio | vfio-pci\");\n+RTE_LOG_REGISTER(otx_net_ep_logtype, pmd.net.octeontx_ep, NOTICE);\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c\nnew file mode 100644\nindex 000000000..0bf8e5bed\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.c\n@@ -0,0 +1,150 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_ethdev_pci.h>\n+#include <rte_io.h>\n+\n+#include \"otx_ep_common.h\"\n+#include \"otx_ep_vf.h\"\n+\n+\n+static void\n+otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\t/* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs\n+\t * IS_64B is by default enabled.\n+\t */\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));\n+\n+\treg_val |= OTX_EP_R_IN_CTL_RDSIZE;\n+\treg_val |= OTX_EP_R_IN_CTL_IS_64B;\n+\treg_val |= OTX_EP_R_IN_CTL_ESR;\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_CONTROL(q_no));\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));\n+\n+\tif (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {\n+\t\tdo {\n+\t\t\treg_val = rte_read64(otx_ep->hw_addr +\n+\t\t\t\t\t OTX_EP_R_IN_CONTROL(q_no));\n+\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));\n+\t}\n+}\n+\n+static void\n+otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(q_no));\n+\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_IMODE);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_ROR_P);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_NSR_P);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_ROR_I);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_NSR_I);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_ES_I);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_ROR_D);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_NSR_D);\n+\treg_val &= ~(OTX_EP_R_OUT_CTL_ES_D);\n+\n+\t/* INFO/DATA ptr swap is required */\n+\treg_val |= (OTX_EP_R_OUT_CTL_ES_P);\n+\n+\totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));\n+}\n+\n+static void\n+otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n+\t\totx_ep_setup_global_iq_reg(otx_ep, q_no);\n+}\n+\n+static void\n+otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no;\n+\n+\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n+\t\totx_ep_setup_global_oq_reg(otx_ep, q_no);\n+}\n+\n+static int\n+otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)\n+{\n+\totx_ep_setup_global_input_regs(otx_ep);\n+\totx_ep_setup_global_output_regs(otx_ep);\n+\n+\treturn 0;\n+}\n+\n+/* OTX_EP default configuration */\n+static const struct otx_ep_config default_otx_ep_conf = {\n+\t/* IQ attributes */\n+\t.iq = {\n+\t\t.max_iqs = OTX_EP_CFG_IO_QUEUES,\n+\t\t.instr_type = OTX_EP_64BYTE_INSTR,\n+\t\t.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *\n+\t\t\t\t OTX_EP_CFG_IO_QUEUES),\n+\t},\n+\n+\t/* OQ attributes */\n+\t.oq = {\n+\t\t.max_oqs = OTX_EP_CFG_IO_QUEUES,\n+\t\t.info_ptr = OTX_EP_OQ_INFOPTR_MODE,\n+\t\t.refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,\n+\t},\n+\n+\t.num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,\n+\t.num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,\n+\t.oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,\n+\n+};\n+\n+\n+static const struct otx_ep_config*\n+otx_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)\n+{\n+\tconst struct otx_ep_config *default_conf = NULL;\n+\n+\tdefault_conf = &default_otx_ep_conf;\n+\n+\treturn default_conf;\n+}\n+\n+int\n+otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* If application doesn't provide its conf, use driver default conf */\n+\tif (otx_ep->conf == NULL) {\n+\t\totx_ep->conf = otx_ep_get_defconf(otx_ep);\n+\t\tif (otx_ep->conf == NULL) {\n+\t\t\totx_ep_err(\"OTX_EP VF default config not found\\n\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\totx_ep_info(\"Default config is used\\n\");\n+\t}\n+\n+\t/* Get IOQs (RPVF] count */\n+\treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(0));\n+\n+\totx_ep->sriov_info.rings_per_vf = ((reg_val >> OTX_EP_R_IN_CTL_RPVF_POS)\n+\t\t\t\t\t & OTX_EP_R_IN_CTL_RPVF_MASK);\n+\n+\totx_ep_info(\"OTX_EP RPVF: %d\\n\", otx_ep->sriov_info.rings_per_vf);\n+\n+\totx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h\nindex e88b40971..c5741a3f1 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.h\n@@ -4,6 +4,39 @@\n #ifndef _OTX_EP_VF_H_\n #define _OTX_EP_VF_H_\n \n+#define OTX_EP_RING_OFFSET (0x1ull << 17)\n+\n+/* OTX_EP VF IQ Registers */\n+#define OTX_EP_R_IN_CONTROL_START (0x10000)\n+#define OTX_EP_R_IN_CONTROL(ring) \\\n+\t(OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))\n+\n+/* OTX_EP VF IQ Masks */\n+#define OTX_EP_R_IN_CTL_RPVF_MASK (0xF)\n+#define\tOTX_EP_R_IN_CTL_RPVF_POS (48)\n+\n+#define OTX_EP_R_IN_CTL_IDLE (0x1ull << 28)\n+#define OTX_EP_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */\n+#define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24)\n+#define OTX_EP_R_IN_CTL_ESR (0x1ull << 1)\n+/* OTX_EP VF OQ Registers */\n+#define OTX_EP_R_OUT_CONTROL_START (0x10150)\n+#define OTX_EP_R_OUT_CONTROL(ring) \\\n+\t(OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))\n+/* OTX_EP VF OQ Masks */\n+#define OTX_EP_R_OUT_CTL_ES_I (1ull << 34)\n+#define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33)\n+#define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32)\n+#define OTX_EP_R_OUT_CTL_ES_D (1ull << 30)\n+#define OTX_EP_R_OUT_CTL_NSR_D (1ull << 29)\n+#define OTX_EP_R_OUT_CTL_ROR_D (1ull << 28)\n+#define OTX_EP_R_OUT_CTL_ES_P (1ull << 26)\n+#define OTX_EP_R_OUT_CTL_NSR_P (1ull << 25)\n+#define OTX_EP_R_OUT_CTL_ROR_P (1ull << 24)\n+#define OTX_EP_R_OUT_CTL_IMODE (1ull << 23)\n+\n #define PCI_DEVID_OCTEONTX_EP_VF 0xa303\n \n+int\n+otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);\n #endif /*_OTX_EP_VF_H_ */\n", "prefixes": [ "v3", "04/11" ] }