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GET /api/patches/87359/?format=api
{ "id": 87359, "url": "https://patches.dpdk.org/api/patches/87359/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-5-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-5-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-5-pnalla@marvell.com", "date": "2021-01-26T21:30:45", "name": "[v3,05/11] net/octeontx_ep: Add dev info get and configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1a444cfe3e2565527d6e6cc57a386baaacb28b34", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-5-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87359/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1AA0DA052A;\n\tTue, 26 Jan 2021 22:31:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AAAC8140D19;\n\tTue, 26 Jan 2021 22:31:50 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 25F03140D0A\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:46 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QKxVBY013577 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:46 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 368j1u9psv-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:46 -0800", "from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:44 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:44 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id AE5B03F703F;\n Tue, 26 Jan 2021 13:31:44 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=GBbeXtse512pqYl8hekMtfB7CE5ZaFwTUBhv2z5hjNo=;\n b=TEt3lnrJoXmW8V56G84YCzngBDeM/GOaRtmMMeNHYYXPSv/+82jMwx64eKjzyMIoslQN\n PDk6EkF/19Xi96qebOSl0RiQ1vbbnzkToh8gHN+irZvfhGI6+BJlP0x76NpXTHgBED9J\n k1Bmpxz4GiTbfs0cfQHzl1U9+6zQsRLVt9HVr+wGVkd3a7M3uQCn7fbNaD/vnv1GvSsU\n KsxVLDAJ/8PeblfODsd/CXjJRvhoeAXk4TzuA7S4DyB34qu/MoStAcyTwkoJvM/qvNR8\n Fl+3RGpUnqsyJ1AgeUSfj2xHgA6SkyWlGdkH7X3Qk1IuDGwkZpEagKkCnyYnSuUEkWG5 sg==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:45 -0800", "Message-ID": "<20210126213051.57281-5-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 05/11] net/octeontx_ep: Add dev info get and\n configure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add device information get and device configure operations.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx_ep_common.h | 15 +++++\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 89 ++++++++++++++++++++++++-\n drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 +++\n 3 files changed, 111 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h", "diff": "diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 74f9e10b1..7f3c913f3 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -7,9 +7,12 @@\n #define OTX_EP_MAX_RINGS_PER_VF (8)\n #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF\n #define OTX_EP_64BYTE_INSTR (64)\n+#define OTX_EP_MIN_IQ_DESCRIPTORS (128)\n+#define OTX_EP_MIN_OQ_DESCRIPTORS (128)\n #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)\n #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)\n #define OTX_EP_OQ_BUF_SIZE (2048)\n+#define OTX_EP_MIN_RX_BUF_SIZE (64)\n \n #define OTX_EP_OQ_INFOPTR_MODE (0)\n #define OTX_EP_OQ_REFIL_THRESHOLD (16)\n@@ -112,6 +115,10 @@ struct otx_ep_device {\n \n \tstruct otx_ep_fn_list fn_list;\n \n+\tuint32_t max_tx_queues;\n+\n+\tuint32_t max_rx_queues;\n+\n \t/* SR-IOV info */\n \tstruct otx_ep_sriov_info sriov_info;\n \n@@ -119,7 +126,15 @@ struct otx_ep_device {\n \tconst struct otx_ep_config *conf;\n \n \tint port_configured;\n+\n+\tuint64_t rx_offloads;\n+\n+\tuint64_t tx_offloads;\n };\n \n+#define OTX_EP_MAX_PKT_SZ 64000U\n+\n+#define OTX_EP_MAX_MAC_ADDRS 1\n+\n extern int otx_net_ep_logtype;\n #endif /* _OTX_EP_COMMON_H_ */\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex c90ef13c0..4b6800fae 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -10,8 +10,57 @@\n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n #include \"otx2_ep_vf.h\"\n+#include \"otx_ep_rxtx.h\"\n+\n+#define OTX_EP_DEV(_eth_dev) \\\n+\t((struct otx_ep_device *)(_eth_dev)->data->dev_private)\n+\n+static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {\n+\t.nb_max\t\t= OTX_EP_MAX_OQ_DESCRIPTORS,\n+\t.nb_min\t\t= OTX_EP_MIN_OQ_DESCRIPTORS,\n+\t.nb_align\t= OTX_EP_RXD_ALIGN,\n+};\n+\n+static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {\n+\t.nb_max\t\t= OTX_EP_MAX_IQ_DESCRIPTORS,\n+\t.nb_min\t\t= OTX_EP_MIN_IQ_DESCRIPTORS,\n+\t.nb_align\t= OTX_EP_TXD_ALIGN,\n+};\n+\n+static int\n+otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_dev_info *devinfo)\n+{\n+\tstruct otx_ep_device *otx_epvf;\n+\tstruct rte_pci_device *pdev;\n+\tuint32_t dev_id;\n+\n+\totx_epvf = OTX_EP_DEV(eth_dev);\n+\tpdev = otx_epvf->pdev;\n+\tdev_id = pdev->id.device_id;\n+\n+\tdevinfo->speed_capa = ETH_LINK_SPEED_10G;\n+\tdevinfo->max_rx_queues = otx_epvf->max_rx_queues;\n+\tdevinfo->max_tx_queues = otx_epvf->max_tx_queues;\n+\n+\tdevinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;\n+\tif (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||\n+\t dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||\n+\t dev_id == PCI_DEVID_CN98XX_EP_NET_VF) {\n+\t\tdevinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;\n+\t\tdevinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;\n+\t\tdevinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;\n+\t\tdevinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;\n+\t}\n+\n+\tdevinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;\n+\n+\tdevinfo->rx_desc_lim = otx_ep_rx_desc_lim;\n+\tdevinfo->tx_desc_lim = otx_ep_tx_desc_lim;\n+\n+\treturn 0;\n+}\n \n-#define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)\n static int\n otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n {\n@@ -62,6 +111,41 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \treturn -ENOMEM;\n }\n \n+static int\n+otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_eth_rxmode *rxmode;\n+\tstruct rte_eth_txmode *txmode;\n+\tstruct rte_eth_conf *conf;\n+\tuint32_t ethdev_queues;\n+\n+\tconf = &data->dev_conf;\n+\trxmode = &conf->rxmode;\n+\ttxmode = &conf->txmode;\n+\tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n+\tif (eth_dev->data->nb_rx_queues > ethdev_queues ||\n+\t eth_dev->data->nb_tx_queues > ethdev_queues) {\n+\t\totx_ep_err(\"invalid num queues\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\totx_ep_info(\"OTX_EP Device is configured with num_txq %d num_rxq %d\\n\",\n+\t\t eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);\n+\n+\totx_epvf->port_configured = 1;\n+\totx_epvf->rx_offloads = rxmode->offloads;\n+\totx_epvf->tx_offloads = txmode->offloads;\n+\n+\treturn 0;\n+}\n+\n+/* Define our ethernet definitions */\n+static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n+\t.dev_configure\t\t= otx_ep_dev_configure,\n+\t.dev_infos_get\t\t= otx_ep_dev_info_get,\n+};\n+\n static int\n otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n {\n@@ -99,6 +183,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \totx_epvf->eth_dev = eth_dev;\n \totx_epvf->port_id = eth_dev->data->port_id;\n+\teth_dev->dev_ops = &otx_ep_eth_dev_ops;\n \teth_dev->data->mac_addrs = rte_zmalloc(\"otx_ep\", RTE_ETHER_ADDR_LEN, 0);\n \tif (eth_dev->data->mac_addrs == NULL) {\n \t\totx_ep_err(\"MAC addresses memory allocation failed\\n\");\n@@ -139,8 +224,6 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = {\n \t{ .vendor_id = 0, /* sentinel */ }\n };\n \n-\n-\n static struct rte_pci_driver rte_otx_ep_pmd = {\n \t.id_table\t= pci_id_otx_ep_map,\n \t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.h b/drivers/net/octeontx_ep/otx_ep_rxtx.h\nnew file mode 100644\nindex 000000000..9779e96b6\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _OTX_EP_RXTX_H_\n+#define _OTX_EP_RXTX_H_\n+\n+#define OTX_EP_RXD_ALIGN 1\n+#define OTX_EP_TXD_ALIGN 1\n+#endif\n", "prefixes": [ "v3", "05/11" ] }