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GET /api/patches/8723/?format=api
{ "id": 8723, "url": "https://patches.dpdk.org/api/patches/8723/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446741498-3096-14-git-send-email-jerin.jacob@caviumnetworks.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446741498-3096-14-git-send-email-jerin.jacob@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446741498-3096-14-git-send-email-jerin.jacob@caviumnetworks.com", "date": "2015-11-05T16:38:16", "name": "[dpdk-dev,13/15] eal: introduce rte_smp_*mb() for memory barriers to use between lcores", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "981db478896922fb32690b253177e72e6cc135fa", "submitter": { "id": 305, "url": "https://patches.dpdk.org/api/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446741498-3096-14-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8723/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8723/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 02C7691AD;\n\tThu, 5 Nov 2015 17:40:01 +0100 (CET)", "from na01-bn1-obe.outbound.protection.outlook.com\n\t(mail-bn1on0085.outbound.protection.outlook.com [157.56.110.85])\n\tby dpdk.org (Postfix) with ESMTP id D7A329201\n\tfor <dev@dpdk.org>; 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CY1PR0701MB1977;\n\t2:Vbq0Vvx2E6JXXT/3aAU+5yi8k78q3Y/t4MM6y+1J+CzZiP8QD09UYgytw7ZlpNejvb6xh5FOGYA0BLleSk5Kz7Fd7xf+KaE9jlX0Mbrm2C66C72xcEMrZlO3ILsDQ7pcTeCcAFHJM8iz8cuajtjB0b446zSYtq9tHLzvJ5XJzpY=;\n\t3:vff2hz9j7vpsivyVYQU40+Zl8/73He1uQmLq55ymx8I6fzWy7/gY0XFDNUVUbB5LvVEOPWQP3byt6TjlEB80taPAVloD6C/HUuyKuCKhU6s3xjBBQuSJbxjS2xMpx9VsUpxeeAu9aOhvGnlmYfwS0Q==;\n\t25:3uD0ocCEDEPTZ0QF4gVIOfiu9Fh7yker3px41iDAhlWk8yy7VGrEekABHmMpEWk72OA3WETpBm94KHzazXwUHUQ+hJ0swceXFKg8DzG7/TW+MyG04gqOssQff56A7XAD1uAag96MApO8A/iS0xBrsS/uaHhkxNGi529PCUzFchfVarFe0GJOFNVLANCwEwPbgy/xyFGlceDoWRo6h0SgVqAtYE4f5XqS9QVx9inxmJao80bANX6D1i90YeNvK3ccBsk1zsAJrGSJ684GuXj+IA==", "1; CY1PR0701MB1977;\n\t20:wDD6ZZ513Q1MkUKCG1EncYlr7IgRjGn+bGFn/90E80R2K9UJftleMA75PZr8e7nBaaR8JUHYJA2UcGKWmDiHQbYe/zrhfpf8fBw9Pfd2H54F+nqLpTrcXJZrLP1uU4/pC9L7x4S+z4hiatCn2R05nTO5Yk0H6z2z+HN9fAU3XOQzilfiAa25gW8S58JzPkabL8MLSeFJW4VDiwsLq8tgG/4jP6dFpnYnZD2x8zlJV9QmiuoIx9tL2PsvEsAEWvhyyHw2CFjmDcJgpBfFpNFz0K7mRPocfX6TnMzQRAfpwTJrBK45hqQV5SlMHv2NU7hXVBLON1DMINAftV+09FpzsPlEZ313sC0cmTttdgzoBvNZlYE3D50TNYM2rQ7f1BsO9BOihHPmnuX4ghl/csYB3xKITge0Hp7/iW9K8ARrFiXGilq7ZfzqPhfI+xU2iPZzPluVyJayL2qvma7wEqpOsggRXoCUunV4rjKSe6sPMcQ7adSz1uTE45hg/6bmHImdgQ6Cu5fR6y2rZWBNQBnEHe9y4GpVQW+4MOCQ2ITDfilDMGxw2TS625mGdZeqpid26JOvVu0YUqbTQ2YxN84hLYMMnBMtSewBanm69ZkhLcc=", "1; CY1PR0701MB1977;\n\t4:JsNSV6qVAuSM3LDIrcrL9V1efP+M9nzn8nJ0eldihlbyIC2aEBxSc6hq/njV6ozZdcYiaSWNBsNfjaa2QHE0wKq/fUXnpFK95nKxF9zIRBQrEdzpQPfD1fTNh+NbVw4psJ5q2BMjUsdskB1dmOBq1kBITv0RTVAUkDTvq374pIjJ+kqtOLeWbjJSMFTjFtXeDl4UiWfRHk0dSlchMJczGiC1N1uxpV4ret5F4l+SSovSyoYdbX9ek1+yu9GcHl+Zw7hJRPztvILTR+a55uxWEZ+uYoA6Nhc6hDhTwJOel+RKctYgsVClwMAVw/U9Z0SLNmlRH6XbyVdq/1ozVYdpckaKFjeXPUGFFz6hdAD3w8gF4zEynkglJSK9U0YMnD/g", "=?us-ascii?Q?1; CY1PR0701MB1977;\n\t23:q+XBZAHDXP0yoxVAavzfOs8Js6P9qW1nHzxWNeA?=\n\t=?us-ascii?Q?nDRvR3ATprLABEMQKAsHPQ3PYv+DTx5uzN5VGQTAWVtjdLTz1ryp20vdD1AO?=\n\t=?us-ascii?Q?xGmy4lye78MgrVyLSsv/ZJSwQhtOrEZ4R5GfywzXUfSbsznRFUP1y4zJMQNj?=\n\t=?us-ascii?Q?ceVelQCyBUu+R5Lwy0cWTUau0ec2EBr2u8APbT12s2wweEpbQnSMulwxuhWF?=\n\t=?us-ascii?Q?XH/KoAFjQ9nP/5WNhMc9PfslhY8eExNQ4cjHviFdr/Ne+TtN5sVdjq3covbA?=\n\t=?us-ascii?Q?fXcInisKPVFC9gQ2ULU5Dxc1P2+mhyAaL5bbYyBoz4cK9vHUjVZyFAcIjXje?=\n\t=?us-ascii?Q?muU30KBW+tzmIw7TfYPo3x5hxxlyqv0AvIPVjbNK1vviWbfUtYuni0Fv+H79?=\n\t=?us-ascii?Q?8wGkrOhLo2FHtmVxhjlJthO6GHpkS9smTh+XkQuCwNG+HIxEhtCYdhExCO/a?=\n\t=?us-ascii?Q?0Q3Q5sR1fVaR1XpLkFpxPymbvvSiRdbm+KedGDiAH2lNQ4g4g07/O/fFit1S?=\n\t=?us-ascii?Q?O+gctTGFkvyCdYgmVjMkuAaOvB+Fo5Ea/1tunberhJLgk+e/v7/WdxWct82U?=\n\t=?us-ascii?Q?h1jkNUZVeW4kYXcvC8T7GwKdcX5MzkM5uyME7s95iByXbmZFsx12kd3W3CYD?=\n\t=?us-ascii?Q?8Xd1lFZCMR+ZfcOL5Ctc//swsFttqp/Q6O8+QRKMImCLXUgd8ymdoRH8jtlZ?=\n\t=?us-ascii?Q?AtsDHORRKkRwby/iNp/kThj02ikpaQp9dHxOV7mC+shoVEFCGGo7eiSff5O/?=\n\t=?us-ascii?Q?0uocKnL8COm0fWFE8RgVbbsDl2kmaVB30mvoAfUzXjRmpChQrgc8zRPZZfpQ?=\n\t=?us-ascii?Q?8AL8rL+2+At0exP5kxJqd7BDXsOzPmak8RElhSIyMoAcH8rhWS86SrLeGzGP?=\n\t=?us-ascii?Q?OY2oZRKbFTJQSYln/usrBQLcu6TU30IngjKt7/DDzVZ0UWaSfilVIFwHxKMl?=\n\t=?us-ascii?Q?BCCoeB1N7hfXQ+7N+gXCs1nETX1ht9Pxq5W+7hzyISy6UsVrgUJytCJQl1fN?=\n\t=?us-ascii?Q?HYus9weFJxa80zoaObR56arQTfNWHSBngYbNw2tfDMupuAwUE00NcuvZEZAa?=\n\t=?us-ascii?Q?tKKPFraUqgsZQqazwSCRdev5NF13FuRPqYwIAQuWw1Y/j+EBXBEFT3ly/Sc1?=\n\t=?us-ascii?Q?/NCcfR7NkiemaRI57ynZYH77chgePTp+AlWRIL5sJE8VmrcSt4NJU4enboUY?=\n\t=?us-ascii?Q?2LTo8x6WImdXiB38=3D?=", "1; CY1PR0701MB1977;\n\t5:BJAjHuBMKZZs/GMHYmiWIuyarqypvPYylF2rr2L4BpCip1rUVYox0mOpA1nODegsrIAbUxI7Ajw9VfeEjmUpGA/A8zSNQBil3gEAWEINPBI4ziQaRLHuOv+NPFCOIlEhK4M6ZxLGsrXpnGLVElCWMw==;\n\t24:/3FeYDmoprK6tIw1tvD62numKlKvUIhEuXHDEelPudQFf2ykRXr4Tji1pVxQB2IFcSd0kentt2hoVtmDo+C40dKxrwKmrdleHlFa72cccbE=;\n\t20:sWnJBHF/xO+uROtuwxtIKy+EuKkbHIlAtI49py/Sm29Tio9KIinsfcBb89jjBn7HDAlg0yverm47QlGOYCMkPQ==" ], "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0701MB1977;", "X-Microsoft-Antispam-PRVS": "<CY1PR0701MB197724761C87CC43B12728C48C290@CY1PR0701MB1977.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(236414709691187)(228905959029699); ", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(2401047)(520078)(5005006)(8121501046)(3002001)(10201501046);\n\tSRVR:CY1PR0701MB1977; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0701MB1977; ", "X-Forefront-PRVS": "0751474A44", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6009001)(189002)(199003)(5007970100001)(86362001)(5001960100002)(107886002)(36756003)(122386002)(40100003)(189998001)(42186005)(5008740100001)(575784001)(87976001)(110136002)(97736004)(66066001)(101416001)(92566002)(2950100001)(5009440100003)(4001430100002)(19580405001)(76176999)(5003940100001)(50986999)(50226001)(50466002)(106356001)(77096005)(105586002)(5004730100002)(2351001)(81156007)(229853001)(48376002)(33646002)(19580395003)(69596002)(53416004)(93886004)(47776003)(7099028);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0701MB1977;\n\tH:jerin.caveonetworks.com; \n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: caviumnetworks.com does not\n\tdesignate permitted sender hosts)", "SpamDiagnosticOutput": "1:23", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Nov 2015 16:39:55.6490\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0701MB1977", "Subject": "[dpdk-dev] [PATCH 13/15] eal: introduce rte_smp_*mb() for memory\n\tbarriers to use between lcores", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit introduce rte_smp_mb(), rte_smp_wmb() and rte_smp_rmb(), in\norder to enable memory barriers between lcores.\nThe patch does not provide any functional change for IA, the goal is to\nhave infrastructure for weakly ordered machines like ARM to work on DPDK.\n\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n drivers/net/virtio/virtqueue.h | 8 +++----\n drivers/net/xenvirt/rte_eth_xenvirt.c | 4 ++--\n drivers/net/xenvirt/virtqueue.h | 2 +-\n .../common/include/arch/ppc_64/rte_atomic.h | 6 +++++\n .../common/include/arch/tile/rte_atomic.h | 6 +++++\n .../common/include/arch/x86/rte_atomic.h | 6 +++++\n lib/librte_eal/common/include/generic/rte_atomic.h | 27 ++++++++++++++++++++++\n lib/librte_ring/rte_ring.h | 8 +++----\n 8 files changed, 55 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/virtio/virtqueue.h b/drivers/net/virtio/virtqueue.h\nindex 7789411..d233be6 100644\n--- a/drivers/net/virtio/virtqueue.h\n+++ b/drivers/net/virtio/virtqueue.h\n@@ -53,12 +53,10 @@ struct rte_mbuf;\n * accesses through relaxed memory I/O windows, so smp_mb() et al are\n * sufficient.\n *\n- * This driver is for virtio_pci on SMP and therefore can assume\n- * weaker (compiler barriers)\n */\n-#define virtio_mb()\trte_mb()\n-#define virtio_rmb()\trte_compiler_barrier()\n-#define virtio_wmb()\trte_compiler_barrier()\n+#define virtio_mb()\trte_smp_mb()\n+#define virtio_rmb()\trte_smp_rmb()\n+#define virtio_wmb()\trte_smp_wmb()\n \n #ifdef RTE_PMD_PACKET_PREFETCH\n #define rte_packet_prefetch(p) rte_prefetch1(p)\ndiff --git a/drivers/net/xenvirt/rte_eth_xenvirt.c b/drivers/net/xenvirt/rte_eth_xenvirt.c\nindex 73e8bce..8c33a02 100644\n--- a/drivers/net/xenvirt/rte_eth_xenvirt.c\n+++ b/drivers/net/xenvirt/rte_eth_xenvirt.c\n@@ -99,7 +99,7 @@ eth_xenvirt_rx(void *q, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \n \tnb_used = VIRTQUEUE_NUSED(rxvq);\n \n-\trte_compiler_barrier(); /* rmb */\n+\trte_smp_rmb();\n \tnum = (uint16_t)(likely(nb_used <= nb_pkts) ? nb_used : nb_pkts);\n \tnum = (uint16_t)(likely(num <= VIRTIO_MBUF_BURST_SZ) ? num : VIRTIO_MBUF_BURST_SZ);\n \tif (unlikely(num == 0)) return 0;\n@@ -150,7 +150,7 @@ eth_xenvirt_tx(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tPMD_TX_LOG(DEBUG, \"%d packets to xmit\", nb_pkts);\n \tnb_used = VIRTQUEUE_NUSED(txvq);\n \n-\trte_compiler_barrier(); /* rmb */\n+\trte_smp_rmb();\n \n \tnum = (uint16_t)(likely(nb_used <= VIRTIO_MBUF_BURST_SZ) ? nb_used : VIRTIO_MBUF_BURST_SZ);\n \tnum = virtqueue_dequeue_burst(txvq, snd_pkts, len, num);\ndiff --git a/drivers/net/xenvirt/virtqueue.h b/drivers/net/xenvirt/virtqueue.h\nindex eff6208..6dcb0ef 100644\n--- a/drivers/net/xenvirt/virtqueue.h\n+++ b/drivers/net/xenvirt/virtqueue.h\n@@ -151,7 +151,7 @@ vq_ring_update_avail(struct virtqueue *vq, uint16_t desc_idx)\n \t */\n \tavail_idx = (uint16_t)(vq->vq_ring.avail->idx & (vq->vq_nentries - 1));\n \tvq->vq_ring.avail->ring[avail_idx] = desc_idx;\n-\trte_compiler_barrier(); /* wmb , for IA memory model barrier is enough*/\n+\trte_smp_wmb();\n \tvq->vq_ring.avail->idx++;\n }\n \ndiff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h\nindex fb7af2b..b8bc2c0 100644\n--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h\n@@ -72,6 +72,12 @@ extern \"C\" {\n */\n #define\trte_rmb() {asm volatile(\"sync\" : : : \"memory\"); }\n \n+#define rte_smp_mb() rte_mb()\n+\n+#define rte_smp_wmb() rte_compiler_barrier()\n+\n+#define rte_smp_rmb() rte_compiler_barrier()\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n /* To be compatible with Power7, use GCC built-in functions for 16 bit\n * operations */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_atomic.h b/lib/librte_eal/common/include/arch/tile/rte_atomic.h\nindex 3dc8eb8..28825ff 100644\n--- a/lib/librte_eal/common/include/arch/tile/rte_atomic.h\n+++ b/lib/librte_eal/common/include/arch/tile/rte_atomic.h\n@@ -79,6 +79,12 @@ static inline void rte_rmb(void)\n \t__sync_synchronize();\n }\n \n+#define rte_smp_mb() rte_mb()\n+\n+#define rte_smp_wmb() rte_compiler_barrier()\n+\n+#define rte_smp_rmb() rte_compiler_barrier()\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h\nindex e93e8ee..41178c7 100644\n--- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h\n+++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h\n@@ -53,6 +53,12 @@ extern \"C\" {\n \n #define\trte_rmb() _mm_lfence()\n \n+#define rte_smp_mb() rte_mb()\n+\n+#define rte_smp_wmb() rte_compiler_barrier()\n+\n+#define rte_smp_rmb() rte_compiler_barrier()\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n \n #ifndef RTE_FORCE_INTRINSICS\ndiff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h\nindex 6c7581a..26d1f56 100644\n--- a/lib/librte_eal/common/include/generic/rte_atomic.h\n+++ b/lib/librte_eal/common/include/generic/rte_atomic.h\n@@ -72,6 +72,33 @@ static inline void rte_wmb(void);\n */\n static inline void rte_rmb(void);\n \n+/**\n+ * General memory barrier between lcores\n+ *\n+ * Guarantees that the LOAD and STORE operations that precede the\n+ * rte_smp_mb() call are globally visible across the lcores\n+ * before the the LOAD and STORE operations that follows it.\n+ */\n+static inline void rte_smp_mb(void);\n+\n+/**\n+ * Write memory barrier between lcores\n+ *\n+ * Guarantees that the STORE operations that precede the\n+ * rte_smp_wmb() call are globally visible across the lcores\n+ * before the the STORE operations that follows it.\n+ */\n+static inline void rte_smp_wmb(void);\n+\n+/**\n+ * Read memory barrier between lcores\n+ *\n+ * Guarantees that the LOAD operations that precede the\n+ * rte_smp_rmb() call are globally visible across the lcores\n+ * before the the LOAD operations that follows it.\n+ */\n+static inline void rte_smp_rmb(void);\n+\n #endif /* __DOXYGEN__ */\n \n /**\ndiff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h\nindex af68888..19ea1bb 100644\n--- a/lib/librte_ring/rte_ring.h\n+++ b/lib/librte_ring/rte_ring.h\n@@ -457,7 +457,7 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table,\n \n \t/* write entries in ring */\n \tENQUEUE_PTRS();\n-\trte_compiler_barrier();\n+\trte_smp_wmb();\n \n \t/* if we exceed the watermark */\n \tif (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) {\n@@ -552,7 +552,7 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table,\n \n \t/* write entries in ring */\n \tENQUEUE_PTRS();\n-\trte_compiler_barrier();\n+\trte_smp_wmb();\n \n \t/* if we exceed the watermark */\n \tif (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) {\n@@ -643,7 +643,7 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table,\n \n \t/* copy in table */\n \tDEQUEUE_PTRS();\n-\trte_compiler_barrier();\n+\trte_smp_rmb();\n \n \t/*\n \t * If there are other dequeues in progress that preceded us,\n@@ -727,7 +727,7 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table,\n \n \t/* copy in table */\n \tDEQUEUE_PTRS();\n-\trte_compiler_barrier();\n+\trte_smp_rmb();\n \n \t__RING_STAT_ADD(r, deq_success, n);\n \tr->cons.tail = cons_next;\n", "prefixes": [ "dpdk-dev", "13/15" ] }