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GET /api/patches/87157/?format=api
{ "id": 87157, "url": "https://patches.dpdk.org/api/patches/87157/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1611486126-84749-4-git-send-email-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1611486126-84749-4-git-send-email-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1611486126-84749-4-git-send-email-suanmingm@nvidia.com", "date": "2021-01-24T11:02:05", "name": "[3/4] net/mlx5: fix secondary process attach port Tx queue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "77b9fc944d889e94244969159d45a3fea71ec3f1", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1611486126-84749-4-git-send-email-suanmingm@nvidia.com/mbox/", "series": [ { "id": 14914, "url": "https://patches.dpdk.org/api/series/14914/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14914", "date": "2021-01-24T11:02:04", "name": "net/mlx: fix secondary process bugs", "version": 1, "mbox": "https://patches.dpdk.org/series/14914/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87157/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/87157/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBD91A052A;\n\tSun, 24 Jan 2021 12:02:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A446A140DA5;\n\tSun, 24 Jan 2021 12:02:22 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 3DF83140DA1\n for <dev@dpdk.org>; Sun, 24 Jan 2021 12:02:21 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:16 +0200", "from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ8003937;\n Sun, 24 Jan 2021 13:02:15 +0200" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "viacheslavo@nvidia.com, matan@nvidia.com", "Cc": "rasland@nvidia.com, dev@dpdk.org, stable@dpdk.org", "Date": "Sun, 24 Jan 2021 19:02:05 +0800", "Message-Id": "<1611486126-84749-4-git-send-email-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1611486126-84749-1-git-send-email-suanmingm@nvidia.com>", "References": "<1611486126-84749-1-git-send-email-suanmingm@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 3/4] net/mlx5: fix secondary process attach port\n Tx queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, the secondary process port UAR register mapping used by Tx\nqueue is done during port initializing.\n\nUnluckily, in port hot-plug case, the secondary process was requested\nto initialize the port when primary process did not complete the\ndevice configuration and the port Tx queue number is not configured\nyet. Hence, the secondary process getS the zero Tx queue number during\nprobing, causing the UAR registers not be mapped in the correct\nfashion.\n\nThis commit checks the configured number of Tx queues in secondary\nprocess when the port start is requested. In case the Tx queue\nnumber mismatch found the UAR mapping is reinitialized accordingly.\n\nFixes: 2aac5b5d119f (\"net/mlx5: sync stop/start with secondary process\")\ncc: stable@dpdk.org\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_mp_os.c | 19 +++++++++++++++++++\n drivers/net/mlx5/mlx5.c | 2 +-\n drivers/net/mlx5/mlx5.h | 6 +++++-\n 3 files changed, 25 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_mp_os.c b/drivers/net/mlx5/linux/mlx5_mp_os.c\nindex 08ade75..95372e2 100644\n--- a/drivers/net/mlx5/linux/mlx5_mp_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_mp_os.c\n@@ -115,6 +115,7 @@\n \tconst struct mlx5_mp_param *param =\n \t\t(const struct mlx5_mp_param *)mp_msg->param;\n \tstruct rte_eth_dev *dev;\n+\tstruct mlx5_proc_priv *ppriv;\n \tstruct mlx5_priv *priv;\n \tint ret;\n \n@@ -132,6 +133,20 @@\n \t\trte_mb();\n \t\tdev->rx_pkt_burst = mlx5_select_rx_function(dev);\n \t\tdev->tx_pkt_burst = mlx5_select_tx_function(dev);\n+\t\tppriv = (struct mlx5_proc_priv *)dev->process_private;\n+\t\t/* If Tx queue number changes, re-initialize UAR. */\n+\t\tif (ppriv->uar_table_sz != priv->txqs_n) {\n+\t\t\tmlx5_tx_uar_uninit_secondary(dev);\n+\t\t\tmlx5_proc_priv_uninit(dev);\n+\t\t\tret = mlx5_proc_priv_init(dev);\n+\t\t\tif (ret)\n+\t\t\t\treturn -rte_errno;\n+\t\t\tret = mlx5_tx_uar_init_secondary(dev, mp_msg->fds[0]);\n+\t\t\tif (ret) {\n+\t\t\t\tmlx5_proc_priv_uninit(dev);\n+\t\t\t\treturn -rte_errno;\n+\t\t\t}\n+\t\t}\n \t\tmp_init_msg(&priv->mp_id, &mp_res, param->type);\n \t\tres->result = 0;\n \t\tret = rte_mp_reply(&mp_res, peer);\n@@ -183,6 +198,10 @@\n \t\treturn;\n \t}\n \tmp_init_msg(&priv->mp_id, &mp_req, type);\n+\tif (type == MLX5_MP_REQ_START_RXTX) {\n+\t\tmp_req.num_fds = 1;\n+\t\tmp_req.fds[0] = ((struct ibv_context *)priv->sh->ctx)->cmd_fd;\n+\t}\n \tret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);\n \tif (ret) {\n \t\tif (rte_errno != ENOTSUP)\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex efedbb9..b82e767 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1268,7 +1268,7 @@ struct mlx5_dev_ctx_shared *\n * @param dev\n * Pointer to Ethernet device structure.\n */\n-static void\n+void\n mlx5_proc_priv_uninit(struct rte_eth_dev *dev)\n {\n \tif (!dev->process_private)\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 101e9c2..899241e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -743,7 +743,10 @@ struct mlx5_dev_ctx_shared {\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \n-/* Per-process private structure. */\n+/*\n+ * Per-process private structure.\n+ * Caution, secondary pocess may rebuid the struct during port start.\n+ */\n struct mlx5_proc_priv {\n \tsize_t uar_table_sz;\n \t/* Size of UAR register table. */\n@@ -998,6 +1001,7 @@ struct rte_hairpin_peer_info {\n \n int mlx5_getenv_int(const char *);\n int mlx5_proc_priv_init(struct rte_eth_dev *dev);\n+void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);\n int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_udp_tunnel *udp_tunnel);\n uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);\n", "prefixes": [ "3/4" ] }