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GET /api/patches/86964/?format=api
{ "id": 86964, "url": "https://patches.dpdk.org/api/patches/86964/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-7-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1611142175-409485-7-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1611142175-409485-7-git-send-email-matan@nvidia.com", "date": "2021-01-20T11:29:30", "name": "[v3,06/11] compress/mlx5: add transformation operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "eed52752ac2f08d9524dac332f8331053e389502", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-7-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 14865, "url": "https://patches.dpdk.org/api/series/14865/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14865", "date": "2021-01-20T11:29:24", "name": "add mlx5 compress PMD", "version": 3, "mbox": "https://patches.dpdk.org/series/14865/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/86964/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/86964/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81985A0A05;\n\tWed, 20 Jan 2021 12:34:22 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EFB09140D1B;\n\tWed, 20 Jan 2021 12:34:18 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 9EE64140D1B\n for <dev@dpdk.org>; Wed, 20 Jan 2021 12:34:17 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 20 Jan 2021 13:34:15 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10KBTfXD001381;\n Wed, 20 Jan 2021 13:34:15 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>, akhil.goyal@nxp.com", "Date": "Wed, 20 Jan 2021 11:29:30 +0000", "Message-Id": "<1611142175-409485-7-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1611142175-409485-1-git-send-email-matan@nvidia.com>", "References": "<1610554690-411627-1-git-send-email-matan@nvidia.com>\n <1611142175-409485-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 06/11] compress/mlx5: add transformation\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for the next operations:\n\t- private_xform_create\n\t- private_xform_free\n\nThe driver transformation structure includes preparations for the next\nGGA WQE fields used by the enqueue function: opcode. compress specific\nfields (window size, block size and dynamic size) checksum type and\ncompress type.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 121 +++++++++++++++++++++++++++++++++-\n 1 file changed, 119 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex a2507c2..cc9be72 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -6,6 +6,7 @@\n #include <rte_log.h>\n #include <rte_errno.h>\n #include <rte_pci.h>\n+#include <rte_spinlock.h>\n #include <rte_comp.h>\n #include <rte_compressdev.h>\n #include <rte_compressdev_pmd.h>\n@@ -24,6 +25,15 @@\n #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress\n #define MLX5_COMPRESS_LOG_NAME pmd.compress.mlx5\n #define MLX5_COMPRESS_MAX_QPS 1024\n+#define MLX5_COMP_MAX_WIN_SIZE_CONF 6u\n+\n+struct mlx5_compress_xform {\n+\tLIST_ENTRY(mlx5_compress_xform) next;\n+\tenum rte_comp_xform_type type;\n+\tenum rte_comp_checksum_type csum_type;\n+\tuint32_t opcode;\n+\tuint32_t gga_ctrl1; /* BE. */\n+};\n \n struct mlx5_compress_priv {\n \tTAILQ_ENTRY(mlx5_compress_priv) next;\n@@ -36,6 +46,8 @@ struct mlx5_compress_priv {\n \t/* Minimum huffman block size supported by the device. */\n \tstruct ibv_pd *pd;\n \tstruct rte_compressdev_config dev_config;\n+\tLIST_HEAD(xform_list, mlx5_compress_xform) xform_list;\n+\trte_spinlock_t xform_sl;\n };\n \n struct mlx5_compress_qp {\n@@ -221,6 +233,111 @@ struct mlx5_compress_qp {\n \treturn -1;\n }\n \n+static int\n+mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)\n+{\n+\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\n+\trte_spinlock_lock(&priv->xform_sl);\n+\tLIST_REMOVE((struct mlx5_compress_xform *)xform, next);\n+\trte_spinlock_unlock(&priv->xform_sl);\n+\trte_free(xform);\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_compress_xform_create(struct rte_compressdev *dev,\n+\t\t\t const struct rte_comp_xform *xform,\n+\t\t\t void **private_xform)\n+{\n+\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_compress_xform *xfrm;\n+\tuint32_t size;\n+\n+\tif (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==\n+\t\t\t\t\t\t\t RTE_COMP_LEVEL_NONE) {\n+\t\tDRV_LOG(ERR, \"Non-compressed block is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=\n+\t RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&\n+\t\t xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {\n+\t\tDRV_LOG(ERR, \"SHA is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\txfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,\n+\t\t\t\t\t\t priv->dev_config.socket_id);\n+\tif (xfrm == NULL)\n+\t\treturn -ENOMEM;\n+\txfrm->opcode = MLX5_OPCODE_MMO;\n+\txfrm->type = xform->type;\n+\tswitch (xform->type) {\n+\tcase RTE_COMP_COMPRESS:\n+\t\tswitch (xform->compress.algo) {\n+\t\tcase RTE_COMP_ALGO_NULL:\n+\t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<\n+\t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\tbreak;\n+\t\tcase RTE_COMP_ALGO_DEFLATE:\n+\t\t\tsize = 1 << xform->compress.window_size;\n+\t\t\tsize /= MLX5_GGA_COMP_WIN_SIZE_UNITS;\n+\t\t\txfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),\n+\t\t\t\t\t MLX5_COMP_MAX_WIN_SIZE_CONF) <<\n+\t\t\t\t\t WQE_GGA_COMP_WIN_SIZE_OFFSET;\n+\t\t\tif (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)\n+\t\t\t\tsize = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;\n+\t\t\telse\n+\t\t\t\tsize = priv->min_block_size - 1 +\n+\t\t\t\t\t\t\t xform->compress.level;\n+\t\t\txfrm->gga_ctrl1 += RTE_MIN(size,\n+\t\t\t\t\t MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<\n+\t\t\t\t\t\t WQE_GGA_COMP_BLOCK_SIZE_OFFSET;\n+\t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<\n+\t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\tsize = xform->compress.deflate.huffman ==\n+\t\t\t\t\t\t RTE_COMP_HUFFMAN_DYNAMIC ?\n+\t\t\t\t\t MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :\n+\t\t\t\t\t MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;\n+\t\t\txfrm->gga_ctrl1 += size <<\n+\t\t\t\t\t WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto err;\n+\t\t}\n+\t\txfrm->csum_type = xform->compress.chksum;\n+\t\tbreak;\n+\tcase RTE_COMP_DECOMPRESS:\n+\t\tswitch (xform->decompress.algo) {\n+\t\tcase RTE_COMP_ALGO_NULL:\n+\t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<\n+\t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\tbreak;\n+\t\tcase RTE_COMP_ALGO_DEFLATE:\n+\t\t\txfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<\n+\t\t\t\t\t\t\tWQE_CSEG_OPC_MOD_OFFSET;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto err;\n+\t\t}\n+\t\txfrm->csum_type = xform->decompress.chksum;\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Algorithm %u is not supported.\", xform->type);\n+\t\tgoto err;\n+\t}\n+\tDRV_LOG(DEBUG, \"New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum \"\n+\t\t\"type = %d.\", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);\n+\txfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);\n+\trte_spinlock_lock(&priv->xform_sl);\n+\tLIST_INSERT_HEAD(&priv->xform_list, xfrm, next);\n+\trte_spinlock_unlock(&priv->xform_sl);\n+\t*private_xform = xfrm;\n+\treturn 0;\n+err:\n+\trte_free(xfrm);\n+\treturn -ENOTSUP;\n+}\n+\n static struct rte_compressdev_ops mlx5_compress_ops = {\n \t.dev_configure\t\t= mlx5_compress_dev_configure,\n \t.dev_start\t\t= NULL,\n@@ -231,8 +348,8 @@ struct mlx5_compress_qp {\n \t.stats_reset\t\t= NULL,\n \t.queue_pair_setup\t= mlx5_compress_qp_setup,\n \t.queue_pair_release\t= mlx5_compress_qp_release,\n-\t.private_xform_create\t= NULL,\n-\t.private_xform_free\t= NULL,\n+\t.private_xform_create\t= mlx5_compress_xform_create,\n+\t.private_xform_free\t= mlx5_compress_xform_free,\n \t.stream_create\t\t= NULL,\n \t.stream_free\t\t= NULL,\n };\n", "prefixes": [ "v3", "06/11" ] }