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GET /api/patches/86963/?format=api
{ "id": 86963, "url": "https://patches.dpdk.org/api/patches/86963/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-6-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1611142175-409485-6-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1611142175-409485-6-git-send-email-matan@nvidia.com", "date": "2021-01-20T11:29:29", "name": "[v3,05/11] compress/mlx5: support queue pair operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9353f585f01b3c8f9ad7fdf1c7cef42a4c88cdb5", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-6-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 14865, "url": "https://patches.dpdk.org/api/series/14865/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14865", "date": "2021-01-20T11:29:24", "name": "add mlx5 compress PMD", "version": 3, "mbox": "https://patches.dpdk.org/series/14865/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/86963/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/86963/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75AB3A0A05;\n\tWed, 20 Jan 2021 12:34:14 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5E165140D01;\n\tWed, 20 Jan 2021 12:34:14 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 928A4140D01\n for <dev@dpdk.org>; Wed, 20 Jan 2021 12:34:12 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 20 Jan 2021 13:34:08 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10KBTfXC001381;\n Wed, 20 Jan 2021 13:34:07 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>, akhil.goyal@nxp.com", "Date": "Wed, 20 Jan 2021 11:29:29 +0000", "Message-Id": "<1611142175-409485-6-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1611142175-409485-1-git-send-email-matan@nvidia.com>", "References": "<1610554690-411627-1-git-send-email-matan@nvidia.com>\n <1611142175-409485-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 05/11] compress/mlx5: support queue pair\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for the next operations:\n\t- queue_pair_setup\n\t- queue_pair_release\n\nCreate and initialize DevX SQ and CQ for each compress API queue-pair.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 148 +++++++++++++++++++++++++++++++++-\n 1 file changed, 146 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex efb77d0..a2507c2 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -15,6 +15,8 @@\n #include <mlx5_common_pci.h>\n #include <mlx5_devx_cmds.h>\n #include <mlx5_common_os.h>\n+#include <mlx5_common_devx.h>\n+#include <mlx5_common_mr.h>\n #include <mlx5_prm.h>\n \n #include \"mlx5_compress_utils.h\"\n@@ -36,6 +38,20 @@ struct mlx5_compress_priv {\n \tstruct rte_compressdev_config dev_config;\n };\n \n+struct mlx5_compress_qp {\n+\tuint16_t qp_id;\n+\tuint16_t entries_n;\n+\tuint16_t pi;\n+\tuint16_t ci;\n+\tvolatile uint64_t *uar_addr;\n+\tint socket_id;\n+\tstruct mlx5_devx_cq cq;\n+\tstruct mlx5_devx_sq sq;\n+\tstruct mlx5_pmd_mr opaque_mr;\n+\tstruct rte_comp_op **ops;\n+\tstruct mlx5_compress_priv *priv;\n+};\n+\n TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);\n static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;\n@@ -77,6 +93,134 @@ struct mlx5_compress_priv {\n \treturn 0;\n }\n \n+static int\n+mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)\n+{\n+\tstruct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\tif (qp->sq.sq != NULL)\n+\t\tmlx5_devx_sq_destroy(&qp->sq);\n+\tif (qp->cq.cq != NULL)\n+\t\tmlx5_devx_cq_destroy(&qp->cq);\n+\tif (qp->opaque_mr.obj != NULL) {\n+\t\tvoid *opaq = qp->opaque_mr.addr;\n+\n+\t\tmlx5_common_verbs_dereg_mr(&qp->opaque_mr);\n+\t\tif (opaq != NULL)\n+\t\t\trte_free(opaq);\n+\t}\n+\trte_free(qp);\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_compress_init_sq(struct mlx5_compress_qp *qp)\n+{\n+\tvolatile struct mlx5_gga_wqe *restrict wqe =\n+\t\t\t\t (volatile struct mlx5_gga_wqe *)qp->sq.wqes;\n+\tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n+\tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);\n+\tconst uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t\tMLX5_COMP_MODE_OFFSET);\n+\tconst uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);\n+\tint i;\n+\n+\t/* All the next fields state should stay constant. */\n+\tfor (i = 0; i < qp->entries_n; ++i, ++wqe) {\n+\t\twqe->sq_ds = sq_ds;\n+\t\twqe->flags = flags;\n+\t\twqe->opaque_lkey = opaq_lkey;\n+\t\twqe->opaque_vaddr = rte_cpu_to_be_64\n+\t\t\t\t\t\t((uint64_t)(uintptr_t)&opaq[i]);\n+\t}\n+}\n+\n+static int\n+mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n+\t\t uint32_t max_inflight_ops, int socket_id)\n+{\n+\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_compress_qp *qp;\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n+\t};\n+\tstruct mlx5_devx_create_sq_attr sq_attr = {\n+\t\t.user_index = qp_id,\n+\t\t.wq_attr = (struct mlx5_devx_wq_attr){\n+\t\t\t.pd = priv->pdn,\n+\t\t\t.uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),\n+\t\t},\n+\t};\n+\tstruct mlx5_devx_modify_sq_attr modify_attr = {\n+\t\t.state = MLX5_SQC_STATE_RDY,\n+\t};\n+\tuint32_t log_ops_n = rte_log2_u32(max_inflight_ops);\n+\tuint32_t alloc_size = sizeof(*qp);\n+\tvoid *opaq_buf;\n+\tint ret;\n+\n+\talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n+\talloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);\n+\tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (qp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate qp memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\topaq_buf = rte_calloc(__func__, 1u << log_ops_n,\n+\t\t\t sizeof(struct mlx5_gga_compress_opaque),\n+\t\t\t sizeof(struct mlx5_gga_compress_opaque));\n+\tif (opaq_buf == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate opaque memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tqp->entries_n = 1 << log_ops_n;\n+\tqp->socket_id = socket_id;\n+\tqp->qp_id = qp_id;\n+\tqp->priv = priv;\n+\tqp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tqp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);\n+\tMLX5_ASSERT(qp->uar_addr);\n+\tif (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *\n+\t\t\t\t\tsizeof(struct mlx5_gga_compress_opaque),\n+\t\t\t\t\t\t\t &qp->opaque_mr) != 0) {\n+\t\trte_free(opaq_buf);\n+\t\tDRV_LOG(ERR, \"Failed to register opaque MR.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,\n+\t\t\t\t socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n+\t\tgoto err;\n+\t}\n+\tsq_attr.cqn = qp->cq.cq->id;\n+\tret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,\n+\t\t\t\t socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create SQ.\");\n+\t\tgoto err;\n+\t}\n+\tmlx5_compress_init_sq(qp);\n+\tret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Can't change SQ state to ready.\");\n+\t\tgoto err;\n+\t}\n+\tDRV_LOG(INFO, \"QP %u: SQN=0x%X CQN=0x%X entries num = %u\\n\",\n+\t\t(uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);\n+\treturn 0;\n+err:\n+\tmlx5_compress_qp_release(dev, qp_id);\n+\treturn -1;\n+}\n+\n static struct rte_compressdev_ops mlx5_compress_ops = {\n \t.dev_configure\t\t= mlx5_compress_dev_configure,\n \t.dev_start\t\t= NULL,\n@@ -85,8 +229,8 @@ struct mlx5_compress_priv {\n \t.dev_infos_get\t\t= mlx5_compress_dev_info_get,\n \t.stats_get\t\t= NULL,\n \t.stats_reset\t\t= NULL,\n-\t.queue_pair_setup\t= NULL,\n-\t.queue_pair_release\t= NULL,\n+\t.queue_pair_setup\t= mlx5_compress_qp_setup,\n+\t.queue_pair_release\t= mlx5_compress_qp_release,\n \t.private_xform_create\t= NULL,\n \t.private_xform_free\t= NULL,\n \t.stream_create\t\t= NULL,\n", "prefixes": [ "v3", "05/11" ] }