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{
    "id": 86962,
    "url": "https://patches.dpdk.org/api/patches/86962/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-5-git-send-email-matan@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1611142175-409485-5-git-send-email-matan@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1611142175-409485-5-git-send-email-matan@nvidia.com",
    "date": "2021-01-20T11:29:28",
    "name": "[v3,04/11] common/mlx5: add compress primitives",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d6eea371af4675ab973c56fc2d97c6683cb990bf",
    "submitter": {
        "id": 1911,
        "url": "https://patches.dpdk.org/api/people/1911/?format=api",
        "name": "Matan Azrad",
        "email": "matan@nvidia.com"
    },
    "delegate": {
        "id": 6690,
        "url": "https://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1611142175-409485-5-git-send-email-matan@nvidia.com/mbox/",
    "series": [
        {
            "id": 14865,
            "url": "https://patches.dpdk.org/api/series/14865/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14865",
            "date": "2021-01-20T11:29:24",
            "name": "add mlx5 compress PMD",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/14865/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/86962/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/86962/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 84CDFA0A05;\n\tWed, 20 Jan 2021 12:34:00 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4EE92140CF1;\n\tWed, 20 Jan 2021 12:34:00 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 4D2BA140CF0\n for <dev@dpdk.org>; Wed, 20 Jan 2021 12:33:58 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 20 Jan 2021 13:33:55 +0200",
            "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10KBTfXB001381;\n Wed, 20 Jan 2021 13:33:55 +0200"
        ],
        "From": "Matan Azrad <matan@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>, akhil.goyal@nxp.com",
        "Date": "Wed, 20 Jan 2021 11:29:28 +0000",
        "Message-Id": "<1611142175-409485-5-git-send-email-matan@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1611142175-409485-1-git-send-email-matan@nvidia.com>",
        "References": "<1610554690-411627-1-git-send-email-matan@nvidia.com>\n <1611142175-409485-1-git-send-email-matan@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v3 04/11] common/mlx5: add compress primitives",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add the GGA compress WQE related structures and definitions.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 41 +++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 39 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 72c843f..8809b92 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -412,10 +412,23 @@ struct mlx5_cqe_ts {\n \tuint8_t op_own;\n };\n \n+/* GGA */\n /* MMO metadata segment */\n \n-#define\tMLX5_OPCODE_MMO\t0x2f\n-#define\tMLX5_OPC_MOD_MMO_REGEX 0x4\n+#define\tMLX5_OPCODE_MMO\t0x2fu\n+#define\tMLX5_OPC_MOD_MMO_REGEX 0x4u\n+#define\tMLX5_OPC_MOD_MMO_COMP 0x2u\n+#define\tMLX5_OPC_MOD_MMO_DECOMP 0x3u\n+#define\tMLX5_OPC_MOD_MMO_DMA 0x1u\n+\n+#define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u\n+#define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u\n+#define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u\n+#define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u\n+#define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)\n+#define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u\n+#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u\n+#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u\n \n struct mlx5_wqe_metadata_seg {\n \tuint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */\n@@ -423,6 +436,30 @@ struct mlx5_wqe_metadata_seg {\n \tuint64_t addr;\n };\n \n+struct mlx5_gga_wqe {\n+\tuint32_t opcode;\n+\tuint32_t sq_ds;\n+\tuint32_t flags;\n+\tuint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */\n+\tuint32_t gga_ctrl2;\n+\tuint32_t opaque_lkey;\n+\tuint64_t opaque_vaddr;\n+\tstruct mlx5_wqe_dseg gather;\n+\tstruct mlx5_wqe_dseg scatter;\n+} __rte_packed;\n+\n+struct mlx5_gga_compress_opaque {\n+\tuint32_t syndrom;\n+\tuint32_t reserved0;\n+\tuint32_t scattered_length;\n+\tuint32_t gathered_length;\n+\tuint64_t scatter_crc;\n+\tuint64_t gather_crc;\n+\tuint32_t crc32;\n+\tuint32_t adler32;\n+\tuint8_t reserved1[216];\n+} __rte_packed;\n+\n struct mlx5_ifc_regexp_mmo_control_bits {\n \tuint8_t reserved_at_31[0x2];\n \tuint8_t le[0x1];\n",
    "prefixes": [
        "v3",
        "04/11"
    ]
}