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GET /api/patches/86821/?format=api
{ "id": 86821, "url": "https://patches.dpdk.org/api/patches/86821/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210118203508.1332-2-aboyer@pensando.io/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210118203508.1332-2-aboyer@pensando.io>", "list_archive_url": "https://inbox.dpdk.org/dev/20210118203508.1332-2-aboyer@pensando.io", "date": "2021-01-18T20:34:56", "name": "[01/13] net/ionic: strip out unneeded interrupt code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "df754173c15a2678b4dad647fc1f3a84f1294e2e", "submitter": { "id": 2036, "url": "https://patches.dpdk.org/api/people/2036/?format=api", "name": "Andrew Boyer", "email": "aboyer@pensando.io" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210118203508.1332-2-aboyer@pensando.io/mbox/", "series": [ { "id": 14820, "url": "https://patches.dpdk.org/api/series/14820/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14820", "date": "2021-01-18T20:34:55", "name": "net/ionic: fixes and optimizations", "version": 1, "mbox": "https://patches.dpdk.org/series/14820/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/86821/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/86821/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 98992A0A03;\n\tMon, 18 Jan 2021 21:35:38 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 83DE3140E2A;\n\tMon, 18 Jan 2021 21:35:38 +0100 (CET)", "from mail-pj1-f41.google.com (mail-pj1-f41.google.com\n [209.85.216.41])\n by mails.dpdk.org (Postfix) with ESMTP id 65A6C140E25\n for <dev@dpdk.org>; Mon, 18 Jan 2021 21:35:35 +0100 (CET)", "by mail-pj1-f41.google.com with SMTP id g15so6312069pjd.2\n for <dev@dpdk.org>; Mon, 18 Jan 2021 12:35:35 -0800 (PST)", "from driver-dev1.pensando.io ([12.226.153.42])\n by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.33\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 18 Jan 2021 12:35:33 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=B4UI11kE2DNoQedH08fP0vqG/hiVRwSZOAYmeDV4EOk=;\n b=ZNY31uba3qlHeZWIrRTjitJjW7r2Ys5rfBCTaYJLE6vhUyjPsuG+xu+SDwdcYf3ERL\n 54MwYRxYd3lG3LOdRHxFs6wN4q+nq+Ln2DdctCI8pzfPe6WmOtQIVkCZtqhtkKvbYabz\n IbKVfc/SCDnRuxavn74diKSg16NQl0lRoh4Pi8zJ/bdDJrspxghnxuiw0mtvxG5K/3LH\n UUp1y/eebLX7Jp76Qf7ALPsV8tDjJE4LRKHZi10uRYzKaKQDSVtha1yd1NHhoCVHRP+v\n iczmblbf18OIKIVPHVEGi4i+VcWs+WzKUzaVNX0Hi6z4IPI85mIy9eLFIusqXpZpljiw\n 6taQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=B4UI11kE2DNoQedH08fP0vqG/hiVRwSZOAYmeDV4EOk=;\n b=ALNQ2/R4+WdY8idpOZecbL9u3Ft935HlaxRQJ0a/OFjKim3XnQgBwrPlKhx8qwNjKh\n D485uWwVJU0KnEm9/8SP1PpFkrfsBG4WVFghl+kASnWpjTpyU1YU/uyWT/0YCS5ez98Z\n oNWzhkIFbX0kYJWNQtqLNwjZMrUZbsi/6jNVcfOJ0/LWtjvjyjUQdXOb89UuIzql61Bt\n wpfAToY4GAyH8zrqYVZWaZD9JWY/q3s/Qc9R85ZcRMK0qUMPCRpwkHYbzuaVGhNLkVSY\n SoxJ9XUX7FJqwDWVHapH9trdlo1WRJxWW76Cbx7B4VgOXO5OJ5+CR7eheSW2RZLHQ8cg\n CM2w==", "X-Gm-Message-State": "AOAM533mksP3j3rJB1Gk9KXgFObgozMy/WECdE2hqAlFu0GCH/alDKjf\n OOeGFIpNvbbNzdPfvuhBi0LuSUbSvutl4A==", "X-Google-Smtp-Source": "\n ABdhPJwhAGKdSHASgbNTy2w5x8yHRbIQzxxnkf9lMMN5zn8HXnokS+y2adH5FdAmP8weCasjPlcUQg==", "X-Received": "by 2002:a17:90a:9603:: with SMTP id\n v3mr1172794pjo.128.1611002134253;\n Mon, 18 Jan 2021 12:35:34 -0800 (PST)", "From": "Andrew Boyer <aboyer@pensando.io>", "To": "dev@dpdk.org", "Cc": "Alfredo Cardigliano <cardigliano@ntop.org>,\n Andrew Boyer <aboyer@pensando.io>", "Date": "Mon, 18 Jan 2021 12:34:56 -0800", "Message-Id": "<20210118203508.1332-2-aboyer@pensando.io>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210118203508.1332-1-aboyer@pensando.io>", "References": "<20210118203508.1332-1-aboyer@pensando.io>", "Subject": "[dpdk-dev] [PATCH 01/13] net/ionic: strip out unneeded interrupt\n code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Only the NotifyQ uses an interrupt, so simplify the other queues.\n\nSimplify ionic_dev_cmd_adminq_init() and ionic_cq_init().\nMove ionic_intr_alloc() into ionic_notify_qcq_alloc().\nCreate ionic_lif_notifyq_deinit().\nSimplify ionic_lif_qcq_deinit().\nRemove unneeded flags and defines.\n\nSigned-off-by: Andrew Boyer <aboyer@pensando.io>\n---\n drivers/net/ionic/ionic_dev.c | 8 +--\n drivers/net/ionic/ionic_dev.h | 12 ++--\n drivers/net/ionic/ionic_lif.c | 116 ++++++++++++++++------------------\n drivers/net/ionic/ionic_lif.h | 2 -\n 4 files changed, 59 insertions(+), 79 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c\nindex 4b5e24f98c..3507d4166f 100644\n--- a/drivers/net/ionic/ionic_dev.c\n+++ b/drivers/net/ionic/ionic_dev.c\n@@ -323,9 +323,7 @@ ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,\n }\n \n void\n-ionic_dev_cmd_adminq_init(struct ionic_dev *idev,\n-\t\tstruct ionic_qcq *qcq,\n-\t\tuint16_t intr_index)\n+ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq)\n {\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_cq *cq = &qcq->cq;\n@@ -335,7 +333,7 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev,\n \t\t.q_init.type = q->type,\n \t\t.q_init.index = q->index,\n \t\t.q_init.flags = IONIC_QINIT_F_ENA,\n-\t\t.q_init.intr_index = intr_index,\n+\t\t.q_init.intr_index = IONIC_INTR_NONE,\n \t\t.q_init.ring_size = rte_log2_u32(q->num_descs),\n \t\t.q_init.ring_base = q->base_pa,\n \t\t.q_init.cq_ring_base = cq->base_pa,\n@@ -348,7 +346,6 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev,\n \n int\n ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,\n-\t\tstruct ionic_intr_info *intr,\n \t\tuint32_t num_descs, size_t desc_size)\n {\n \tif (desc_size == 0) {\n@@ -365,7 +362,6 @@ ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,\n \t}\n \n \tcq->lif = lif;\n-\tcq->bound_intr = intr;\n \tcq->num_descs = num_descs;\n \tcq->desc_size = desc_size;\n \tcq->tail_idx = 0;\ndiff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 6588a373fc..6ee2918959 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -165,11 +165,9 @@ struct ionic_queue {\n \tstruct ionic_doorbell __iomem *db;\n };\n \n-#define IONIC_INTR_INDEX_NOT_ASSIGNED\t(-1)\n-#define IONIC_INTR_NAME_MAX_SZ\t\t(32)\n+#define IONIC_INTR_NONE\t\t(-1)\n \n struct ionic_intr_info {\n-\tchar name[IONIC_INTR_NAME_MAX_SZ];\n \tint index;\n \tuint32_t vector;\n \tstruct ionic_intr __iomem *ctrl;\n@@ -184,7 +182,6 @@ struct ionic_cq {\n \tbool done_color;\n \tvoid *base;\n \trte_iova_t base_pa;\n-\tstruct ionic_intr_info *bound_intr;\n };\n \n /** ionic_admin_ctx - Admin command context.\n@@ -234,15 +231,14 @@ void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type,\n \tuint8_t ver);\n void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr);\n void ionic_dev_cmd_lif_reset(struct ionic_dev *idev);\n-void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,\n-\tuint16_t intr_index);\n+\n+void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq);\n \n struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif,\n \tstruct ionic_queue *q);\n \n int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,\n-\tstruct ionic_intr_info *intr, uint32_t num_descs,\n-\tsize_t desc_size);\n+\tuint32_t num_descs, size_t desc_size);\n void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa);\n void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);\n typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint32_t cq_desc_index,\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex f39b54e8ef..856e977186 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -20,7 +20,6 @@ ionic_qcq_enable(struct ionic_qcq *qcq)\n {\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = q->lif;\n-\tstruct ionic_dev *idev = &lif->adapter->idev;\n \tstruct ionic_admin_ctx ctx = {\n \t\t.pending_work = true,\n \t\t.cmd.q_control = {\n@@ -31,11 +30,6 @@ ionic_qcq_enable(struct ionic_qcq *qcq)\n \t\t},\n \t};\n \n-\tif (qcq->flags & IONIC_QCQ_F_INTR) {\n-\t\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n-\t\t\tIONIC_INTR_MASK_CLEAR);\n-\t}\n-\n \treturn ionic_adminq_post_wait(lif, &ctx);\n }\n \n@@ -44,7 +38,6 @@ ionic_qcq_disable(struct ionic_qcq *qcq)\n {\n \tstruct ionic_queue *q = &qcq->q;\n \tstruct ionic_lif *lif = q->lif;\n-\tstruct ionic_dev *idev = &lif->adapter->idev;\n \tstruct ionic_admin_ctx ctx = {\n \t\t.pending_work = true,\n \t\t.cmd.q_control = {\n@@ -55,11 +48,6 @@ ionic_qcq_disable(struct ionic_qcq *qcq)\n \t\t},\n \t};\n \n-\tif (qcq->flags & IONIC_QCQ_F_INTR) {\n-\t\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n-\t\t\tIONIC_INTR_MASK_SET);\n-\t}\n-\n \treturn ionic_adminq_post_wait(lif, &ctx);\n }\n \n@@ -584,7 +572,7 @@ ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)\n void\n ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)\n {\n-\tif (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)\n+\tif (intr->index != IONIC_INTR_NONE)\n \t\tlif->adapter->intrs[intr->index] = false;\n }\n \n@@ -640,7 +628,8 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \tnew->q.info = rte_zmalloc(\"ionic\", sizeof(*new->q.info) * num_descs, 0);\n \tif (!new->q.info) {\n \t\tIONIC_PRINT(ERR, \"Cannot allocate queue info\");\n-\t\treturn -ENOMEM;\n+\t\terr = -ENOMEM;\n+\t\tgoto err_out_free_qcq;\n \t}\n \n \tnew->q.type = type;\n@@ -649,25 +638,13 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \t\tdesc_size, sg_desc_size);\n \tif (err) {\n \t\tIONIC_PRINT(ERR, \"Queue initialization failed\");\n-\t\treturn err;\n+\t\tgoto err_out_free_info;\n \t}\n \n-\tif (flags & IONIC_QCQ_F_INTR) {\n-\t\terr = ionic_intr_alloc(lif, &new->intr);\n-\t\tif (err)\n-\t\t\treturn err;\n-\n-\t\tionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,\n-\t\t\tIONIC_INTR_MASK_SET);\n-\t} else {\n-\t\tnew->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;\n-\t}\n-\n-\terr = ionic_cq_init(lif, &new->cq, &new->intr,\n-\t\tnum_descs, cq_desc_size);\n+\terr = ionic_cq_init(lif, &new->cq, num_descs, cq_desc_size);\n \tif (err) {\n \t\tIONIC_PRINT(ERR, \"Completion queue initialization failed\");\n-\t\tgoto err_out_free_intr;\n+\t\tgoto err_out_free_info;\n \t}\n \n \tnew->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,\n@@ -677,7 +654,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \tif (!new->base_z) {\n \t\tIONIC_PRINT(ERR, \"Cannot reserve queue DMA memory\");\n \t\terr = -ENOMEM;\n-\t\tgoto err_out_free_intr;\n+\t\tgoto err_out_free_info;\n \t}\n \n \tnew->base = new->base_z->addr;\n@@ -709,9 +686,10 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \n \treturn 0;\n \n-err_out_free_intr:\n-\tif (flags & IONIC_QCQ_F_INTR)\n-\t\tionic_intr_free(lif, &new->intr);\n+err_out_free_info:\n+\trte_free(new->q.info);\n+err_out_free_qcq:\n+\trte_free(new);\n \n \treturn err;\n }\n@@ -800,21 +778,32 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif)\n static int\n ionic_notify_qcq_alloc(struct ionic_lif *lif)\n {\n-\tuint32_t flags;\n+\tstruct ionic_qcq *nqcq;\n+\tstruct ionic_dev *idev = &lif->adapter->idev;\n+\tuint32_t flags = 0;\n \tint err = -ENOMEM;\n \n-\tflags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;\n-\n \terr = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, \"notify\",\n \t\tflags,\n \t\tIONIC_NOTIFYQ_LENGTH,\n \t\tsizeof(struct ionic_notifyq_cmd),\n \t\tsizeof(union ionic_notifyq_comp),\n \t\t0,\n-\t\t&lif->notifyqcq);\n+\t\t&nqcq);\n \tif (err)\n \t\treturn err;\n \n+\terr = ionic_intr_alloc(lif, &nqcq->intr);\n+\tif (err) {\n+\t\tionic_qcq_free(nqcq);\n+\t\treturn err;\n+\t}\n+\n+\tionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,\n+\t\tIONIC_INTR_MASK_SET);\n+\n+\tlif->notifyqcq = nqcq;\n+\n \treturn 0;\n }\n \n@@ -1040,30 +1029,36 @@ ionic_lif_rss_teardown(struct ionic_lif *lif)\n }\n \n static void\n-ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)\n+ionic_lif_qcq_deinit(struct ionic_qcq *qcq)\n {\n-\tstruct ionic_dev *idev = &lif->adapter->idev;\n-\n-\tif (!(qcq->flags & IONIC_QCQ_F_INITED))\n-\t\treturn;\n-\n-\tif (qcq->flags & IONIC_QCQ_F_INTR)\n-\t\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n-\t\t\tIONIC_INTR_MASK_SET);\n-\n \tqcq->flags &= ~IONIC_QCQ_F_INITED;\n }\n \n void\n ionic_lif_txq_deinit(struct ionic_qcq *qcq)\n {\n-\tionic_lif_qcq_deinit(qcq->lif, qcq);\n+\tionic_lif_qcq_deinit(qcq);\n }\n \n void\n ionic_lif_rxq_deinit(struct ionic_qcq *qcq)\n {\n-\tionic_lif_qcq_deinit(qcq->lif, qcq);\n+\tionic_lif_qcq_deinit(qcq);\n+}\n+\n+static void\n+ionic_lif_notifyq_deinit(struct ionic_lif *lif)\n+{\n+\tstruct ionic_qcq *nqcq = lif->notifyqcq;\n+\tstruct ionic_dev *idev = &lif->adapter->idev;\n+\n+\tif (!(nqcq->flags & IONIC_QCQ_F_INITED))\n+\t\treturn;\n+\n+\tionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,\n+\t\tIONIC_INTR_MASK_SET);\n+\n+\tnqcq->flags &= ~IONIC_QCQ_F_INITED;\n }\n \n bool\n@@ -1227,7 +1222,7 @@ ionic_lif_adminq_init(struct ionic_lif *lif)\n \tstruct ionic_q_init_comp comp;\n \tint err;\n \n-\tionic_dev_cmd_adminq_init(idev, qcq, qcq->intr.index);\n+\tionic_dev_cmd_adminq_init(idev, qcq);\n \terr = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);\n \tif (err)\n \t\treturn err;\n@@ -1242,10 +1237,6 @@ ionic_lif_adminq_init(struct ionic_lif *lif)\n \tIONIC_PRINT(DEBUG, \"adminq->hw_index %d\", q->hw_index);\n \tIONIC_PRINT(DEBUG, \"adminq->db %p\", q->db);\n \n-\tif (qcq->flags & IONIC_QCQ_F_INTR)\n-\t\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n-\t\t\tIONIC_INTR_MASK_CLEAR);\n-\n \tqcq->flags |= IONIC_QCQ_F_INITED;\n \n \treturn 0;\n@@ -1292,9 +1283,8 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)\n \tIONIC_PRINT(DEBUG, \"notifyq->hw_index %d\", q->hw_index);\n \tIONIC_PRINT(DEBUG, \"notifyq->db %p\", q->db);\n \n-\tif (qcq->flags & IONIC_QCQ_F_INTR)\n-\t\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n-\t\t\tIONIC_INTR_MASK_CLEAR);\n+\tionic_intr_mask(idev->intr_ctrl, qcq->intr.index,\n+\t\tIONIC_INTR_MASK_CLEAR);\n \n \tqcq->flags |= IONIC_QCQ_F_INITED;\n \n@@ -1372,7 +1362,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)\n \t\t\t.type = q->type,\n \t\t\t.index = q->index,\n \t\t\t.flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,\n-\t\t\t.intr_index = cq->bound_intr->index,\n+\t\t\t.intr_index = IONIC_INTR_NONE,\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n \t\t\t.ring_base = q->base_pa,\n \t\t\t.cq_ring_base = cq->base_pa,\n@@ -1418,7 +1408,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)\n \t\t\t.type = q->type,\n \t\t\t.index = q->index,\n \t\t\t.flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,\n-\t\t\t.intr_index = cq->bound_intr->index,\n+\t\t\t.intr_index = IONIC_INTR_NONE,\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n \t\t\t.ring_base = q->base_pa,\n \t\t\t.cq_ring_base = cq->base_pa,\n@@ -1544,10 +1534,10 @@ ionic_lif_init(struct ionic_lif *lif)\n \tionic_rx_filters_deinit(lif);\n \n err_out_notifyq_deinit:\n-\tionic_lif_qcq_deinit(lif, lif->notifyqcq);\n+\tionic_lif_notifyq_deinit(lif);\n \n err_out_adminq_deinit:\n-\tionic_lif_qcq_deinit(lif, lif->adminqcq);\n+\tionic_lif_qcq_deinit(lif->adminqcq);\n \n \treturn err;\n }\n@@ -1560,8 +1550,8 @@ ionic_lif_deinit(struct ionic_lif *lif)\n \n \tionic_rx_filters_deinit(lif);\n \tionic_lif_rss_teardown(lif);\n-\tionic_lif_qcq_deinit(lif, lif->notifyqcq);\n-\tionic_lif_qcq_deinit(lif, lif->adminqcq);\n+\tionic_lif_notifyq_deinit(lif);\n+\tionic_lif_qcq_deinit(lif->adminqcq);\n \n \tlif->state &= ~IONIC_LIF_F_INITED;\n }\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex 4f48845eb9..d245c6da01 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -48,8 +48,6 @@ struct ionic_rx_stats {\n \n #define IONIC_QCQ_F_INITED\tBIT(0)\n #define IONIC_QCQ_F_SG\t\tBIT(1)\n-#define IONIC_QCQ_F_INTR\tBIT(2)\n-#define IONIC_QCQ_F_NOTIFYQ\tBIT(3)\n #define IONIC_QCQ_F_DEFERRED\tBIT(4)\n \n /* Queue / Completion Queue */\n", "prefixes": [ "01/13" ] }