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GET /api/patches/86795/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 86795,
    "url": "https://patches.dpdk.org/api/patches/86795/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1610969353-31938-4-git-send-email-xuemingl@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1610969353-31938-4-git-send-email-xuemingl@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1610969353-31938-4-git-send-email-xuemingl@nvidia.com",
    "date": "2021-01-18T11:29:07",
    "name": "[v3,3/9] net/mlx5: revert setting bonding representor to first PF",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b46768cc08b0695c0a81dbe3839b7dfdb10b5824",
    "submitter": {
        "id": 1904,
        "url": "https://patches.dpdk.org/api/people/1904/?format=api",
        "name": "Xueming Li",
        "email": "xuemingl@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1610969353-31938-4-git-send-email-xuemingl@nvidia.com/mbox/",
    "series": [
        {
            "id": 14810,
            "url": "https://patches.dpdk.org/api/series/14810/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14810",
            "date": "2021-01-18T11:29:04",
            "name": "net/mlx5: support SubFunction representor",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/14810/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/86795/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/86795/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E3F50A0A03;\n\tMon, 18 Jan 2021 12:29:41 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5954F140DE4;\n\tMon, 18 Jan 2021 12:29:25 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id C9C8A140DC2\n for <dev@dpdk.org>; Mon, 18 Jan 2021 12:29:19 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n xuemingl@nvidia.com) with SMTP; 18 Jan 2021 13:29:15 +0200",
            "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10IBTFed026901;\n Mon, 18 Jan 2021 13:29:15 +0200"
        ],
        "From": "Xueming Li <xuemingl@nvidia.com>",
        "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Cc": "dev@dpdk.org, Matan Azrad <matan@nvidia.com>,\n Shahaf Shuler <shahafs@nvidia.com>,\n Thomas Monjalon <thomas@monjalon.net>, xuemingl@nvidia.com,\n Asaf Penso <asafp@nvidia.com>",
        "Date": "Mon, 18 Jan 2021 11:29:07 +0000",
        "Message-Id": "<1610969353-31938-4-git-send-email-xuemingl@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": [
            "<1610969353-31938-1-git-send-email-xuemingl@nvidia.com>",
            "<1608304614-13908-2-git-send-email-xuemingl@nvidia.com>"
        ],
        "References": [
            "<1610969353-31938-1-git-send-email-xuemingl@nvidia.com>",
            "<1608304614-13908-2-git-send-email-xuemingl@nvidia.com>"
        ],
        "Subject": "[dpdk-dev] [PATCH v3 3/9] net/mlx5: revert setting bonding\n representor to first PF",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "With kernel bonding, representors on second PF are being probed by\ndevargs:\n\t<primary_bdf>,representor=pf1vf<N>\nNo need to save primary PF port ID and lookup when probing sibling\nports, revert patch [1]\n\n[1]:\ncommit e6818853c022 (\"net/mlx5: set representor to first PF in bonding\nmode\")\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 20 ++------------------\n drivers/net/mlx5/mlx5.c          |  1 -\n drivers/net/mlx5/mlx5.h          |  1 -\n 3 files changed, 2 insertions(+), 20 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex b2776c080a..7b320e8b72 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -816,13 +816,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\trte_errno = ENOMEM;\n \t\t\treturn NULL;\n \t\t}\n-\t\tpriv = eth_dev->data->dev_private;\n-\t\tif (priv->sh->bond_dev != UINT16_MAX)\n-\t\t\t/* For bonding port, use primary PCI device. */\n-\t\t\teth_dev->device =\n-\t\t\t\trte_eth_devices[priv->sh->bond_dev].device;\n-\t\telse\n-\t\t\teth_dev->device = dpdk_dev;\n+\t\teth_dev->device = dpdk_dev;\n \t\teth_dev->dev_ops = &mlx5_dev_sec_ops;\n \t\teth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;\n \t\teth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;\n@@ -1439,17 +1433,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \teth_dev->data->dev_private = priv;\n \tpriv->dev_data = eth_dev->data;\n \teth_dev->data->mac_addrs = priv->mac;\n-\tif (spawn->pf_bond < 0) {\n-\t\teth_dev->device = dpdk_dev;\n-\t} else {\n-\t\t/* Use primary bond PCI as device. */\n-\t\tif (sh->bond_dev == UINT16_MAX) {\n-\t\t\tsh->bond_dev = eth_dev->data->port_id;\n-\t\t\teth_dev->device = dpdk_dev;\n-\t\t} else {\n-\t\t\teth_dev->device = rte_eth_devices[sh->bond_dev].device;\n-\t\t}\n-\t}\n+\teth_dev->device = dpdk_dev;\n \teth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;\n \t/* Configure the first MAC address by default. */\n \tif (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e245276fce..5e8cd6a3df 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -914,7 +914,6 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tgoto error;\n \t}\n \tsh->refcnt = 1;\n-\tsh->bond_dev = UINT16_MAX;\n \tsh->max_port = spawn->max_port;\n \tstrncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),\n \t\tsizeof(sh->ibdev_name) - 1);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 3836a9696c..e06e0ff3bb 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -668,7 +668,6 @@ struct mlx5_flex_parser_profiles {\n struct mlx5_dev_ctx_shared {\n \tLIST_ENTRY(mlx5_dev_ctx_shared) next;\n \tuint32_t refcnt;\n-\tuint16_t bond_dev; /* Bond primary device id. */\n \tuint32_t devx:1; /* Opened with DV. */\n \tuint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n",
    "prefixes": [
        "v3",
        "3/9"
    ]
}