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GET /api/patches/86731/?format=api
{ "id": 86731, "url": "https://patches.dpdk.org/api/patches/86731/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210117102123.19045-9-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210117102123.19045-9-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210117102123.19045-9-shirik@nvidia.com", "date": "2021-01-17T10:21:22", "name": "[v7,8/9] net/mlx5: add GENEVE TLV option flow translation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e665508dfcc760a99102bb6a53eadc66af714eac", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210117102123.19045-9-shirik@nvidia.com/mbox/", "series": [ { "id": 14793, "url": "https://patches.dpdk.org/api/series/14793/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14793", "date": "2021-01-17T10:21:14", "name": "ethdev: introduce GENEVE header TLV option item", "version": 7, "mbox": "https://patches.dpdk.org/series/14793/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/86731/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/86731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A340EA09E4;\n\tSun, 17 Jan 2021 11:23:01 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BC591140DFC;\n\tSun, 17 Jan 2021 11:22:25 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 365AF140DF9\n for <dev@dpdk.org>; Sun, 17 Jan 2021 11:22:23 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 17 Jan 2021 12:22:19 +0200", "from nvidia.com (c-141-140-1-007.mtl.labs.mlnx [10.141.140.7])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10HALkmN003653;\n Sun, 17 Jan 2021 12:22:19 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com,\n andrew.rybchenko@oktetlabs.ru", "Date": "Sun, 17 Jan 2021 12:21:22 +0200", "Message-Id": "<20210117102123.19045-9-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20210117102123.19045-1-shirik@nvidia.com>", "References": "<20210114070743.2377-1-shirik@nvidia.com>\n <20210117102123.19045-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v7 8/9] net/mlx5: add GENEVE TLV option flow\n translation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The GENEVE TLV option matching flows must be created\nusing a translation function.\n\nThis function checks whether we already created a Devx\nobject for the matching and either creates the objects\nor updates the reference counter.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 2 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 85 +++++++++++++++++++++++++++++++++\n 2 files changed, 86 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 4c68c65f4f..a9e33b8ab8 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -330,7 +330,7 @@ enum mlx5_feature_name {\n #define MLX5_GENEVE_VER_VAL(a) \\\n \t\t(((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))\n #define MLX5_GENEVE_OPTLEN_MASK 0x3F\n-#define MLX5_GENEVE_OPTLEN_SHIFT 7\n+#define MLX5_GENEVE_OPTLEN_SHIFT 8\n #define MLX5_GENEVE_OPTLEN_VAL(a) \\\n \t (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))\n #define MLX5_GENEVE_OAMF_MASK 0x1\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 86c9d2cbbd..936ddfa92f 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7416,6 +7416,80 @@ flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+/**\n+ * Add Geneve TLV option item to matcher.\n+ *\n+ * @param[in, out] dev\n+ * Pointer to rte_eth_dev structure.\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ */\n+static int\n+flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,\n+\t\t\t\t void *key, const struct rte_flow_item *item,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;\n+\tconst struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;\n+\tvoid *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);\n+\tvoid *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n+\tvoid *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\tmisc_parameters_3);\n+\tvoid *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);\n+\trte_be32_t opt_data_key = 0, opt_data_mask = 0;\n+\tint ret = 0;\n+\n+\tif (!geneve_opt_v)\n+\t\treturn -1;\n+\tif (!geneve_opt_m)\n+\t\tgeneve_opt_m = &rte_flow_item_geneve_opt_mask;\n+\tret = flow_dev_geneve_tlv_option_resource_register(dev, item,\n+\t\t\t\t\t\t\t error);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to create geneve_tlv_obj\");\n+\t\treturn ret;\n+\t}\n+\t/*\n+\t * Set the option length in GENEVE header if not requested.\n+\t * The GENEVE TLV option length is expressed by the option length field\n+\t * in the GENEVE header.\n+\t * If the option length was not requested but the GENEVE TLV option item\n+\t * is present we set the option length field implicitly.\n+\t */\n+\tif (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {\n+\t\tMLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,\n+\t\t\t MLX5_GENEVE_OPTLEN_MASK);\n+\t\tMLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,\n+\t\t\t geneve_opt_v->option_len + 1);\n+\t}\n+\t/* Set the data. */\n+\tif (geneve_opt_v->data) {\n+\t\tmemcpy(&opt_data_key, geneve_opt_v->data,\n+\t\t\tRTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),\n+\t\t\t\tsizeof(opt_data_key)));\n+\t\tMLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=\n+\t\t\t\tsizeof(opt_data_key));\n+\t\tmemcpy(&opt_data_mask, geneve_opt_m->data,\n+\t\t\tRTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),\n+\t\t\t\tsizeof(opt_data_mask)));\n+\t\tMLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=\n+\t\t\t\tsizeof(opt_data_mask));\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_m,\n+\t\t\t\tgeneve_tlv_option_0_data,\n+\t\t\t\trte_be_to_cpu_32(opt_data_mask));\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_v,\n+\t\t\t\tgeneve_tlv_option_0_data,\n+\t\t\trte_be_to_cpu_32(opt_data_key & opt_data_mask));\n+\t}\n+\treturn ret;\n+}\n+\n /**\n * Add MPLS item to matcher and to the value.\n *\n@@ -10739,6 +10813,17 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tmatcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);\n \t\t\tlast_item = MLX5_FLOW_LAYER_GENEVE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GENEVE_OPT:\n+\t\t\tret = flow_dv_translate_item_geneve_opt(dev, match_mask,\n+\t\t\t\t\t\t\t match_value,\n+\t\t\t\t\t\t\t items, error);\n+\t\t\tif (ret)\n+\t\t\t\treturn rte_flow_error_set(error, -ret,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t\"cannot create GENEVE TLV option\");\n+\t\t\tflow->geneve_tlv_option = 1;\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GENEVE_OPT;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_MPLS:\n \t\t\tflow_dv_translate_item_mpls(match_mask, match_value,\n \t\t\t\t\t\t items, last_item, tunnel);\n", "prefixes": [ "v7", "8/9" ] }