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{
    "id": 8607,
    "url": "https://patches.dpdk.org/api/patches/8607/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446568728-12220-6-git-send-email-danielx.t.mrzyglod@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1446568728-12220-6-git-send-email-danielx.t.mrzyglod@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1446568728-12220-6-git-send-email-danielx.t.mrzyglod@intel.com",
    "date": "2015-11-03T16:38:46",
    "name": "[dpdk-dev,v3,5/7] i40e: add additional ieee1588 support functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e9a726ac26eb97fa62ee301ba0f5064f97d8be7b",
    "submitter": {
        "id": 23,
        "url": "https://patches.dpdk.org/api/people/23/?format=api",
        "name": "Daniel Mrzyglod",
        "email": "danielx.t.mrzyglod@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446568728-12220-6-git-send-email-danielx.t.mrzyglod@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/8607/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/8607/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D5CB58EA1;\n\tTue,  3 Nov 2015 17:45:43 +0100 (CET)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 4F89D8E9A\n\tfor <dev@dpdk.org>; Tue,  3 Nov 2015 17:45:42 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby fmsmga101.fm.intel.com with ESMTP; 03 Nov 2015 08:45:40 -0800",
            "from unknown ([10.217.248.15])\n\tby orsmga002.jf.intel.com with SMTP; 03 Nov 2015 08:45:36 -0800",
            "by  (sSMTP sendmail emulation); Tue, 03 Nov 2015 17:44:32 +0100"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,239,1444719600\"; d=\"scan'208\";a=\"841651665\"",
        "From": "Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue,  3 Nov 2015 17:38:46 +0100",
        "Message-Id": "<1446568728-12220-6-git-send-email-danielx.t.mrzyglod@intel.com>",
        "X-Mailer": "git-send-email 2.1.4",
        "In-Reply-To": "<1446568728-12220-1-git-send-email-danielx.t.mrzyglod@intel.com>",
        "References": "<1443799208-9408-1-git-send-email-danielx.t.mrzyglod@intel.com>\n\t<1446568728-12220-1-git-send-email-danielx.t.mrzyglod@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 5/7] i40e: add additional ieee1588 support\n\tfunctions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pablo de Lara <pablo.de.lara.guarch@intel.com>\n\nAdd additional functions to support the existing IEEE1588\nfunctionality and to enable getting, setting and adjusting\nthe device time.\n\nSigned-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>\nSigned-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 192 ++++++++++++++++++++++++++++++++++++-----\n drivers/net/i40e/i40e_ethdev.h |   5 ++\n 2 files changed, 177 insertions(+), 20 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 5a9f11d..f1c36a8 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -129,11 +129,13 @@\n \t(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \\\n \t(1UL << RTE_ETH_FLOW_L2_PAYLOAD))\n \n-#define I40E_PTP_40GB_INCVAL  0x0199999999ULL\n-#define I40E_PTP_10GB_INCVAL  0x0333333333ULL\n-#define I40E_PTP_1GB_INCVAL   0x2000000000ULL\n-#define I40E_PRTTSYN_TSYNENA  0x80000000\n-#define I40E_PRTTSYN_TSYNTYPE 0x0e000000\n+/* Additional timesync values. */\n+#define I40E_PTP_40GB_INCVAL     0x0199999999ULL\n+#define I40E_PTP_10GB_INCVAL     0x0333333333ULL\n+#define I40E_PTP_1GB_INCVAL      0x2000000000ULL\n+#define I40E_PRTTSYN_TSYNENA     0x80000000\n+#define I40E_PRTTSYN_TSYNTYPE    0x0e000000\n+#define I40E_CYCLECOUNTER_MASK   0xffffffffffffffff\n \n #define I40E_MAX_PERCENT            100\n #define I40E_DEFAULT_DCB_APP_NUM    1\n@@ -268,6 +270,11 @@ static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t   struct timespec *timestamp);\n static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);\n+static int i40e_timesync_time_adjust(struct rte_eth_dev *dev, int64_t delta);\n+static int i40e_timesync_time_get(struct rte_eth_dev *dev,\n+\t\t\t\t  struct timespec *timestamp);\n+static int i40e_timesync_time_set(struct rte_eth_dev *dev,\n+\t\t\t\t  struct timespec *timestamp);\n \n \n static const struct rte_pci_id pci_id_i40e_map[] = {\n@@ -332,6 +339,9 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,\n \t.timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,\n \t.get_dcb_info                 = i40e_dev_get_dcb_info,\n+\t.timesync_time_adjust         = i40e_timesync_time_adjust,\n+\t.timesync_time_get            = i40e_timesync_time_get,\n+\t.timesync_time_set            = i40e_timesync_time_set,\n };\n \n /* store statistics names and its offset in stats structure */\n@@ -6742,17 +6752,95 @@ i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)\n \treturn 0;\n }\n \n-static int\n-i40e_timesync_enable(struct rte_eth_dev *dev)\n+/*\n+ * Adds the new cycles (in nanoseconds) to the previous time stored.\n+ */\n+static uint64_t\n+timecounter_cycles_to_ns_time(struct timecounter *tc, uint64_t cycle_tstamp)\n+{\n+\tuint64_t delta = (cycle_tstamp - tc->cycle_last);\n+\tuint64_t nsec = tc->nsec;\n+\n+\tnsec += delta;\n+\n+\treturn nsec;\n+}\n+\n+static uint64_t\n+i40e_read_timesync_cyclecounter(struct rte_eth_dev *dev)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tstruct rte_eth_link *link = &dev->data->dev_link;\n-\tuint32_t tsync_ctl_l;\n-\tuint32_t tsync_ctl_h;\n+\tuint64_t systim_cycles = 0;\n+\n+\tsystim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);\n+\tsystim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)\n+\t\t\t<< 32;\n+\n+\treturn systim_cycles;\n+}\n+\n+static uint64_t\n+timecounter_read_ns_delta(struct rte_eth_dev *dev)\n+{\n+\tuint64_t cycle_now, cycle_delta;\n+\tstruct i40e_adapter *adapter =\n+\t\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\n+\t/* Read cycle counter. */\n+\tcycle_now = adapter->tc.cc->read(dev);\n+\n+\t/* Calculate the delta since the last timecounter_read_delta(). */\n+\tcycle_delta = (cycle_now - adapter->tc.cycle_last);\n+\n+\t/* Update time stamp of timecounter_read_delta() call. */\n+\tadapter->tc.cycle_last = cycle_now;\n+\n+\t/* Delta already in nanoseconds. */\n+\treturn cycle_delta;\n+}\n+\n+static uint64_t\n+timecounter_read(struct rte_eth_dev *dev)\n+{\n+\tuint64_t nsec;\n+\tstruct i40e_adapter *adapter =\n+\t\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\n+\t/* Increment time by nanoseconds since last call. */\n+\tnsec = timecounter_read_ns_delta(dev);\n+\tnsec += adapter->tc.nsec;\n+\tadapter->tc.nsec = nsec;\n+\n+\treturn nsec;\n+}\n+\n+static void\n+timecounter_init(struct rte_eth_dev *dev,\n+\t\t      uint64_t start_time)\n+{\n+\tstruct i40e_adapter *adapter =\n+\t\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\tadapter->tc.cc = &adapter->cc;\n+\tadapter->tc.cycle_last = adapter->tc.cc->read(dev);\n+\tadapter->tc.nsec = start_time;\n+}\n+\n+static void\n+i40e_start_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_adapter *adapter =\n+\t\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\tstruct rte_eth_link link;\n \tuint32_t tsync_inc_l;\n \tuint32_t tsync_inc_h;\n \n-\tswitch (link->link_speed) {\n+\t/* Get current link speed. */\n+\tmemset(&link, 0, sizeof(link));\n+\ti40e_dev_link_update(dev, 1);\n+\trte_i40e_dev_atomic_read_link_status(dev, &link);\n+\n+\tswitch (link.link_speed) {\n \tcase ETH_LINK_SPEED_40G:\n \t\ttsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;\n \t\ttsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;\n@@ -6770,6 +6858,63 @@ i40e_timesync_enable(struct rte_eth_dev *dev)\n \t\ttsync_inc_h = 0x0;\n \t}\n \n+\t/* Set the timesync increment value. */\n+\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);\n+\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);\n+\n+\tmemset(&adapter->cc, 0, sizeof(struct cyclecounter));\n+\tadapter->cc.read = i40e_read_timesync_cyclecounter;\n+}\n+\n+static int\n+i40e_timesync_time_adjust(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct i40e_adapter *adapter =\n+\t\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\n+\tadapter->tc.nsec += delta;\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_timesync_time_set(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\n+\tns = timespec_to_ns(ts);\n+\n+\t/* Reset the timecounter. */\n+\ttimecounter_init(dev, ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_timesync_time_get(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\n+\tns = timecounter_read(dev);\n+\t*ts = ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_timesync_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t tsync_ctl_l;\n+\tuint32_t tsync_ctl_h;\n+\tuint64_t ns;\n+\tstruct timespec zerotime = {0, 0};\n+\n+\t/* Set 0.0 epoch time to initialize timecounter. */\n+\tns = timespec_to_ns(&zerotime);\n+\ti40e_start_cyclecounter(dev);\n+\ttimecounter_init(dev, ns);\n+\n \t/* Clear timesync registers. */\n \tI40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);\n \tI40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n@@ -6779,10 +6924,6 @@ i40e_timesync_enable(struct rte_eth_dev *dev)\n \tI40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));\n \tI40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n \n-\t/* Set the timesync increment value. */\n-\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);\n-\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);\n-\n \t/* Enable timestamping of PTP packets. */\n \ttsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);\n \ttsync_ctl_l |= I40E_PRTTSYN_TSYNENA;\n@@ -6814,7 +6955,7 @@ i40e_timesync_disable(struct rte_eth_dev *dev)\n \tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);\n \tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);\n \n-\t/* Set the timesync increment value. */\n+\t/* Reset the timesync increment value. */\n \tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);\n \tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);\n \n@@ -6826,10 +6967,14 @@ i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\tstruct timespec *timestamp, uint32_t flags)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_adapter *adapter =\n+\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\n \tuint32_t sync_status;\n \tuint32_t rx_stmpl;\n \tuint32_t rx_stmph;\n \tuint32_t index = flags & 0x03;\n+\tuint64_t regival = 0;\n \n \tsync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);\n \tif ((sync_status & (1 << index)) == 0)\n@@ -6837,9 +6982,11 @@ i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \n \trx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));\n \trx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));\n+\ttimecounter_read(dev);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tregival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n+\tregival = timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = ns_to_timespec(regival);\n \n \treturn  0;\n }\n@@ -6849,9 +6996,13 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\tstruct timespec *timestamp)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_adapter *adapter =\n+\t\t(struct i40e_adapter *)dev->data->dev_private;\n+\n \tuint32_t sync_status;\n \tuint32_t tx_stmpl;\n \tuint32_t tx_stmph;\n+\tuint64_t regival = 0;\n \n \tsync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);\n \tif ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)\n@@ -6860,8 +7011,9 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \ttx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);\n \ttx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tregival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n+\tregival = timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = ns_to_timespec(regival);\n \n \treturn  0;\n }\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex de3b9d9..500f1f5 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -35,6 +35,7 @@\n #define _I40E_ETHDEV_H_\n \n #include <rte_eth_ctrl.h>\n+#include <rte_ptp.h>\n \n #define I40E_VLAN_TAG_SIZE        4\n \n@@ -502,6 +503,10 @@ struct i40e_adapter {\n \tbool rx_vec_allowed;\n \tbool tx_simple_allowed;\n \tbool tx_vec_allowed;\n+\n+\t/* for PTP */\n+\tstruct cyclecounter cc;\n+\tstruct timecounter tc;\n };\n \n int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "5/7"
    ]
}