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GET /api/patches/85927/?format=api
{ "id": 85927, "url": "https://patches.dpdk.org/api/patches/85927/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-15-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201231072247.5719-15-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201231072247.5719-15-pnalla@marvell.com", "date": "2020-12-31T07:22:46", "name": "[14/15] net/octeontx_ep: rx queue interrupt", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "88fca70e707f8ad7193dc8082325c866274d4c5a", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-15-pnalla@marvell.com/mbox/", "series": [ { "id": 14507, "url": "https://patches.dpdk.org/api/series/14507/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14507", "date": "2020-12-31T07:22:32", "name": "Octeon Tx/Tx2 Endpoint pmd", "version": 1, "mbox": "https://patches.dpdk.org/series/14507/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85927/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/85927/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0E811A0A00;\n\tThu, 31 Dec 2020 08:25:36 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D82DA140D56;\n\tThu, 31 Dec 2020 08:23:17 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7EB5A140CEE\n for <dev@dpdk.org>; Thu, 31 Dec 2020 08:23:01 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BV7G0IQ022182 for <dev@dpdk.org>; Wed, 30 Dec 2020 23:23:00 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx58-4\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 30 Dec 2020 23:23:00 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:22:59 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:22:58 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 30 Dec 2020 23:22:59 -0800", "from localhost.localdomain (unknown [10.111.145.157])\n by maili.marvell.com (Postfix) with ESMTP id C925C3F7044;\n Wed, 30 Dec 2020 23:22:58 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=JWM7Ibp+hGXAZFYkQ0+b2Y7eUz+J7TGFPqbK5FOnHzI=;\n b=gdDraC++5v9IwCvbCaBNLP6birfwYkvUZVh6PpIEtJhtxyrv6qekRDIES69ej+5vIvot\n vC5i0buKK6mr5TgljVSwZIkHc9jmDC47x380enEgYUvXGsNEBuzB2911Jil61xoLZfEj\n IoDF1SdWcMobCdCNEgCuIB+m6HuMXkWUSE+xUa+ab6LEmyb4uXmJbdyz1TpLVp2h+Gkc\n nuPa7jnHoVxSwTMjB4hwuVzQp7iYWFe3tJQuctUC0ZLX0Q334aWdKK1JmmnoBLS74MXB\n dIsO7VvobeViATOBzel/k5miEw2bMicbt42uJp+hFH/nT8ZuNsA/yj1QUgLMtF8JKU3n 3Q==", "From": "\"Nalla, Pradeep\" <pnalla@marvell.com>", "To": "\"Nalla, Pradeep\" <pnalla@marvell.com>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 31 Dec 2020 07:22:46 +0000", "Message-ID": "<20201231072247.5719-15-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201231072247.5719-1-pnalla@marvell.com>", "References": "<20201231072247.5719-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-31_02:2020-12-30,\n 2020-12-31 signatures=0", "Subject": "[dpdk-dev] [PATCH 14/15] net/octeontx_ep: rx queue interrupt", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"Nalla Pradeep\" <pnalla@marvell.com>\n\nAdded rx queue interrupt enable and disable operations. These functions\nare supported on both otx and otx2 platforms. Application can make use\nof these functions and wait on event at packet reception.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx2_ep_vf.c | 63 ++++++\n drivers/net/octeontx_ep/otx2_ep_vf.h | 26 +++\n drivers/net/octeontx_ep/otx_ep_common.h | 53 +++++\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 255 ++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.c | 66 ++++++\n drivers/net/octeontx_ep/otx_ep_vf.h | 25 +++\n 6 files changed, 488 insertions(+)", "diff": "diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c\nindex b570a49566..0fb8c26a5e 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c\n@@ -2,6 +2,7 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <rte_ethdev_driver.h>\n #include \"otx2_common.h\"\n #include \"otx_ep_common.h\"\n #include \"otx2_ep_vf.h\"\n@@ -282,6 +283,33 @@ otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep)\n \t}\n }\n \n+static uint32_t\n+otx2_vf_update_read_index(struct otx_ep_instr_queue *iq)\n+{\n+\tuint32_t new_idx = rte_read32(iq->inst_cnt_reg);\n+\n+\tif (new_idx == 0xFFFFFFFF) {\n+\t\totx_ep_dbg(\"%s Going to reset IQ index\\n\", __func__);\n+\t\trte_write32(new_idx, iq->inst_cnt_reg);\n+\t}\n+\n+\t/* The new instr cnt reg is a 32-bit counter that can roll over.\n+\t * We have noted the counter's initial value at init time into\n+\t * reset_instr_cnt\n+\t */\n+\tif (iq->reset_instr_cnt < new_idx)\n+\t\tnew_idx -= iq->reset_instr_cnt;\n+\telse\n+\t\tnew_idx += (0xffffffff - iq->reset_instr_cnt) + 1;\n+\n+\t/* Modulo of the new index with the IQ size will give us\n+\t * the new index.\n+\t */\n+\tnew_idx %= iq->nb_desc;\n+\n+\treturn new_idx;\n+}\n+\n static const struct otx_ep_config default_otx2_ep_conf = {\n \t/* IQ attributes */\n \t.iq = {\n@@ -313,6 +341,38 @@ otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)\n \treturn default_conf;\n }\n \n+static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\tunion out_int_lvl_t out_int_lvl;\n+\tunion out_cnts_t out_cnts;\n+\n+\tout_int_lvl.s.time_cnt_en = 1;\n+\tout_int_lvl.s.cnt = 0;\n+\totx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +\n+\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\tout_cnts.d64 = 0;\n+\tout_cnts.s.resend = 1;\n+\totx2_write64(out_cnts.d64, otx_epvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\treturn 0;\n+}\n+\n+static int otx2_vf_disable_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\tunion out_int_lvl_t out_int_lvl;\n+\n+\t/* Disable the interrupt for this queue */\n+\tout_int_lvl.d64 = otx2_read64(otx_epvf->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\tout_int_lvl.s.time_cnt_en = 0;\n+\tout_int_lvl.s.cnt = 0;\n+\totx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +\n+\t\t\tSDP_VF_R_OUT_INT_LEVELS(q_no));\n+\n+\treturn 0;\n+}\n+\n int\n otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n {\n@@ -340,6 +400,7 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \totx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs;\n \n \totx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;\n+\totx_ep->fn_list.update_iq_read_idx = otx2_vf_update_read_index;\n \n \totx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues;\n \totx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues;\n@@ -349,6 +410,8 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx_ep->fn_list.enable_oq = otx2_vf_enable_oq;\n \totx_ep->fn_list.disable_oq = otx2_vf_disable_oq;\n+\totx_ep->fn_list.enable_rxq_intr = otx2_vf_enable_rxq_intr;\n+\totx_ep->fn_list.disable_rxq_intr = otx2_vf_disable_rxq_intr;\n \n \treturn 0;\n }\ndiff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h\nindex 3a3b3413b2..64a505afdb 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.h\n@@ -26,5 +26,31 @@ struct otx2_ep_instr_64B {\n \tuint64_t exhdr[4];\n };\n \n+union out_int_lvl_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timet:22;\n+\t\tuint64_t max_len:7;\n+\t\tuint64_t max_len_en:1;\n+\t\tuint64_t time_cnt_en:1;\n+\t\tuint64_t bmode:1;\n+\t} s;\n+};\n+\n+union out_cnts_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timer:22;\n+\t\tuint64_t rsvd:5;\n+\t\tuint64_t resend:1;\n+\t\tuint64_t mbox_int:1;\n+\t\tuint64_t in_int:1;\n+\t\tuint64_t out_int:1;\n+\t\tuint64_t send_ism:1;\n+\t} s;\n+};\n+\n #endif /*_OTX2_EP_VF_H_ */\n \ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 0b6e7e2042..fdd31c889d 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -122,6 +122,37 @@ typedef union otx_ep_instr_ih {\n \t} s;\n } otx_ep_instr_ih_t;\n \n+\n+\n+typedef union otx_ep_resp_hdr {\n+\tuint64_t u64;\n+\tstruct {\n+\t /** The request id for a packet thats in response\n+\t * to pkt sent by host.\n+\t */\n+\t\tuint64_t request_id:16;\n+\n+\t /** Reserved. */\n+\t\tuint64_t reserved:2;\n+\n+\t /** checksum verified. */\n+\t\tuint64_t csum_verified:2;\n+\n+\t /** The destination Queue port. */\n+\t\tuint64_t dest_qport:22;\n+\n+\t /** The source port for a packet thats in response\n+\t * to pkt sent by host.\n+\t */\n+\t\tuint64_t src_port:6;\n+\n+\t /** Opcode for this packet. */\n+\t\tuint64_t opcode:16;\n+\t} s;\n+} otx_ep_resp_hdr_t;\n+\n+#define OTX_EP_RESP_HDR_SIZE (sizeof(otx_ep_resp_hdr_t))\n+\n /* OTX_EP IQ request list */\n struct otx_ep_instr_list {\n \tvoid *buf;\n@@ -210,6 +241,17 @@ struct otx_ep_instr_queue {\n \tconst struct rte_memzone *iq_mz;\n };\n \n+/* DROQ packet format for application i/f. */\n+struct otx_ep_droq_pkt {\n+\t/* DROQ packet data buffer pointer. */\n+\tuint8_t\t *data;\n+\n+\t/* DROQ packet data length */\n+\tuint32_t len;\n+\n+\tuint32_t misc;\n+};\n+\n /** Descriptor format.\n * The descriptor ring is made of descriptors which have 2 64-bit values:\n * -# Physical (bus) address of the data buffer.\n@@ -395,6 +437,7 @@ struct otx_ep_fn_list {\n \tvoid (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \n \tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n+\tuint32_t (*update_iq_read_idx)(struct otx_ep_instr_queue *iq);\n \n \tvoid (*enable_io_queues)(struct otx_ep_device *otx_ep);\n \tvoid (*disable_io_queues)(struct otx_ep_device *otx_ep);\n@@ -404,6 +447,8 @@ struct otx_ep_fn_list {\n \n \tvoid (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \tvoid (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\tint (*enable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);\n+\tint (*disable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);\n };\n \n /* SRIOV information */\n@@ -508,8 +553,16 @@ struct otx_ep_buf_free_info {\n \tstruct otx_ep_gather g;\n };\n \n+int\n+otx_ep_register_irq(struct rte_intr_handle *intr_handle, unsigned int vec);\n+\n+void\n+otx_ep_unregister_irq(struct rte_intr_handle *intr_handle, unsigned int vec);\n+\n #define OTX_EP_MAX_PKT_SZ 64000U\n #define OTX_EP_MAX_MAC_ADDRS 1\n #define OTX_EP_SG_ALIGN 8\n \n+#define SDP_VF_R_MSIX_START (0x0)\n+#define SDP_VF_R_MSIX(ring) (SDP_VF_R_MSIX_START + (ring))\n #endif /* _OTX_EP_COMMON_H_ */\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex 1739bae765..d37a4c1c5a 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -2,6 +2,7 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <rte_ethdev_driver.h>\n #include <rte_ethdev_pci.h>\n #include <rte_malloc.h>\n #include <rte_io.h>\n@@ -12,6 +13,14 @@\n #include \"otx2_ep_vf.h\"\n #include \"otx_ep_rxtx.h\"\n \n+#include <linux/vfio.h>\n+#include <sys/eventfd.h>\n+#include <sys/ioctl.h>\n+#include <unistd.h>\n+\n+#define MAX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID\n+#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \\\n+\t\tsizeof(int) * (MAX_INTR_VEC_ID))\n #define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)\n \n static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {\n@@ -186,6 +195,55 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \treturn -ENOMEM;\n }\n \n+static int otx_epvf_setup_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\tstruct rte_eth_dev *eth_dev = otx_epvf->eth_dev;\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = SDP_VF_R_MSIX(q_no);\n+\n+\trc = otx_ep_register_irq(handle, vec);\n+\tif (rc) {\n+\t\totx_ep_err(\"Fail to register Rx irq, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tif (!handle->intr_vec) {\n+\t\thandle->intr_vec = rte_zmalloc(\"intr_vec\",\n+\t\t\t\t otx_epvf->max_rx_queues *\n+\t\t\t\t sizeof(int), 0);\n+\t\tif (!handle->intr_vec) {\n+\t\t\totx_ep_err(\"Failed to allocate %d rx intr_vec\",\n+\t\t\t\t otx_epvf->max_rx_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\t/* VFIO vector zero is resereved for misc interrupt so\n+\t * doing required adjustment.\n+\t */\n+\thandle->intr_vec[q_no] = RTE_INTR_VEC_RXTX_OFFSET + vec;\n+\n+\treturn rc;\n+}\n+\n+static void otx_epvf_unset_rxq_intr(struct otx_ep_device *otx_epvf,\n+\t\t\t\t uint16_t q_no)\n+{\n+\t/* Not yet implemented */\n+\tstruct rte_eth_dev *eth_dev = otx_epvf->eth_dev;\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = SDP_VF_R_MSIX(q_no);\n+\totx_epvf->fn_list.disable_rxq_intr(otx_epvf, q_no);\n+\totx_ep_unregister_irq(handle, vec);\n+}\n+\n static int\n otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n {\n@@ -195,6 +253,7 @@ otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n \tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n \tstruct rte_eth_txmode *txmode = &conf->txmode;\n \tuint32_t ethdev_queues;\n+\tuint16_t q;\n \n \tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n \tif (eth_dev->data->nb_rx_queues > ethdev_queues ||\n@@ -209,9 +268,177 @@ otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n \totx_epvf->rx_offloads = rxmode->offloads;\n \totx_epvf->tx_offloads = txmode->offloads;\n \n+\tif (eth_dev->data->dev_conf.intr_conf.rxq) {\n+\t\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++)\n+\t\t\totx_epvf_setup_rxq_intr(otx_epvf, q);\n+\t}\n \treturn 0;\n }\n \n+static int\n+irq_get_info(struct rte_intr_handle *intr_handle)\n+{\n+\tstruct vfio_irq_info irq = { .argsz = sizeof(irq) };\n+\tint rc;\n+\n+\tirq.index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);\n+\tif (rc < 0) {\n+\t\totx_ep_err(\"Failed to get IRQ info rc=%d errno=%d\", rc, errno);\n+\t\treturn rc;\n+\t}\n+\n+\totx_ep_dbg(\"Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x\",\n+\t\t irq.flags, irq.index, irq.count, MAX_INTR_VEC_ID);\n+\n+\tif (irq.count > MAX_INTR_VEC_ID) {\n+\t\totx_ep_err(\"HW max=%d > MAX_INTR_VEC_ID: %d\",\n+\t\t\t intr_handle->max_intr, MAX_INTR_VEC_ID);\n+\t\tintr_handle->max_intr = MAX_INTR_VEC_ID;\n+\t} else {\n+\t\tintr_handle->max_intr = irq.count;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+irq_init(struct rte_intr_handle *intr_handle)\n+{\n+\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n+\tstruct vfio_irq_set *irq_set;\n+\tint32_t *fd_ptr;\n+\tint len, rc;\n+\tuint32_t i;\n+\n+\tif (intr_handle->max_intr > MAX_INTR_VEC_ID) {\n+\t\totx_ep_err(\"Max_intr=%d greater than MAX_INTR_VEC_ID=%d\",\n+\t\t\t intr_handle->max_intr, MAX_INTR_VEC_ID);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\tlen = sizeof(struct vfio_irq_set) +\n+\t\tsizeof(int32_t) * intr_handle->max_intr;\n+\n+\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n+\tirq_set->argsz = len;\n+\tirq_set->start = 0;\n+\tirq_set->count = intr_handle->max_intr;\n+\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n+\t\t\t VFIO_IRQ_SET_ACTION_TRIGGER;\n+\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\tfd_ptr = (int32_t *)&irq_set->data[0];\n+\tfor (i = 0; i < irq_set->count; i++)\n+\t\tfd_ptr[i] = -1;\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n+\tif (rc)\n+\t\totx_ep_err(\"Failed to set irqs vector rc=%d\", rc);\n+\n+\treturn rc;\n+}\n+\n+static int\n+irq_config(struct rte_intr_handle *intr_handle, unsigned int vec)\n+{\n+\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n+\tstruct vfio_irq_set *irq_set;\n+\tint32_t *fd_ptr;\n+\tint len, rc;\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx_ep_err(\"vector=%d greater than max_intr=%d\", vec,\n+\t\t\t intr_handle->max_intr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tlen = sizeof(struct vfio_irq_set) + sizeof(int32_t);\n+\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n+\tirq_set->argsz = len;\n+\tirq_set->start = vec;\n+\tirq_set->count = 1;\n+\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n+\t\t\t VFIO_IRQ_SET_ACTION_TRIGGER;\n+\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\t/* Use vec fd to set interrupt vectors */\n+\tfd_ptr = (int32_t *)&irq_set->data[0];\n+\tfd_ptr[0] = intr_handle->efds[vec];\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n+\tif (rc)\n+\t\totx_ep_err(\"Failed to set_irqs vector=0x%x rc=%d\", vec, rc);\n+\n+\treturn rc;\n+}\n+\n+int\n+otx_ep_register_irq(struct rte_intr_handle *intr_handle, unsigned int vec)\n+{\n+\tstruct rte_intr_handle tmp_handle;\n+\n+\t/* If no max_intr read from VFIO */\n+\tif (intr_handle->max_intr == 0) {\n+\t\tirq_get_info(intr_handle);\n+\t\tirq_init(intr_handle);\n+\t}\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx_ep_err(\"Vector=%d greater than max_intr=%d\", vec,\n+\t\t\t intr_handle->max_intr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttmp_handle = *intr_handle;\n+\t/* Create new eventfd for interrupt vector */\n+\ttmp_handle.fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n+\tif (tmp_handle.fd == -1)\n+\t\treturn -ENODEV;\n+\n+\tintr_handle->efds[vec] = tmp_handle.fd;\n+\tintr_handle->nb_efd = ((vec + 1) > intr_handle->nb_efd) ?\n+\t\t\t (vec + 1) : intr_handle->nb_efd;\n+\tintr_handle->max_intr = RTE_MAX(intr_handle->nb_efd + 1,\n+\t\t\t\t\tintr_handle->max_intr);\n+\n+\totx_ep_dbg(\"Enable vector:0x%x for vfio (efds: %d, max:%d)\",\n+\t\t vec, intr_handle->nb_efd, intr_handle->max_intr);\n+\n+\t/* Enable MSIX vectors to VFIO */\n+\treturn irq_config(intr_handle, vec);\n+}\n+\n+/**\n+ * @internal\n+ * Unregister IRQ\n+ */\n+void\n+otx_ep_unregister_irq(struct rte_intr_handle *intr_handle, unsigned int vec)\n+{\n+\tstruct rte_intr_handle tmp_handle;\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx_ep_err(\"Error unregistering MSI-X interrupts vec:%d > %d\",\n+\t\t\tvec, intr_handle->max_intr);\n+\t\treturn;\n+\t}\n+\n+\ttmp_handle = *intr_handle;\n+\ttmp_handle.fd = intr_handle->efds[vec];\n+\tif (tmp_handle.fd == -1)\n+\t\treturn;\n+\n+\totx_ep_dbg(\"Disable vector:0x%x for vfio (efds: %d, max:%d)\",\n+\t\t\tvec, intr_handle->nb_efd, intr_handle->max_intr);\n+\n+\tif (intr_handle->efds[vec] != -1)\n+\t\tclose(intr_handle->efds[vec]);\n+\t/* Disable MSIX vectors from VFIO */\n+\tintr_handle->efds[vec] = -1;\n+\tirq_config(intr_handle, vec);\n+}\n /**\n * Setup our receive queue/ringbuffer. This is the\n * queue the Octeon uses to send us packets and\n@@ -429,6 +656,26 @@ otx_ep_dev_stats_reset(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static int otx_ep_dev_rxq_irq_enable(struct rte_eth_dev *dev,\n+\t\t\t\t uint16_t rx_queue_id)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(dev);\n+\tint rc;\n+\n+\trc = otx_epvf->fn_list.enable_rxq_intr(otx_epvf, rx_queue_id);\n+\treturn rc;\n+}\n+\n+static int otx_ep_dev_rxq_irq_disable(struct rte_eth_dev *dev,\n+\t\t\t\t uint16_t rx_queue_id)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(dev);\n+\tint rc;\n+\n+\trc = otx_epvf->fn_list.disable_rxq_intr(otx_epvf, rx_queue_id);\n+\treturn rc;\n+}\n+\n /* Define our ethernet definitions */\n static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.dev_configure\t\t= otx_ep_dev_configure,\n@@ -442,6 +689,8 @@ static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.stats_get\t\t= otx_ep_dev_stats_get,\n \t.stats_reset\t\t= otx_ep_dev_stats_reset,\n \t.dev_infos_get\t\t= otx_ep_dev_info_get,\n+\t.rx_queue_intr_enable = otx_ep_dev_rxq_irq_enable,\n+\t.rx_queue_intr_disable = otx_ep_dev_rxq_irq_disable,\n };\n \n \n@@ -483,11 +732,17 @@ static int\n otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n {\n \tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\tuint16_t q;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \totx_epdev_exit(eth_dev);\n \n+\tif (eth_dev->data->dev_conf.intr_conf.rxq) {\n+\t\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++)\n+\t\t\totx_epvf_unset_rxq_intr(otx_epvf, q);\n+\t}\n+\n \totx_epvf->port_configured = 0;\n \n \tif (eth_dev->data->mac_addrs != NULL)\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c\nindex 4a00736dab..a7c9d48dbc 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.c\n@@ -324,6 +324,33 @@ otx_ep_disable_io_queues(struct otx_ep_device *otx_ep)\n \t}\n }\n \n+static uint32_t\n+otx_ep_update_read_index(struct otx_ep_instr_queue *iq)\n+{\n+\tuint32_t new_idx = rte_read32(iq->inst_cnt_reg);\n+\n+\tif (new_idx == 0xFFFFFFFF) {\n+\t\totx_ep_dbg(\"%s Going to reset IQ index\\n\", __func__);\n+\t\trte_write32(new_idx, iq->inst_cnt_reg);\n+\t}\n+\n+\t/* The new instr cnt reg is a 32-bit counter that can roll over.\n+\t * We have noted the counter's initial value at init time into\n+\t * reset_instr_cnt\n+\t */\n+\tif (iq->reset_instr_cnt < new_idx)\n+\t\tnew_idx -= iq->reset_instr_cnt;\n+\telse\n+\t\tnew_idx += (0xffffffff - iq->reset_instr_cnt) + 1;\n+\n+\t/* Modulo of the new index with the IQ size will give us\n+\t * the new index.\n+\t */\n+\tnew_idx %= iq->nb_desc;\n+\n+\treturn new_idx;\n+}\n+\n /* OTX_EP default configuration */\n static const struct otx_ep_config default_otx_ep_conf = {\n \t/* IQ attributes */\n@@ -358,6 +385,41 @@ otx_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)\n \treturn default_conf;\n }\n \n+static int otx_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf __rte_unused,\n+\t\t\t\t uint16_t q_no __rte_unused)\n+{\n+\tunion otx_out_int_lvl_t out_int_lvl;\n+\tunion otx_out_cnts_t out_cnts;\n+\n+\tout_int_lvl.d64 = rte_read64(otx_epvf->hw_addr +\n+\t\t\t\tOTX_EP_R_OUT_INT_LEVELS(q_no));\n+\tout_int_lvl.s.cnt = 0;\n+\totx_ep_write64(out_int_lvl.d64, otx_epvf->hw_addr,\n+\t\t\tOTX_EP_R_OUT_INT_LEVELS(q_no));\n+\n+\tout_cnts.d64 = 0;\n+\tout_cnts.s.resend = 1;\n+\totx_ep_write64(out_cnts.d64, otx_epvf->hw_addr,\n+\t\t OTX_EP_R_OUT_CNTS(q_no));\n+\n+\treturn 0;\n+}\n+\n+static int otx_vf_disable_rxq_intr(struct otx_ep_device *otx_epvf __rte_unused,\n+\t\t\t\t uint16_t q_no __rte_unused)\n+{\n+\tunion otx_out_int_lvl_t out_int_lvl;\n+\n+\t/* Increase the int level so that you get no more interrupts */\n+\tout_int_lvl.d64 = rte_read64(otx_epvf->hw_addr +\n+\t\t\t\tOTX_EP_R_OUT_INT_LEVELS(q_no));\n+\tout_int_lvl.s.cnt = 0xFFFFFFFF;\n+\totx_ep_write64(out_int_lvl.d64, otx_epvf->hw_addr,\n+\t\t\tOTX_EP_R_OUT_INT_LEVELS(q_no));\n+\n+\treturn 0;\n+}\n+\n int\n otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n {\n@@ -385,6 +447,7 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \totx_ep->fn_list.setup_oq_regs = otx_ep_setup_oq_regs;\n \n \totx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;\n+\totx_ep->fn_list.update_iq_read_idx = otx_ep_update_read_index;\n \n \totx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues;\n \totx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues;\n@@ -394,7 +457,10 @@ otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)\n \n \totx_ep->fn_list.enable_oq = otx_ep_enable_oq;\n \totx_ep->fn_list.disable_oq = otx_ep_disable_oq;\n+\totx_ep->fn_list.enable_rxq_intr = otx_vf_enable_rxq_intr;\n+\totx_ep->fn_list.disable_rxq_intr = otx_vf_disable_rxq_intr;\n \n \n \treturn 0;\n }\n+\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.h b/drivers/net/octeontx_ep/otx_ep_vf.h\nindex f91251865b..da1893bc1f 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.h\n@@ -170,4 +170,29 @@ struct otx_ep_instr_64B {\n \n int\n otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);\n+\n+union otx_out_int_lvl_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timet:22;\n+\t\tuint64_t raz:9;\n+\t\tuint64_t bmode:1;\n+\t} s;\n+};\n+\n+union otx_out_cnts_t {\n+\tuint64_t d64;\n+\tstruct {\n+\t\tuint64_t cnt:32;\n+\t\tuint64_t timer:22;\n+\t\tuint64_t rsvd0:5;\n+\t\tuint64_t resend:1;\n+\t\tuint64_t mbox_int:1;\n+\t\tuint64_t in_int:1;\n+\t\tuint64_t out_int:1;\n+\t\tuint64_t rsvd1:1;\n+\t} s;\n+};\n+\n #endif /*_OTX_EP_VF_H_ */\n", "prefixes": [ "14/15" ] }